LTC2355CMSE-14#PBF - ANALOG DEVICES

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

BLOCK DIAGRAM

FEATURES

APPLICATIONS

DESCRIPTION

Serial 12-Bit/14-Bit, 3.5Msps

Sampling ADCs with Shutdown

The LTC

2355-12/LTC2355-14 are 12-bit/14-bit, 3.5Msps

serial ADCs with differential inputs. The devices draw

only 5.5mA from a single 3.3V supply and come in a

tiny 10-lead MSOP package. A Sleep shutdown feature

further reduces power consumption to 13µW. The com-

bination of speed, low power and tiny package makes the

LTC2355-12/LTC2355-14 suitable for high speed, portable

applications.

The 80dB common mode rejection allows users to eliminate

ground loops and common mode noise by measuring

signals differentially from the source.

The devices convert 0V to 2.5V unipolar inputs differentially.

The absolute voltage swing for AIN+ and AIN– extends from

ground to the supply voltage.

The serial interface sends out the conversion results during

the 16 clock cycles following a CONV rising edge for com-

patibility with standard serial interfaces. If two additional

clock cycles for acquisition time are allowed after the data

stream in between conversions, the full sampling rate of

3.5Msps can be achieved with a 63MHz clock.

n 3.5Msps Conversion Rate

n 74.2dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits

n Low Power Dissipation: 18mW

n 3.3V Single Supply Operation

n 2.5V Internal Bandgap Reference can be Overdriven

n 3-Wire SPI-Compatible Serial Interface

n Sleep (13µW) Shutdown Mode

n Nap (4mW) Shutdown Mode

n 80dB Common Mode Rejection

n 0V to 2.5V Unipolar Input Range

n Tiny 10-Lead MSOP Package

n Communications

n Data Acquisition Systems

n Uninterrupted Power Supplies

n Multiphase Motor Control

n Multiplexed Data Acquisition

n RFID

THD, 2nd, 3rd and SFDR

vs Input Frequency

–

S & H

GND

EXPOSED PAD

LTC2355-14

VREF

10µF

AIN–

AIN+

14-BIT ADC

3.3V10µF

14-BIT LATCH

THREE-

STATE

SERIAL

OUTPUT

PORT

2.5V

REFERENCE

TIMING

LOGIC

VDD

SDO

CONV

SCK

2355 TA01

5 6 11

FREQUENCY (MHz)

0.1

–80

THD, 2nd, 3rd (dB)

–74

–68

–62

–56

1 10 100

2355 G02

–86

–92

–98

–104

–110

–50

THD

2nd

3rd

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDD) ..................................................4V

Analog and VREF Input Voltages

(Note 3) ....................................–0.3V to (VDD + 0.3V)

Digital Input Voltages ................... – 0.3V to (VDD + 0.3V)

Digital Output Voltage ...................–0.3V to (VDD + 0.3V)

Power Dissipation ...............................................100mW

Operation Temperature Range

LTC2355C-12/LTC2355C-14 ..................... 0°C to 70°C

LTC2355I-12/LTC2355I-14 ...................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ...................300°C

(Notes 1, 2)

CONVERTER CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. With internal reference. VDD = 3.3V.

PARAMETER CONDITIONS

LTC2355-12 LTC2355-14

UNITSMIN TYP MAX MIN TYP MAX

Resolution (No Missing Codes) l12 14 Bits

Integral Linearity Error (Notes 4, 5, 18) l–2 ±0.25 2 –4 ±0.5 4 LSB

Offset Error (Notes 4, 18) l–10 ±1 10 –20 ±2 20 LSB

Gain Error (Note 4, 18) l–30 ±5 30 –80 ±10 80 LSB

Gain Tempco Internal Reference (Note 4)

External Reference

±15

±1

±15

±1

ppm/°C

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2355CMSE-12#PBF LTC2355CMSE-12#TRPBF LTCVX 10-Lead Plastic MSOP 0°C to 70°C

LTC2355IMSE-12#PBF LTC2355IMSE-12#TRPBF LTCVX 10-Lead Plastic MSOP –40°C to 85°C

LTC2355CMSE-14#PBF LTC2355CMSE-14#TRPBF LTCVY 10-Lead Plastic MSOP 0°C to 70°C

LTC2355IMSE-14#PBF LTC2355IMSE-14#TRPBF LTCVY 10-Lead Plastic MSOP –40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF sufﬁx.

PIN CONFIGURATION

AIN+

AIN–

VREF

GND

CONV

SCK

SDO

VDD

GND

TOP VIEW

GND

MSE PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 40°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

http://www.linear.com/product/LTC2355-12#orderinfo

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

DYNAMIC ACCURACY

The l denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at TA = 25°C with external reference = 2.55V. VDD = 3.3V.

ANALOG INPUT

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at TA = 25°C. With internal reference. VDD = 3.3V.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Differential Input Range (Notes 3, 8, 9) 3.1V ≤ VDD ≤ 3.6V l0 to 2.5 V

VCM Analog Common Mode + Differential

Input Range (Note 10)

0 to VDD V

IIN Analog Input Leakage Current l1 µA

CIN Analog Input Capacitance (Note 19) 13 pF

tACQ Sample-and-Hold Acquisition Time (Note 6) l39 ns

tAP Sample-and-Hold Aperture Delay Time 1 ns

tJITTER Sample-and-Hold Aperture Delay Time Jitter 0.3 ps

CMRR Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 0V to 3V

fIN = 100MHz, VIN = 0V to 3V

–60

–15

SYMBOL PARAMETER CONDITIONS

LTC2355-12 LTC2355-14

UNITSMIN TYP MAX MIN TYP MAX

SINAD Signal-to-Noise Plus

Distortion Ratio

100kHz Input Signal

1.4MHz Input Signal

71.1

74.2

73.8

THD Total Harmonic

Distortion

100kHz First 5 Harmonics

1.4MHz First 5 Harmonics

–86

–82

–76

–86

–82

–78

SFDR Spurious Free

Dynamic Range

100kHz Input Signal

1.4MHz Input Signal

IMD Intermodulation

Distortion

1.25V to 2.5V 1.25MHz into AIN+, 0V to 1.25V,

1.2MHz into AIN––82 –82 dB

Code-to-Code

Transition Noise

VREF = 2.5V (Note 18) 0.25 1 LSBRMS

Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15) 50 50 MHz

Full Linear Bandwidth S/(N + D) ≥ 68dB 5 5 MHz

PARAMETER CONDITIONS MIN TYP MAX UNITS

VREF Output Voltage IOUT = 0 2.5 V

VREF Output Tempco 15 ppm/°C

VREF Line Regulation VDD = 3.1V to 3.6V, VREF = 2.5V 600 µV/V

VREF Output Resistance Load Current = 0.5mA 0.2 Ω

VREF Settling Time CREF = 10µF 2 ms

External VREF Input Range 2.55 VDD V

INTERNAL REFERENCE CHARACTERISTICS

The l denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at TA = 25°C, VDD = 3.3V.

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

POWER REQUIREMENTS

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 17)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD Supply Voltage 3.1 3.3 3.6 V

IDD Supply Current Active Mode

Nap Mode

Sleep Mode (LTC2355-12)

Sleep Mode (LTC2355-14)

5.5

1.1

1.5

µA

PDPower Dissipation 18 mW

DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at TA = 25°C, VDD = 3.3V.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VDD = 3.6V l2.4 V

VIL Low Level Input Voltage VDD = 3.1V l0.6 V

IIN Digital Input Current VIN = 0V to VDD l±10 µA

CIN Digital Input Capacitance 5 pF

VOH High Level Output Voltage VDD = 3.3V, IOUT = –200µA l2.5 2.9 V

VOL Low Level Output Voltage VDD = 3.1V, IOUT= 160µA

VDD = 3.1V, IOUT = 1.6mA

0.05

0.10

0.4

IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VDD l±10 µA

COZ Hi-Z Output Capacitance DOUT 1 pF

ISOURCE Output Short-Circuit Source Current VOUT = 0V, VDD = 3.3V 20 mA

ISINK Output Short-Circuit Sink Current VOUT = VDD = 3.3V 15 mA

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

TIMING CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: When these pins are taken below GND or above VDD, they will be

clamped by internal diodes. This product can handle input currents greater

than 100mA below GND or greater than VDD without latchup.

Note 4: Offset and full-gain speciﬁcations are measured for a single-ended

AIN+ input with AIN– grounded and using the internal 2.5V reference.

Note 5: Integral linearity is tested with an external 2.55V reference and is

deﬁned as the deviation of a code from the straight line passing through

the actual endpoints of a transfer curve. The deviation is measured from

the center of quantization band.

Note 6: Guaranteed by design, not subject to test.

Note 7: Recommended operating conditions.

Note 8: The analog input range is deﬁned for the voltage difference

between AIN+ and AIN–.

Note 9: The absolute voltage at AIN+ and AIN– must be within this range.

Note 10: If less than 3ns is allowed, the output data will appear one

clock cycle later. It is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. VDD = 3.3V.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSAMPLE(MAX) Maximum Sampling Rate per Channel

(Conversion Rate)

l3.5 MHz

tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) l286 ns

tSCK Clock Period (Note 16) l15.872 10000 ns

tCONV Conversion Time (Note 6) 17 18 SCLK cycles

t1Minimum High or Low SCLK Pulse Width (Note 6) 2 ns

t2CONV to SCK Setup Time (Notes 6, 10) 3 ns

t3Nearest SCK Edge Before CONV (Note 6) 0 ns

t4Minimum High or Low CONV Pulse Width (Note 6) 4 ns

t5SCK↑ to Sample Mode (Note 6) 4 ns

t6CONV↑ to Hold Mode (Notes 6, 11) 1.2 ns

t716th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns

t8Delay from SCK to Valid Bits 0 Through 13 (Notes 6, 12) 8 ns

t9SCK↑ to Hi-Z at SDO (Notes 6, 12) 6 ns

t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns

t12 VREF Settling Time After Sleep-to-Wake Transition (Note 14) 2 ms

Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)

because the 2.2ns delay through the sample-and-hold is subtracted from

the CONV to Hold mode delay.

Note 12: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.

Note 13: The time period for acquiring the input signal is started by the

16th rising clock and it is ended by the rising edge of convert.

Note 14: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10µF capacitive load.

Note 15: The full power bandwidth is the frequency where the output code

swing drops to 3dB with a 2.5VP-P input sine wave.

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read with an arbitrarily long clock.

Note 17: VDD = 3.3V, fSAMPLE = 3.5Msps.

Note 18: The LTC2355-14 is measured and speciﬁed with 14-bit resolution

(1LSB = 152µV) and the LTC2355-12 is measured and speciﬁed with

12-bit resolution (1LSB = 610µV).

Note 19: The sampling capacitor at each input accounts for 4.1pF of the

input capacitance.

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

TYPICAL PERFORMANCE CHARACTERISTICS

SINAD vs Input Frequency

THD, 2nd and 3rd vs Input

Frequency

SFDR vs Input Frequency

SNR vs Input Frequency

100kHz Sine Wave 8192 Point

FFT Plot

1.4MHz Sine Wave 8192 Point

FFT Plot

Differential Linearity

vs Output Code

Integral Linearity

vs Output Code

TA = 25°C, VDD = 3.3V (LTC2355-14)

FREQUENCY (MHz)

0.1

SINAD (dB)

1 10 100

2355 G01

FREQUENCY (MHz)

0.1

–80

THD, 2nd, 3rd (dB)

–74

–68

–62

–56

1 10 100

2355 G02

–86

–92

–98

–104

–110

–50

THD

2nd

3rd

FREQUENCY (MHz)

0.1

SFDR (dB)

1 10 100

2355 G03

FREQUENCY (MHz)

0.1

SNR (dB)

1 10 100

2355 G04

FREQUENCY (MHz)

0.00

MAGNITUDE (dB)

–90

–30

–20

–10

0.50 1.00 1.25

2355 G05

–110

–50

–70

–100

–40

–120

–60

–80

0.25 0.75 1.50 1.75

FREQUENCY (MHz)

0.00

MAGNITUDE (dB)

–90

–30

–20

–10

0.50 1.00 1.25

2355 G06

–110

–50

–70

–100

–40

–120

–60

–80

0.25 0.75 1.50 1.75

2355 G07

OUTPUT CODE

–1.0

DIFFERENTIAL LINEARITY (LSB)

–0.8

–0.4

–0.2

1.0

0.4

4096 8192

–0.6

0.6

0.8

0.2

12288 16384

OUTPUT CODE

INTEGRAL LINEARITY (LSB)

16384

2355 G08

–1

–2

–4 4096 8192 12288

–3

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

Differential and Integral Linearity

vs Conversion Rate

SINAD vs Conversion Rate, Input

Frequency = 1.4MHz

2.5VP-P Power Bandwidth

CMRR vs Frequency

PSRR vs Frequency

Internal Reference Voltage vs

Load Current

Internal Reference Voltage

vs VDD

VDD Supply Current vs

Conversion Rate

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VDD = 3.3V (LTC2355-14)

TA = 25°C, VDD = 3.3V (LTC2355-12 and LTC2355-14)

CONVERSION RATE (Msps)

2.0

LINEARITY (LSB)

–1

–2

–3

–4 3.6

2355 G09

2.4 2.8 3.2 4.03.42.2 2.6 3.0 3.8

MAX INL

MAX DNL

MIN INL

MIN DNL

CONVERSION RATE (Msps)

SINAD (dB)

3.6

2355 G10

70 2.2 2.4 2.6 2.8 3 3.2 3.4 3.8 4

FREQUENCY (Hz)

1M 10M 100M 1G

–18

AMPLITUDE (dB)

–12

–6

2355 G11

–24

–30

–36

FREQUENCY (Hz)

100

CMRR (dB)

–20

–40

–60

–80

–100

–120 1k 10k 100k 1M

2355 G12

10M 100M

FREQUENCY (Hz)

1 10

–50

PSRR (dB)

–45

–40

–35

–30

100 1k 10k 100k 1M

2355 G13

–55

–60

–65

–70

–25

LOAD CURRENT (mA)

0.4 0.8 1.2 1.6

2355 G14

2.00.20 0.6 1.0 1.4 1.8

2.4890

REF

(V)

2.4894

2.4898

2.4902

2.4892

2.4896

2.4900

VDD (V)

2.4890

VREF (V)

2.4894

2.4898

2.4902

2.4892

2.4896

2.4900

2.8 3.0 3.2 3.4

2355 G15

2.6 3.6

CONVERSION RATE (Mps)

VDD SUPPLY CURRENT (mA)

0.5

1.5

2.5

3.5

5.5

0.5 1 1.5 2

2355 G16

2.5 3.53 4

4.5

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

PIN FUNCTIONS

AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates fully

differentially with respect to AIN– with a 0V to 2.5V dif-

ferential swing and a 0V to VDD common mode swing.

AIN– (Pin 2): Inverting Analog Input. AIN– operates fully

differentially with respect to AIN+ with a –2.5V to 0V dif-

ferential swing and a 0V to VDD common mode swing.

VREF (Pin 3): 2.5V Internal Reference. Bypass to GND

and to a solid analog ground plane with a 10µF ceramic

capacitor (or 10µF tantalum in parallel with 0.1µF ceramic).

Can be overdriven by an external reference between 2.55V

and VDD.

GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These

ground pins and the exposed pad must be tied directly to

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

ﬂow through these pins.

VDD (Pin 7): 3.3V Positive Supply. This single power pin

supplies 3.3V to the entire device. Bypass to GND and to

a solid analog ground plane with a 10µF ceramic capacitor

(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in

mind that internal analog currents and digital output signal

currents ﬂow through this pin. Care should be taken to

place the 0.1µF bypass capacitor as close to Pins 6 and

7 as possible.

SDO (Pin 8): Three-State Serial Data Output. Each set

of output data words represents the difference between

AIN+ and AIN– analog inputs at the start of the previous

conversion.

SCK (Pin 9): External Clock Input. Advances the conversion

process and sequences the output data on the rising edge.

Responds to TTL (≤3.3V) and 3.3V CMOS levels. One or

more SCK pulses wakes the ADC from sleep mode.

CONV (Pin 10): Convert Start. Holds the analog input signal

and starts the conversion on the rising edge. Responds

to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses

with SCK in ﬁxed high or ﬁxed low state start Nap mode.

Four or more CONV pulses with SCK in ﬁxed high or ﬁxed

low state start Sleep mode.

BLOCK DIAGRAM

2355 BD

–

S & H

GND

EXPOSED PAD

LTC2355-14

VREF

10µF

AIN–

AIN+

14-BIT ADC

3.3V10µF

14-BIT LATCH

THREE-

STATE

SERIAL

OUTPUT

PORT

2.5V

REFERENCE

TIMING

LOGIC

VDD

SDO

CONV

SCK

5 6 11

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

TIMING DIAGRAM

Nap Mode and Sleep Mode Waveforms

SCK to SDO Delay

LTC2355-12 Timing Diagram

LTC2355-14 Timing Diagram

SCK

CONV

INTERNAL

S/H STATUS

SDO

t3t1

11716 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

t8t10

t4t5

t8t9

tACQ

SAMPLE HOLD HOLD

Hi-Z Hi-Z

tCONV

14-BIT DATA WORD

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

*BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.

tTHROUGHPUT

2355 TD01

D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XD9

SAMPLE

SCK

CONV

INTERNAL

S/H STATUS

SDO

t3t1

11716 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

t8t10

t4t5

t8t9

tACQ

SAMPLE HOLD HOLD

Hi-Z Hi-Z

tCONV

14-BIT DATA WORD

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

tTHROUGHPUT

2355 TD01b

D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D11

SAMPLE

SLK

CONV

NAP

SLEEP

VREF

t12

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS 2355 TD02

t10

SCK

SDO

2355 TD03

VIH

VOH

VOL

SCK

SDO

VIH

90%

10%

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

DRIVING THE ANALOG INPUT

The differential analog inputs of the LTC2355-12/LTC2355-14

may be driven differentially or

as a single-ended input (i.e.,

the AIN– input is grounded). Both differential analog in-

puts, AIN+ and AIN–, are sampled at the same instant. Any

unwanted signal that is common to both inputs of each

input pair will be reduced by the common mode rejection

of the sample-and-hold circuit. The inputs draw only one

small current spike while charging the sample-and-hold

capacitors at the end of conversion. During conversion,

the analog inputs draw only a small leakage current. If the

source impedance of the driving circuit is low, then the

LTC2355-12/LTC2355-14 inputs can be driven directly. As

source impedance increases, so will acquisition time. For

minimum acquisition time with high source impedance,

a buffer ampliﬁer must be used. The main requirement is

that the ampliﬁer driving the analog input(s) must settle

after the small current spike before the next conversion

starts (settling time must be 39ns for full throughput rate).

Also keep in mind while choosing an input ampliﬁer the

amount of noise and harmonic distortion added by the

ampliﬁer.

CHOOSING AN INPUT AMPLIFIER

Choosing an input ampliﬁer is easy if a few requirements

are taken into consideration. First, to limit the magnitude of

the voltage spike seen by the ampliﬁer from charging the

sampling capacitor, choose an ampliﬁer that has a low output

impedance (<100Ω) at the closed-loop bandwidth frequency.

For example, if an ampliﬁer is used in a gain of 1 and has a

unity-gain bandwidth of 50MHz, then the output impedance at

50MHz must be less than 100Ω. The second requirement is

that the closed-loop bandwidth must be greater than 40MHz

to ensure adequate small-signal settling for full throughput

rate. If slower op amps are used, more time for settling can

be provided by increasing the time between conversions.

The best choice for an op amp to drive the LTC2355-12/

LTC2355-14 will depend on the application. Generally, ap-

plications fall into two categories: AC applications where

dynamic speciﬁcations are most critical and time domain

applications where DC accuracy and settling time are most

critical. The following list is a summary of the op amps that

are suitable for driving the LTC2355-12/LTC2355-14. (More

APPLICATIONS INFORMATION

detailed information is available in the Linear Technology

Databooks and on the LinearView™ CD-ROM.)

LTC1566-1: Low Noise 2.3MHz Continuous Time Low-

Pass Filter.

1630: Dual 30MHz Rail-to-Rail Voltage FB Ampliﬁer.

2.7V to ±15V supplies. Very high AVOL, 500µV offset and

520ns settling to 0.5LSB for a 4V swing. THD and noise

are –93dB to 40kHz and below 1LSB to 320kHz (AV = 1,

2VP-P into 1kΩ, VS = 5V), making the part excellent for AC

applications (to 1/3 Nyquist) where rail-to-rail performance

is desired. Quad version is available as LT1631.

LT1632: Dual 45MHz Rail-to-Rail Voltage FB Ampliﬁer.

2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and

400ns settling to 0.5LSB for a 4V swing. It is suitable for

applications with a single 5V supply. THD and noise are

–93dB to 40kHz and below 1LSB to 800kHz (AV = 1,

2VP-P into 1kΩ, VS = 5V), making the part excellent for

AC applications where rail-to-rail performance is desired.

Quad version is available as LT1633.

LT1813: Dual 100MHz 750V/µs 3mA Voltage Feedback

Ampliﬁer. 5V to ±5V supplies. Distortion is –86dB to 100kHz

and –77dB to 1MHz with ±5V supplies (2VP-P into 500Ω).

Excellent part for fast AC applications with ±5V supplies.

LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/Ampliﬁer,

8.5nV/√Hz.

LT1806/LT1807: 325MHz GBWP, –80dBc Distortion at 5MHz, Uni-

ty-Gain Stable, R-R In and Out, 10mA/Ampliﬁer, 3.5nV/√Hz.

LT1810: 180MHz GBWP, –90dBc Distortion at 5MHz,

Unity-Gain Stable, R-R In and Out, 15mA/Ampliﬁer, 16nV/√Hz.

LT1818/LT1819: 400MHz, 2500V/µs,9mA, Single/Dual

Voltage Mode Operational Ampliﬁer.

LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 15mA/Amplifier,

0.95nV/√Hz.

LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 3mA/Amplifier,

1.9nV/√Hz.

LT6600-10: Ampliﬁer/Filter Differential In/Out with 10MHz

Cutoff.

LinearView is a trademark of Linear Technology Corporation.

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

APPLICATIONS INFORMATION

INPUT FILTERING AND SOURCE IMPEDANCE

The noise and the distortion of the input ampliﬁer and

other circuitry must be considered since they will add to

the LTC2355-12/LTC2355-14 noise and distortion. The

small-signal bandwidth of the sample-and-hold circuit is

50MHz. Any noise or distortion products that are pres-

ent at the analog inputs will be summed over this entire

bandwidth. Noisy input circuitry should be ﬁltered prior

to the analog inputs to minimize noise. A simple 1-pole

RC ﬁlter is sufﬁcient for many applications. For example,

Figure 1 shows a 47pF capacitor from AIN+ to ground and a

51Ω source resistor to limit the input bandwidth to 47MHz.

The 47pF capacitor also acts as a charge reservoir for the

input sample-and-hold and isolates the ADC input from

sampling-glitch sensitive circuitry. High quality capacitors

and resistors should be used since these components

can add distortion. NPO and silvermica type dielectric

capacitors have excellent linearity. Carbon surface mount

resistors can generate distortion from self heating and

from damage that may occur during soldering. Metal ﬁlm

surface mount resistors are much less susceptible to both

problems. When high amplitude unwanted signals are close

in frequency to the desired signal frequency, a multiple

pole ﬁlter is required. High external source resistance,

combined with the 13pF of input capacitance, will reduce

the rated 50MHz bandwidth and increase acquisition time

beyond 39ns.

INPUT RANGE

The analog inputs of the LTC2355-12/LTC2355-14 may be

driven fully differentially with a single supply. Each input

may swing up to 2.5VP-P individually. When using the

internal reference, the noninverting input should never be

more than 2.5V more positive than the inverting input. The

0V to 2.5V range is also ideally suited for single-ended

input use with single supply applications. The common

mode range of the inputs extend from ground to the sup-

ply voltage VDD. If the difference between the AIN+ and

AIN– inputs exceeds 2.5V, the output code will stay ﬁxed

at all ones and if this difference goes below 0V, the ouput

code will stay ﬁxed at all zeros.

INTERNAL REFERENCE

The LTC2355-12/LTC2355-14 has an on-chip, temperature

compensated, bandgap reference that is factory trimmed

to 2.5V to obtain a unipolar 0V to 2.5V input span. The

reference ampliﬁer output VREF, (Pin 3) must be bypassed

with a capacitor to ground. The reference ampliﬁer is

stable with capacitors of 1µF or greater. For the best noise

performance, a 10µF ceramic or a 10µF tantalum in parallel

with a 0.1µF ceramic is recommended. The VREF pin can be

overdriven with an external reference as shown in Figure

2. The voltage of the external reference must be higher

than the 2.5V output of the internal reference. The recom-

mended range for an external reference is 2.55V to VDD.

An external reference at 2.55V will see a DC quiescent load

of 0.75mA and as much as 3mA during conversion.

Figure 1. RC Input Filter Figure 2. Overdriving VREF Pin with an External Reference

10µF

AIN–

LTC2355-12/

LTC2355-14

AIN+

47pF

51Ω

GND

VREF

2355 F01

GND

LTC2355-12/

LTC2355-14

LT1790-3 VREF

10µF

3.5V TO 18V

2355 F02

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

APPLICATIONS INFORMATION

INPUT SPAN VERSUS REFERENCE VOLTAGE

The differential input range has a 0V to VREF unipolar voltage

span that equals the difference between the voltage at the

reference buffer output VREF at Pin 3, and the voltage at

the ground (Exposed Pad Ground). The differential input

range of the ADC is 0V to 2.5V when using the internal

reference. The internal ADC is referenced to these two

nodes. This relationship also holds true with an external

reference.

DIFFERENTIAL INPUTS

The LTC2355-12/LTC2355-14 has a unique differential

sample-and-hold circuit that measures input voltages from

ground to VDD. The ADC will always convert the unipolar

difference of AIN+ – AIN–, independent of the common

mode voltage at the inputs. The common mode rejection

holds up at extremely high frequencies, see Figure 3. The

only requirement is that both inputs not go below ground

or exceed VDD. Integral nonlinearity errors (INL) and dif-

ferential nonlinearity errors (DNL) are largely independent

of the common mode voltage. However, the offset error

will vary. The change in offset error is typically less than

0.1% of the common mode voltage.

Figure 4 shows the ideal input/output characteristics for

the LTC2355-12/LTC2355-14. The code transitions occur

midway between successive integer LSB values (i.e.,

0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code

is straight binary with 1LSB = 2.5V/16384 = 153µV for

the LTC2355-14, and 1LSB = 2.5V/4096 = 610µV for the

LTC2355-12. The LTC2355-14 has 1LSB RMS of random

white noise.

Figure 3. CMRR vs Frequency Figure 4. LTC2355-12/LTC2355-14 Transfer Characteristic

FREQUENCY (Hz)

100

CMRR (dB)

–20

–40

–60

–80

–100

–120 1k 10k 100k 1M

2355 F03

10M 100M

INPUT VOLTAGE (V)

UNIPOLAR OUTPUT CODE

2355 F04

111...111

111...110

111...101

000...000

000...001

000...010

FS – 1LSB0

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

APPLICATIONS INFORMATION

Board Layout and Bypassing

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC2355-12/LTC2355-14, a printed

circuit board with ground plane is required. Layout for

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. In

particular, care should be taken not to run any digital track

alongside an analog signal track. If optimum phase match

between the inputs is desired, the length of the two input

wires should be kept matched.

High quality tantalum and ceramic bypass capacitors

should be used at the VDD and VREF pins as shown in the

Block Diagram on the ﬁrst page of this data sheet. For

optimum performance, a 10µF surface mount Tantalum

capacitor with a 0.1µF ceramic is recommended for the

VDD and VREF pins. Alternatively, 10µF ceramic chip capaci-

Figure 5. Recommended Layout

tors such as Murata GRM235Y5V106Z016 may be used.

The capacitors must be located as close to the pins as

possible. The traces connecting the pins and the bypass

capacitors must be kept short and should be made as

wide as possible.

Figure 5 shows the recommended system ground connec-

tions. All analog circuitry grounds should be terminated

at the LTC2355-12/LTC2355-14 GND (Pins 4, 5, 6 and

exposed pad). The ground return from the LTC2355-

12/LTC2355-14 (Pins 4, 5, 6 and exposed pad) to the

power supply should be low impedance for noise free

operation. In applications where the ADC data outputs

and control signals are connected to a continuously ac-

tive microprocessor bus, it is possible to get errors in the

conversion results. These errors are due to feedthrough

from the microprocessor to the successive approximation

comparator. The problem can be eliminated by forcing the

microprocessor into a Wait state during conversion or by

using three-state buffers to isolate the ADC data bus.

POWER-DOWN MODES

Upon power-up, the

LTC2355

-12/LTC2355-14 is initial-

ized to the active state and is ready for conversion.

The Nap and Sleep mode waveforms show the power-

down modes for the LTC2355-12/LTC2355-14. The SCK

and CONV inputs control the power-down modes (see

Timing Diagrams). Two rising edges at CONV, without

any intervening rising edges at SCK, put the LTC2355-

12/LTC2355-14 in Nap mode and the power consumption

drops from 18mW to 4mW. The internal reference remains

powered in Nap mode. One or more rising edges at SCK

wake up the LTC2355-12/LTC2355-14 very quickly, and

CONV can start an accurate conversion within a clock

cycle. Four rising edges at CONV, without any interven-

ing rising edges at SCK, put the LTC2355-12/LTC2355-14

REF

BYPASS 0805 SIZE

VDD BYPASS 0805 SIZE

OPTIONAL INPUT FILTERING

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

APPLICATIONS INFORMATION

in Sleep mode and the power consumption drops from

18mW to 13µW. One or more rising edges at SCK wake

up the LTC2355-12/LTC2355-14 for operation. The inter-

nal reference (VREF ) takes 2ms to slew and settle with a

10µF load. Note that, using sleep mode more frequently

than every 2ms, compromises the settled accuracy of the

internal reference. Note that, for slower conversion rates,

the Nap and Sleep modes can be used for substantial

reductions in power consumption.

DIGITAL INTERFACE

The LTC2355-12/LTC2355-14 has a 3-wire SPI-compatible

(Serial

Protocol Interface) interface. The SCK and CONV

inputs and SDO output implement this interface. The SCK

and CONV inputs accept swings from 3.3V logic and are

TTL compatible, if the logic swing does not exceed VDD.

A detailed description of the three serial port signals fol-

lows.

Conversion Start Input (CONV)

The rising edge of CONV starts a conversion, but

subsequent rising edges at CONV are ignored by the

LTC2355

-12/LTC2355-14 until the following 16 SCK ris-

ing edges have occurred and track mode starts again. It

is also necessary to have a minimum of 17 rising edges

of the clock input SCK between rising edges of CONV for

SDO to go to the Hi-Z state and to prepare the internal

ADC logic for the next conversion. But to obtain maximum

conversion speed (with a 63MHz SCK), it is necessary

to allow one more clock period between conversions to

allow 39ns of acquisition time for the internal ADC sample-

and-hold circuit. With 17 clock periods per conversion,

the maximum conversion rate is limited to 3.5Msps to

allow 39ns for acquisition time. In either case, the output

data stream comes out within the ﬁrst 16 clock periods

to ensure compatibility with processor serial ports. The

duty cycle of CONV can be arbitrarily chosen to be used

as a frame sync signal for the processor serial port. A

simple approach to generate CONV is to create a pulse

that is one SCK wide to drive the LTC2355-12/LTC2355-14

and then buffer this signal with the appropriate number

of inverters to ensure the correct delay driving the frame

sync input of the processor serial port. It is good practice

to drive the LTC2355-12/LTC2355-14 CONV input ﬁrst to

avoid digital noise interference during the sample-to-hold

transition triggered by CONV at the start of conversion. It

is also good practice to keep the width of the low portion

of the CONV signal greater than 15ns to avoid introducing

glitches in the front end of the ADC just before the sample-

and-hold goes into hold mode at the rising edge of CONV.

Minimizing Jitter on the CONV Input

In high speed applications where high amplitude sine waves

above 100kHz are sampled, the CONV signal must have

as little jitter as possible (10ps or less). The square wave

output of a common crystal clock module usually meets

this requirement. The challenge is to generate a CONV

signal from this crystal clock without jitter corruption from

other digital circuits in the system. A clock divider and

any gates in the signal path from the crystal clock to the

CONV input should not share the same integrated circuit

with other parts of the system. As shown in Figure 6, the

SCK and CONV inputs should be driven ﬁrst, with digital

buffers used to drive the serial port interface. Also note

that the master clock in the DSP may already be corrupted

with jitter, even if it comes directly from the DSP crystal.

Another problem with high speed processor clocks is that

they often use a low cost, low speed crystal (i.e., 10MHz)

to generate a fast, but jittery, phase-locked-loop system

clock (i.e., 40MHz). The jitter in these PLL-generated high

speed clocks can be several nanoseconds. Note that if

you choose to use the frame sync signal generated by

the DSP port, this signal will have the same jitter of the

DSP’s master clock.

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

APPLICATIONS INFORMATION

The Typical Application Figure on page 16 shows a cir-

cuit for level-shifting and squaring the output from an

RF signal generator or other low-jitter source. A single

D-type ﬂip ﬂop is used to generate the CONV signal to

the LTC2355-12/LTC2355-14. Re-timing the master clock

signal eliminates clock jitter introduced by the controlling

device (DSP, FPGA, etc.) Both the inverter and ﬂip ﬂop must

be treated as analog components and should be powered

from a clean analog supply.

Serial Clock Input (SCK)

The rising edge of SCK advances the conversion process

and also udpates each bit in the SDO data stream. After

CONV rises, the third rising edge of SCK starts clocking

out the 12/14 data bits with the MSB sent ﬁrst. A simple

approach is to generate SCK to drive the LTC2355-12/

LTC2355-14 ﬁrst and then buffer this signal with the ap-

propriate number of inverters to drive the serial clock input

of the processor serial port. Use the falling edge of the clock

to latch data from the Serial Data Output (SDO) into your

processor serial port. The 14-bit serial data will be received

right justiﬁed, in a 16-bit word with 17 or more clocks per

frame sync. It is good practice to drive the LTC2355-12/

LTC2355-14 SCK input ﬁrst to avoid digital noise interfer-

ence during the internal bit comparison decision by the

internal high speed comparator. Unlike the CONV input,

the SCK input is not sensitive to jitter because the input

signal is already sampled and held constant.

Serial Data Output (SDO)

Upon power-up, the SDO output is automatically reset to

the high impedance state. The SDO output remains in high

impedance until a new conversion is started. SDO sends

out 12/14 bits in the output data stream beginning at the

third rising edge of SCK after the rising edge of CONV.

SDO is always in high impedance mode when it is not

sending out data bits. Please note the delay speciﬁcation

from SCK to a valid SDO. SDO is always guaranteed to

be valid by the next rising edge of SCK. The 16-bit output

data stream is compatible with the 16-bit or 32-bit serial

port of most processors.

Loading on the SDO line must be minimized. SDO can

directly drive most fast CMOS logic inputs directly. How-

ever, the general purpose I/O pins on many programmable

logic devices (FPGAs, CPLDs) and DSPs have excessive

capacitance. In these cases, a 100Ω resistor in series

with SDO can isolate the input capacitance of the receiv-

ing device. If the receiving device has more than 10pF

of input capacitance or is located far from the LTC2355-

12/LTC2355-14, an NC7SVU04P5X inverter can be used

to provide more drive.

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2355-12#packaging for the most recent package drawings.

MSOP (MSE) 0213 REV I

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

1234 5

4.90 ±0.152

(.193 ±.006)

0.497 ±0.076

(.0196 ±.003)

REF

8910

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

1.68 ±0.102

(.066 ±.004)

1.88 ±0.102

(.074 ±.004)

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120

±.0015)

TYP

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.68

(.066)

1.88

(.074)

0.1016 ±0.0508

(.004 ±.002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev I)

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 01/10 Revise Values in Pin Conﬁguration Section 2

B 03/17 Updated Timing and Characteristics including tCONV minimum conversion time of 17 clocks. 5, 9, 14, 15

LTC2355-12/LTC2355-14

2355fb

For more information www.linear.com/LTC2355-12

 LINEAR TECHNOLOGY CORPORATION 2007

LT 0317 REV B • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2355-12

RELATED PARTS

TYPICAL APPLICATION

Low-Jitter Clock Timing with RF Sine Generator Using Clock

Squaring/Level Shifting Circuit and Re-Timing Flip-Flop

PRE

VCC

1k50Ω

VCC

NL17SZ74 CONVERT ENABLE

NC7SVU04P5X

MASTER CLOCK

0.1µF

CONV

LTC2355

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

CONV

SCK

SDO

100Ω

NC7SVU04P5X

CLR

2355 TA03

PART NUMBER DESCRIPTION COMMENTS

ADCs

LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span

LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, Unipolar Inputs, MSOP Package

LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, Bipolar Inputs, MSOP Package

LTC1405 12-Bit, 5Msps Parallel ADC 5V, Selectable Spans, 115mW

LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Unipolar Inputs, 14mW, MSOP Package

LTC1407-1/LTC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Bipolar Inputs, 14mW, MSOP Package

LTC1411 14-Bit, 2.5Msps Parallel ADC 5V, Selectable Spans, 80dB SINAD

LTC1412 12-Bit, 3Msps Parallel ADC ±5V Supply, ±2.5V Span, 72dB SINAD

LCT1414 14-Bit, 2.2Msps Parallel ADC ±5V Supply, ±2.5V Span, 78dB SINAD

LTC1420 12-Bit, 10Msps Parallel ADC 5V, Selectable Spans, 72dB SINAD

LTC1604 16-Bit, 333ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD

LTC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD

LTC1609 16-Bit, 250ksps Serial ADC 5V, Conﬁgurable Bipolar/Unipolar Inputs

LTC1864/LTC1865 16-Bit, 250ksps Serial ADCs 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package

LTC2356-12/LTC2356-14 12-/14-Bit, 3.5Msps Serial ADC 3.3V Supply, ±1.25V Span, MSOP Package

DACs

LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs 87dB SFDR, 20ns Settling Time

LTC1592 16-Bit, Serial SoftSpan™ IOUT DAC ±1LSB INL/DNL, Software Selectable Spans

References

LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift

LT1461-2.5 Precision Voltage Reference 0.04% Initial Accuracy, 3ppm Drift

LT1460-2.5 Micropower Series Voltage Reference 0.1% Initial Accuracy, 10ppm Drift