TOSHIBA THLY641641FG-80,-80L,-10,-10L TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THLY641641FG is a 16,777,216-word by 64-bit synchronous dynamic RAM module consisting of eight TC59SM716FT/FTL DRAMs on a printed circuit board. FEATURES @ 16,777,216-word by 64-bit organization @ Single power supply of 3.3 V + 0.3V @ Pipeline architecture -80 -10 @ Auto-refresh and Self-refresh capability tex Clock Cycle Time (CL = 2) 10 ns 12 ns e All inputs and outputs LVITL-compatible tras Active-to-Precharge Command 48 ns 60 ns @ 4096 refresh cycles per 64ms Period (min) @ Package: 144-pin small-outline DIMM tac Access Time from CLK(CL = 2) | 6ns 8 ns (gold contacts) tac Ref/Active-to-Ref/Active e JEDEC Standard * Command Period (min) 68ns | 84ns PIN ASSIGNMENT PIN NAMES 1 1 f\ FRONT Lo o1 59, 61 1430 BACK O2 60~ 62 1440 101| VOD DQi2 DQ44 961001 EBA @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury, or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-08-27 1/13TOSHIBA Serial Presence Detect (Rev.1.2A) THLY641641FG-80,-80L,-10,-10L Naber Function Described #0 8 Entry Value Entry Entry Value Entry 0 ee # bytes Written into Serial Memory at Module 128bytes 80h 128bytes BOh 1 Total # bytes of SPD Memory Device 256bytes 08h 256bytes 08h 2 oe Do SDRAM) ror Appendix A SDRAM 04h SDRAM oah 3 # Row Addresses on this Assembly RAQ-RAI1 0Ch RAO-RAI1 OCh 4 # Column Addresses on this Assembly CA0-CA8 09h CA0-CAB 09h 5 # Module Banks on this Assembly 2B8ank 02h 2Bank 02h 6 Data Width of this Assembly... x64 40h x64 40h 7 ..Data Width Continuation x64 00h x64 00h 8 Voltage Interface Standard of this Assembly LVTTL Oth LVTTL Oth 9 SoRAM Cycle Time at Max. Supported CAS Latency (CL), CL = 3, 8.0ns 80h CL = 3, 10ns AOh 10 SDRAM Access from Clock @ CL = X CL = 3, 6.0ns 60h CL = 3, 7.0ns 70h 1 DIMM Configuration Type (Non-parity, Parity, ECC) Non-Parity 00h Non-Parity 00h 12 Refresh Rate/Type 15.625 ys/self 80h 15.625 s/self 80h 13 SDRAM Width, Primary DRAM x16 10h x16 10h 14 Error Checking SORAM Data Width N/A 00h N/A 00h 15 minima Clock Delay, Back to Back Random Column CLK Oth ICLK Oth 16 Burst Lengths Supported 1,2,4,8 Full page 8Fh 1,2,4,8 Full page 8Fh 7 # Banks on each SDRAM Device 4Bank 04h 4Bank 04h 18 CAS # Latencies Supported 2,3 06h 2,3 06h 19 CS # Latency Oth Oth 20 WE # Latency Oth O1h 21 SDRAM Module Attributes 00h 00h 22 SDRAM Device Attributes: General OEh OEh 23 Minimum Clock Cycle Time at CL- X-1 CL = 2, 10ns AOh CL = 2, 12ns c0h 24 Maximum Data Access Time from Clock @ CL X-1 CL = 2, 6.0ns 60h CL = 2, 8.0ns 80h 25 Minimum Clock Cycle Time at CL X-2 00h 00h 26 Maximum Data Access Time from Clock @ CL X-2 00h 00h 27 Minimum Row Precharge Time 20ns 14h 24ns 18h 28 Minimum Row Active to Row Active Delay 20 ns 14h 200s 14h 29 Minimum RAS to CAS Delay 20 ns 14h 24ns 18h 30 Minimum RAS Pulse Width 48 ns 30h 60 ns 3Ch 31 Module/Bank Density 64 MB 10h 64 MB 10h 32 Command & Address signal Input Setup Time 2ns 20h 2.5 ns 25h 33 Command & Address Signal Input Hold Time tas 10h Ins 10h 34 Data signal Input Setup Time 2ns 20h 2.5 ns 25h 35 Data signal input Hold Time Ins 10h ins 10h 36-61 Superset Information (may be used in future) FFh FFh 62 SPD Revision Rev.1.24 12h Rev.1.2A 12h 63 Checksum for bytes 0-62 1ED2h O2h 1F60h 60h Option Manufacturers JEDEC ID Code per JEP-106E Location Manufacturer's Part Number Revision Code Date Serial Number Manufacturer Data Reserved Reserved Intel Specification Intel Specification Intel Specification Intel Specification 1998-08-27 2/13TOSHIBA BLOCK DIAGRAM THLY641641FG-80,-80L,-10,-10L fT fF CLK LDQM -- pqmeo &J Lo@m CLK wor Fo DQa o7} 01 CK M1 vos f-0 0q7 4 vo8 M1 COKE! 'RAS! UDQM }- DQmB1 O] U0QM (RAS! Pn Vigas! va9 Fo pgs. = Wa9 \oasiT WF FAS, in 1 'caS!| | t-~W- tWE! AO~11,850,1 nig bio pais of wore ROT 11 BS0.1 | WE; LDQM f- paqms2 o LDQM CLK or fo vate Of 01 CLK CoKE; M2 vos Fo 0923. OY wos M2 [ce RAS! UDQM }- DQms3 o7 UDQM | RAS! CLKO o4 CAS! vQ9 F- 0Q2z4 OH] 109 CAS! = bo CLK! WE | ~ i de i ~11,850,1 | qe! WE} = AO~11,BS0,1 gig Fo = pgqa1 4 wore = A011 B50,1 | WE; LDQM f- DQMB4 O~F_ LDQM cLK vor Fo pa32 Oo pt CLK CKE M3 wos Fe q39_- OY vos M3 [ca RAS! UDQM }+- DQMB5 O-| UDQM | RAS! Ph aac} yaa FO =qan. O49 loxeiE Th GAMA AW 1 CAS} YT: i 1 CAS; W \WE} AO~11,BS0,1 org Lio = pqaz of ois AO~11BS0,1 | WE; LDQM fo pqmas o] LOQM CLK vor O DQ48 on vol CLK rexel M4 vos F- pass ows M4 stag RAS! UDQM F DQMB7 O7 UDQM RAS! pt ma o4 1 MAS) pom (CAS! ws pass OF vas CAS! WE ! A0~11, 850,1 wore gea o-| vos A0~11, 850,1 | We! /RAS, /CAS, WE Cum A0~11, - BAO,1 Vop o > Mi~4 = Vp > 2PROM V T Cin F c5~g T c9~12 Vss C13 SS o > MIN~4 = ~E2PROM 102 10P 2 cLK1 Ww scotsc. E2PROM snal 4 soa AO Al A2_ WC tc} ed 7/7 1998-08-27 3/13TOSHIBA THLY641641FG-80,-80L,-10,-10L ABSOLUTE MAXIMUM_RATINGS SYMBOL ITEM RATING UNIT NOTES Vin input Voltage -0.5 to Vpp + 0.3 Vv 1 Vout Output Voltage -0.5 to Vpp + 0.3 Vv 1 Voo Power Supply Voltage -0.5 to 4.6 Vv 1 Torr Operating Temperature 0 to 70 C 1 Tst Storage Temperature ~55 to 125 *C 1 Pp Power Dissipation - 2.4 Ww 1 lout Short Circuit Output Current 50 mA 1 RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to 70C) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES Vop Supply Voltage 3.0 3.3 3.6 Vv 2 Vin LVTTL Input High Voltage 2.0 - Vop + 0.3 Vv 2 Vit LVTTL Input Low Voltage -0.5 - 0.8 Vv 2 CAPACITANCE (Vpp = 3.3 V,f = 1 MHz, Ta = 0 to 70C) SYMBOL PARAMETER MIN MAX UNIT Cy Input Capacitance (AO to A11) ~ T.B.D. pF C2 Input Capacitance (RAS, CAS, WE) - T.B.D. pF C3 Input Capacitance (CLKO,1) - T.B.D. pF Ca Input Capacitance (CSO) - T.B.D. pF Cs input Capacitance (DQMBO to 7) - T.B.D. pF Cog /O Capacitance (DQO to DQ63) - T.B.D. pF 1998-08-27 4/13TOSHIBA AN an tthe eae eS en tn tase! Miya eae Sn ake Site gk Ne oo mtg ee tre Ue eR mo 7 et mee THLY641641FG-80,-80L,-10,-10L DC CHARACTERISTICS (Vpp = 3.3V +t 0.3V, Ta = 0 to 70C) -80 -10 SYMBOL ITEM UNIT | NOTES MIN MAX MIN MAX tec OPERATING CURRENT 1 Active-Precharge Command Cycling . without Burst Operation 1-Bank Operation - 480 - 420 mA 3,5 lec1a | (tex = tae min) STANDBY CURRENT _ . _ !ec2 (tex = min, CS = Vin, CKE = Vin 320 280 mA 3 Vine = Vin (min) / Vi (max) ICKE = Vir 8 8 lcc2e_ | Bank: Inactive State) (Power-down Mode) - - STANDBY CURRENT _ _ _ leeas_ | (CLK = Vy, 3 = Vine _|CKE = Vin 80 80 a Vine = Vin (min) / Vy, (max) CKE = Vit 8 8 lcc2Ps._ | Bank: Inactive State) (Power-down Mode) - - tec3 NO OPERATING CURRENT CKE = Vy - 340 _ 300 (tex = min, CS = Vin (min) CKELV mA \ccap__-| Bank: Active State (2 Banks)) (Power-down Mode) - 80 - 80 , BURST OPERATING CURRENT 600 500 mA 3.45 cca (tee = min, CS = Vi (min) Read/Write Command Cycling) AUTO-REFRESH CURRENT 880 740 mA 3.5 ces (tc = min, Auto-Refresh Command Cycling) ; SELF-REFRESH CURRENT THLY641641FG-80,-10 - 8 - 8 ma | a S| (Self-Refresh Mode, CKE=0.2V) Iruiveqrgaire-oL-1o. | - | a8 | - | 48 ' INPUT LEAKAGE CURRENT 5 5 5 5 uA Mu) (OV S Vin 3 Vop, Ail Other Pins Not under Test = 0V) \ OUTPUT LEAKAGE CURRENT 7 5 5 5 yA ou (Dour 's Disabled, 0V 3 Vout s Vop) Vv OUTPUT LEVEL 24 24 V OH | LVTTL Output H Level Voltage (Ioyt = -2mA) , Vv OUTPUT LEVEL 04 04 V Ot | LVTTL Output L Level Voltage (loyy = 2mA) , , 1998-08-27 5/13TOSHIBA THLY641641FG-80,-80L,-10,-10L AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Vpp = 3.3V + 0.3V, Ta = 0 to 70C) -80 -10 SYMBOL PARAMETER MIN MAX MIN MAX UNIT | NOTES tre Ref/Active-Ref/Active Command Period 68 84 tras Active- Precharge Command Period 48 100000 60 100000 ns trep Active-Read/Write Command Delay Time 20 24 tec Read/Write(a) Readrite(b) ' ' cycle 9 Command Period tre Precharge-Active Command Period 20 24 trro Active(a)-Active(b) Command Period 20 20 twr Write Recovery Time CL* =2 10 12 CL* = 3 8 10 tex CLK Cycle Time CL* = 2 10 1000 12 1000 CL* = 3 8 1000 10 1000 ten CLK High Level Width 3 3 10 tet CLK Low Level Width 3 3 tac Access Time from CLK CL* =2 6 8 CL* = 3 6 7 tou Output Data Hold Time 3 3 tuz Output Data High Impedance Time 3 8 3 10 8 tiz Output Data Low impedance Time 0 0 ns tsp Power-down Mode Entry Time 0 8 0 10 tr Transition Time of CLK (Rise and Fall) 0.5 10 0.5 10 tos Data-in Set-up Time 2 2.5 ton Data-in Hold Time 1 1 tas Address Set-up Time 2 2.5 tay Address Hold Time 1 1 teks CKE Set-up Time 2 2.5 teKH CKE Hold Time 1 1 tems Command Set-up Time 2 2.5 tcmH Command Hold Time 1 1 trer Refresh Time 64 64 ms trsc Mode Register Set Cycle Time 16 20 ns 9 * CL is CAS latency. 1998-08-27 6/13TOSHIBA THLY641641FG-80,-80L,-10,-10L NOTES: 1. Conditions outside the limits listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltages are referenced to Vss. 3. These parameters depend on the cycle rate and their values are measured at the minimum cycle rate values tcx andtrc. Input signals are changed once during tcx. 4, These parameters depend on the output loading. The specified values are obtained with the output open. 5. These valves are measured with the following conditions. Front side (or back side) : the measuring condtions on the data sheet Back side (or front side) : Stand by (measured with Iccg conditions) 6. The power-up sequence is described in Note 12. 7. AC TEST CONDITIONS 1.4V/1.4V Load See the di for AC Test Load (B) below In Si Levels 2.4V/0.4V Transition Time (Rise and Fall) of 2ns 1.4V 3.3V 1.4V 1.2k2 fy Q Output Output tL 50 pF 8700 Ty 50 pF AC TEST LOAD (A) AC TEST LOAD (B) 8, Transition times are measured between the Vip and Vjy levels. Transition (rise and fall) of input signals has a fixed slope. 9, tuz defines the time at which the outputs go open circuit and are not reference levels. 10. These parameters depend on the number of clock cycles and depend on the operating frequency of the clock as follows: Number of clock cycles = Specified value of timing /Clock period (Round up fractions to a whole number.) 1998-08-27 7/13TOSHIBA THLY641641FG-80,-80L,-10,-10L 11. 12. tcu is the pulse width of CLK measured from the positive edge to the negative edge and referenced to Vir (min). tcy is the pulse width of CLK measured from the negative edge to the positive edge and referenced to Viz, (max). Power-up Sequence Power-up must be performed in the following sequence. 1) Power must be applied to Vpp and VppQ (simultaneously) with all input signals heldin the NOP state. The CLK signal must be started at the same time as power is applied. 2) After power-up a pause of at least 200 seconds is required. Then, DQM and CKE must be held High (at the Vpp level) to ensure that the DQ output is high-impedance. 3) Both banks must be precharged. 4) The Mode Register Set command must be asserted to initialize the Mode register. 5) An Auto-Refresh operation must consist of at least eight Auto-Refresh cycles. The order in which 4) and 5) are performed is interchangeable. 1998-08-27 8/13TOSHIBA TIMING DIAGRAMS Read Timing Read CAS Latency THLY641641FG-80,-80L,-10,-10L ao =e ms 7] | TE MMMMMMMM@@ MMMM Y) | WY /MUMMMMMMMM@@ZZ#M _@@@llll "Y QO _i-"?zuo*>7]dAdMqAqQQqQrum BAO, 1 001080 Oh___ WW WMMMMMMM@MMMHHHH@@ eM DQO to 63 f Burst Length 1998-08-27 9/13TOSHIBA THLY641641FG-80,-80L,-10,-10L Command Input Timing ck Vin 7 Vi \ j "WI fT tomH tomy | . dF cs 0 VIIA. TIL. RAS CAS WE "26"; YIN. - TILT LLL tcKs|. tcKH tens| tcKH KS teKH y y Wi X__\ 1998-08-27 10/13TOSHIBA THLY641641FG-80,-80L,-10,-10L Control Timing for Input Data (Word Mask) ck Ff Ve VF VF VF Le tomy _ toms _ tom tems DQMBO to 7 t x t tos} toy tos] ton tos] ton tos (Clock Mask) . CLK _* \ gy | Po \_ Ff VL texu teks | tckH teks t > <_->-| CKE \ \ f y tos} tox tos | ton tos) tox tos| ton DQO to 63 Uy Control Timing for Output Data (Output Enable) uf \# \4 tcmH tems | tomy DQMBO to 7 pf \ LJ) < tac 1 | _ OH __toH ALID DQO to 63 DATA-OUT teky (Clock Mask) CLK ] teks | texH ce + tt >] tac < tac tac tou ton tou tou VALID VALID DQO to 63 DATA-OUT VALID DATA-OUT DATA-OUT 1998-08-27 11/13TOSHIBA THLY641641FG-80,-80L,-10,-10L Mode Register Set Cycle CLK ADtO AIT, BAO, 1 tas 0 0 Set Register Data tan Burst Length Addressing Mode TAS Latency (Test Mode) Reserved Write Mode Reserved Next Command Burst al Interleave 1 > nN z 2 4 8 Reserved Reserved 0 0 0 0 1 1 1 1 -mjlal|olojl|-tosfo Full A3 Addressing Mode 0 Sequential 1 interleave CAS Reserved 2 3 4 Ad Single-Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write 1998-08-27 12/13TOSHIBA THLY641641FG-80,-80L,-10,-10L PACKAGE DIMENSIONS (THLY641641FG) Unit: mm FRONT | 67.60 0.13 1 >| _3.80 MAX. nl wd 4 fF , (do O 0 0 7 \ o| A t+/ 7 o 0 0 z #| |e 5 a + ow) | . So . oe a/e|esi | O oBf] ) tHE 1 R 1 (On mi Al 2.50 3.304013 1 | {. 23.20 . 1.00 0.10 2.004013 | |S 63.60 REF BACK 3.704013 _,| ty 2.10 | 60 62 co CONTACT DIMENSIONS @ THLY641641FG . FULLER Tr FRONT i - 1 so i z 3 % = e i $ w + ! nN w 1 nN y i i oso+o.0s| | |rsoz0.10| i las0| I re} 2.50 1 4.60 xj Contacts: gold Weight: g (typ) 1998-08-27 13/13