ANALOG Quad 12-Bit Microprocessor- DEVICES Compatible D/A Converter AD3S0 REV. C 1.1 Scope. This specification covers the device requirements for a hybrid quad 12-bit voltage output D/A converter with double buffered latches. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number -1 AD390SD/883B 2 AD390TD/883B 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-H-1000: package outline: DH-28. 1.3 Absolute Maximum Ratings. (T, = + 25C unless otherwise noted) +VstoDGND .. 2... ee ee Oto +18V ~VstoDGND .. 1... 2. et ee ne 0 to 18V Digital Inputs (Pins 1-12, 23-28)to DGND ...........0. 02.04 ee eee 1.0V to +7V RefIntoDGND ...... 2.0... ce ee eee +Vs5 AGND to DGND .. 1. 1 ee +0.6V Analog Outputs (Pins 16, 18-21) . 2... ee ee Infinite Short to AGND or DGND, Momentary Shorts to + Vs Storage Temperature Range... 2. 1 ee ee ns 65C to + 150C Lead Temperature (Soldering 10sec) 2... 2. ee + 300C 1.5 Thermal Characteristics. Thermal Resistance @; = 8C/W Oya = 25C/W DIGITAL-TO-ANALOG CONVERTERS 8-11 DIGITAL-TO-ANALOG CONVERTERS a AD390 SPECIFICATIONS Table 1. Design Limit @+25C |Sub Sub Sub (-55Cto |Group | Group | Group Test Symbol |Device | +125C) |1 2,3 4 Test Condition Units Data Input Voltage High Vin -1,2 2.0(2.0) 2.0 Test Limits Apply to V min 5.5(5.5) Pins 1-12. Design V max End Point Electrical -1,2 2.0 Limits Apply to Vmin Pins 23-28. Data Input Voltage Low Vit -1,2 0.0(0.0) Test Limits Apply to Vmin 0.8 (0.8) 0.8 Pins 1-12. Design V max End Point Electrical -1,2 0.8 Limits Apply to V max Pins 23-28. Input Current High Tin -1,2 1200 (1200) Test Limits Apply to pA max End Point Electrical -1,2 1200 Pins 1-12. Design Limits Input Current Low lit 1,2 | 400(400) Apply to Pins 23-28, A max End Point Electrical ~1,2 400 Except for Pin 24 Which is 3X. Output Voltage Range Vour |-1;2 10(10) 10 +V max 10(10) 10 -Vmin Output Current Range Tor -1,2 5(5) @ +10V Output mA min Gain Error Ag -1 0.1 0.1 With External +% FSR max -2 0.05 0.05 | +10,000Ref End Point Electrical -1,2 0.2 Gain Error Temperature TCazk |-1 (40) With Internal + ppm/C max Coefficient -2 (20) Reference -1 (10) 10 With External + ppm/C max -~2 (5) 5 Reference Offset Error Vos -1 0.05 0.05 +% FSR max 2 0.025 0.025 End Point Electrical -1,2 0.1 Bipolar Zero Temperature | TCBpz |-1 (10) 10 Vaprs = + 10V + ppm/C max Coefficient -2 (5) 5 Differential Linearity? DLE |-1 3/4 3/4 + LSB max Error ~2 12 V2 End Point Electrical -~1,2 1 Linearity Error* LE ~1 3/4 34 + LSB max End Point Electrical -2 1/2 1/2 -1,2 1 Linearity Error Tce |-1 (3/4) 3/4 + LSB max Temperature Coefficient -2 (1/2) 1/2 Positive Summation Error | Epp -1 3/4 3/4 + LSB max End Point Electrical -2 1/2 1/2 -1,2 1 Negative Summation Error | Ene -1 3/4 a4 + LSB max End Point Electrical -2 1/2 1/2 -1,2 1 Reference Output REF out] 1,2 9.997 9.997 R,.=6.8k0 Vmin 10.003 10.003 V max Power Supply Voltages? Vs -1,2 13.5 +Vmin -1, 16.5 + V max 8-12 DIGITAL-TO-ANALOG CONVERTERS REV. Design Limi @+25C | Sub Sub Sub (-55Cto| Group| Group| Group Test Symbol| Device | +125C) | 1 2,3 4 Test Condition Units Power Supply Currents leg -1,2 100 100 120 No Load mA max lec 35 35 35 +mA max Power Supply Gain PSRR | -1,2 0.0067 0.0067 | Input Bits = +% FS/% Sensitivity Delta Gain/ Wi 1121 1111 Delta Vs(+ Vs and Vs) Timing Specifications Chip Select aw -1 100 See Figure 2 ns min Pulse Width -2 Address Select twe -1 100 See Figure 2 ns min Low Time -2 Data Valid Before tow ~1 50 See Figure 2 ns min AO Rising Edge -2 Data Valid After toH -1 10 See Figure 2 ns min AO Rising Edge -2 Chip Select Valid tas -1 0 See Figure 2 ns min Before Al Low -2 Output Voltage tserr | -1 8 See Figure 2 Ss max Settling Time -2 NOTES 'T, = +25Cand +Vs = + 15V unless otherwise specified. AD390 can be used with supplies as low as + 11.4V (see AD390 commercial data sheet). 2FSR means Full-Scale Range and is equal to 20V fora + 10V bipolar range. 3Monotonicity is tested for over the full military temperature. Integral Nonlinearity is a measure of the maximum deviation from a straight line passing through the end points of the transfer function. 3.2.1 Functional Block Diagram and Terminal Assignments. Top View +Ve Vs DGND aGNO Q3) C9 (3) An390 Vv DH-28 Package = mQ 12-BiT LATCH o tsB)pB0 [7] 2] csi cat 12-BIT LATCH AG (a) oB1 ez 27) oss es fa] ow [7 Pe) os Des 24] Ao ey AD390 p24 ~ 6 oes [6] [za] At =OTE oes [7] Pez] +- ve? [5] 21] Yours pes [3 | [20] Vours pes [70 (19) Vourz osto (77 | 18] Your: Te isp) 0B11 [12 17) REFIN oano [i] 76 | REFOUT -Vs [ia 15 ] AGNOD PINS 1212 OB9/LE6) DETIMSE) REV. C DIGITAL-TO-ANALOG CONVERTERS 8-13 DIGITAL-TO-ANALOG CONVERTERS a AD390 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (1). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). 22 +V5 71 2k an 2} # 9 mnt > i 2ka ! 7 = 16 1s Table 2. AD390 Truth Table Table 3. AD390 Analog Output vs. Digital Input (+ V Scale) Csi T3i C33 TS Al AO | Operation 1 1 1 1 X X]NoOperation ws X X XX 1 1|NoOperation Digital Input Code Analog Output Voltage 0 1 1 1 1 O|Enable Istrank of DAC1 0000 0000 0000) 10.000V Full Scale 1 6 1 1 1 O|Enable Ist rank of DAC2 0100 0000 0000 | 5.000V ~ 1/2Scale 1 2 1 1 O|Enable Ist rank of DAC3 1000 0000 0000 | 0.000V Zero 1 1 1 O|Enable Ist rank of DAC4 1000 0000 0001 +4.88mV + ILSB 0 1 1 1 0 1]Load DAC secondrankfromfirstrank |] 117 Sin 1111 | +9.99S1V + FullSece ~1LSB 1 0 1 1 Q 1 |Load DAC 2 second rank from first rank 1 1 0 1 0 1 Load DAC 3 second rank from first rank 1 1 1 0 0. 1)]Load DAC 4 second rank from first rank 0 0 0 0 0 /|Alllatches transparent Write Cycle #1 (Load First Rank from Data Bus; AT = 1) x ost css |X f= D811 - DBO x ~~ ton AG QUTPUT | two Figure 1. Timing Diagram 8-14 DIGITAL-TO-ANALOG CONVERTERS Write Cycle #2 (Load Second Rank from First Rank; AO = 1) REV. C