1
FEATURES
APPLICATIONS
TYPICAL APPLICATION
SYNC
GND PGND
SW
VO=3.3V
6.8 Hm
C =22 F
6.3V
Om
VIN
LBI
C =10 F
25V
Im1 Fm
V =3.8Vto17V
I
VIN
EN
VINA
PGNDGND PwPD
AGND
TPS62111
SW
LBO
PG
1M
FB
DESCRIPTION/ORDERING INFORMATION
TPS62110-EP
TPS62111-EP
TPS62112-EP
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.............................................................................................................................................................. SLVS630C APRIL 2007 REVISED MAY 2008
17 V, 1.5 A, SYNCHRONOUS STEP-DOWN CONVERTER
2
Controlled Baseline 20 µA Quiescent Current (Typical) One Assembly Overtemperature and Overcurrent Protected One Test Site Available in 16 Pin QFN Package One Fabrication SiteExtended Temperature Performance of 55 ° Cto 125 ° C
Point-of-Load Regulation From 12 V BusEnhanced Diminishing Manufacturing Sources
Organizers, PDAs, and Handheld PCs(DMS) Support
Handheld ScannersEnhanced Product-Change NotificationQualification PedigreeHigh-Efficiency Synchronous Step-DownConverter With up to 95% Efficiency3.1 V to 17 V Operating Input Voltage RangeAdjustable Output Voltage Range From1.2 V to 16 VFixed Output Voltage Options Available in3.3 V and 5 VSynchronizable to External Clock Signal up to1.4 MHzUp to 1.5 A Output CurrentHigh Efficiency Over a Wide Load CurrentRange Due to PFM/PWM Operation Mode100% Maximum Duty Cycle for Lowest DropoutComponent qualification in accordance with JEDEC and industrystandards to ensure reliable operation over an extendedtemperature range. This includes, but is not limited to, HighlyAccelerated Stress Test (HAST) or biased 85/85, temperaturecycle, autoclave or unbiased HAST, electromigration, bondintermetallic life, and mold compound life. Such qualification testingshould not be viewed as justifying use of this component beyondspecifiedperformance and environmental limits.
The TPS6211x devices are a family of low-noise synchronous step-down dc-dc converters that are ideally suitedfor systems powered from a 2-cell Li-ion battery or from a 12 V or 15 V rail.
The TPS6211x is a synchronous PWM converter with integrated N-channel and P-channel power MOSFETswitches. Synchronous rectification is used to increase efficiency and to reduce external component count. Toachieve highest efficiency over a wide load current range, the converter enters a power-saving, pulse-frequencymodulation (PFM) mode at light load currents. Operating frequency is typically 1 MHz, allowing the use of smallinductor and capacitor values. The device can be synchronized to an external clock signal in the range of 0.8MHz to 1.4 MHz. For low noise operation, the converter can be operated in PWM-only mode. In the shutdownmode, the current consumption is reduced to less than 2 µA. The TPS6211x is available in the 16 pin (RSA)QFN package, and operates over a free-air temperature range of 55 ° C to 125 ° C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
TPS62111
EfficiencyvsOutputCurrent
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
5V
4.2V
12V
8.4V
V =3.3V
T
PFMMode
O
A=25 C
o
TPS62110-EP
TPS62111-EP
TPS62112-EP
SLVS630C APRIL 2007 REVISED MAY 2008 ..............................................................................................................................................................
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Product Folder Link(s): TPS62110-EP TPS62111-EP TPS62112-EP
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
TPS62110-EP
TPS62111-EP
TPS62112-EP
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.............................................................................................................................................................. SLVS630C APRIL 2007 REVISED MAY 2008
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.These circuits have been qualified to protect this device against electrostatic discharges; HBM according to EIA/JESD22-A114-B,MM according EIA/JESD22-A115-A, and CDM according EIA/JESD22C101C; however, it is advised that precautions be taken toavoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handlingthe device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs shouldalways be connected to an appropriate logic voltage level, preferably either VCC or ground. Specific guidelines for handling devicesof this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices andAssemblies available from Texas Instruments.
ORDERING INFORMATION
(1)
T
A
PLASTIC QFN OUTPUT LBI/LBO
MARKING16 PIN (RSA)
(2) (3)
VOLTAGE FUNCTIONALITY
TPS62110MRSAREP Adjustable Standard TPS62110-EP1.2 V to 16 V 55 ° C to 125 ° C
TPS62111MRSAREP 3.3 V Standard TPS62111-EPTPS62112MRSAREP 5 V Standard TPS62112-EP
(1) For the most current package and ordering information, see the Package Option Addendum at the endof this document, or see the TI website at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(3) The RSA package is available in tape and reel. Add R suffix (TPS62110RSAR) to order quantities of3000 parts per reel. Add T suffix (TPS62110RSAT) to order quantities of 250 parts per reel
over operating free-air temperature range (unless otherwise noted)
UNIT
V
CC
Supply voltage at VIN, VINA 0.3 V to 20 VVoltage at SW 0.3 V to V
I
V
I
Voltage at EN, SYNC, LBO, PG 0.3 V to 20 VVoltage at LBI, FB 0.3 V to 7 VI
O
Output current at SW 2400 mAT
J
Maximum junction temperature 150 ° CT
stg
Storage temperature 65 ° C to 150 ° CLead temperature 1,6 mm (1/16-inch) from case for 10 seconds 300 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
T
A
25 ° C DERATING FACTOR T
A
= 70 ° C T
A
= 85 ° CPACKAGE
POWER RATING ABOVE T
A
= 25 ° C POWER RATING POWER RATING
RSA 2.5 W 25 mW/ ° C 1.375 W 1 W
(1) Based on a thermal resistance of 40 K/W soldered onto a high K board.
MIN MAX UNIT
V
CC
Supply voltage at VIN, VINA 3.1 17 VMaximum voltage at power-good, LBO, EN, SYNC 17 VT
J
Operating junction temperature 55 125 ° C
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ELECTRICAL CHARACTERISTICS
TPS62110-EP
TPS62111-EP
TPS62112-EP
SLVS630C APRIL 2007 REVISED MAY 2008 ..............................................................................................................................................................
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V
I
= 12 V, V
O
= 3.3 V, I
O
= 600 mA, EN = V
I
, T
A
= 55 ° C to 125 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
V
I
Input voltage range
(1)
3.1 17 VI
O
= 0 mA, SYNC = GND, V
I
= 7.2 V, 20T
A
= 25 ° C
(2)I
(Q)
Operating quiescent current µAI
O
= 0 mA, SYNC = GND, 23 29V
I
= 17 V
(2)
EN = GND 1.5 5I
(SD)
Shutdown current µAEN = GND, T
A
= 25 ° C, V
I
= 7.2 V 1.5 3
ENABLE
V
IH
EN high-level input voltage 1.3 VV
IL
EN low-level input voltage 0.3 VEN trip-point hysteresis 170 mVI
IKG
EN input leakage current EN = GND or V
I
, V
I
= 17 V 0.01 0.2 µAI
(EN)
EN input current 0.6 V V
(EN)
4 V 10 µAV
(UVLO)
Undervoltage lockout threshold Input voltage falling 2.8 3 3.1 VUndervoltage lockout hysteresis 250 mV
POWER SWITCH
V
I
5.4 V, I
O
= 350 mA 165 250r
DS(ON)
P-channel MOSFET on-resistance V
I
= 3.5 V, I
O
= 200 mA 340 m
V
I
= 3 V, I
O
= 100 mA 490P-channel MOSFET leakage
V
DS
= 17 V 0.1 1 µAcurrent
P-channel MOSFET current limit V
I
= 7.2 V, V
O
= 3.3 V 2400 mAV
I
5.4 V, I
O
= 350 mA 145 200r
DS(ON)
N-channel MOSFET on-resistance V
I
= 3.5 V, I
O
= 200 mA 170 m
V
I
= 3 V, I
O
= 100 mA 200N-channel MOSFET leakage
V
DS
= 17 V 0.1 3 µAcurrent
POWER GOOD OUTPUT, LBI, LBO
V
(PG)
Power good trip voltage V
O
1.6% VV
O
ramping positive 50Power good delay time µsV
O
ramping negative 200V
OL
PG, LBO output low voltage V
(FB)
= 1.1 × V
O
nominal, I
OL
= 1 mA 0.3 VI
OL
PG, LBO sink current 1 mAPG, LBO output leakage current V
(FB)
= V
O
nominal 0.01 0.25 µAMinimum supply voltage for valid
3 Vpower good, LBI, LBO signalV
LBI
Low battery input trip voltage Input voltage falling 1.256 VILBI LBI input leakage current 10 100 nALow battery input trip-point
1.5 %accuracyV
LBI,HYS
Low battery input hysteresis 25 mV
(1) Not Production tested(2) Device is not switching.
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Product Folder Link(s): TPS62110-EP TPS62111-EP TPS62112-EP
TPS62110-EP
TPS62111-EP
TPS62112-EP
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.............................................................................................................................................................. SLVS630C APRIL 2007 REVISED MAY 2008
ELECTRICAL CHARACTERISTICS (continued)V
I
= 12 V, V
O
= 3.3 V, I
O
= 600 mA, EN = V
I
, T
A
= 55 ° C to 125 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OSCILLATOR
f
S
Oscillator frequency 900 1000 1100 kHzf
(SYNC)
Synchronization range CMOS-logic clock signal on SYNC pin 800 1400 kHzV
IH
SYNC high-level input voltage 1.5 VV
IL
SYNC low-level input voltage 0.3 VI
lkg
SYNC input leakage current SYNC = GND or VIN 0.01 0.2 µASYNC trip-point hysteresis 170 mVSYNC input current 0.6 V V
(SYNC)
4 V 10 20 µ ADuty cycle of external clock signal 30 90 %
OUTPUT
V
O
Adjustable output voltage range TPS62110 1.153 16 VV
FB
Feedback voltage TPS62110 1.153 VFB leakage current TPS62110 10 100 nAV
I
= 3.1 V to 17 V,Feedback voltage tolerance
(3)
TPS62110 6 6 %0 mA < I
O
< 1500 mA
(4)
V
I
= 3.8 V to 17 V,TPS62111 7 7 %0 mA < I
O
< 1500 mA
(4)Fixed output voltage tolerance
(5)
V
I
= 5.5 V to 17 V,TPS62112 7 7 %0 mA < I
O
< 1500 mA
(4)
V
I
3 V (once undervoltage lockout voltage
100exceeded)
V
I
3.5 V 500I
O
Maximum output current mAV
I
4.3 V 1200V
I
6 V 1500Current into internal voltage divider for
5µAfixed voltage versions
V
I
= 7.2 V, V
O
= 3.3 V, I
O
= 600 mAηEfficiency 92 %V
I
= 12 V, V
O
= 5 V, I
O
= 600 mADuty cycle range for main switches at 1 MHz 10 100 %Minimum t
on
time for main switch 100 nsShutdown temperature 145 ° CStart-up time I
O
= 800 mA, V
I
= 12 V, V
O
= 3.3 V 1 ms
(3) Not Production tested(4) The maximum output current depends on the input voltage. See the maximum output current for further restrictions on the minimuminput voltage.(5) The output voltage accuracy includes line and load regulation over the full temperature range T
A
= 55 ° C to 125 ° C. See the section forno-load operation in this data sheet.
Copyright © 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS62110-EP TPS62111-EP TPS62112-EP
DEVICE INFORMATION
PIN ASSIGNMENT TOP VIEW
16 15 14 13
5678
1
2
3
4 9
GND
GND
FB
AGND
PGND
Exposed
Thermal
Pad
VIN
VIN
EN
PGND
SW
LBI
VINA
SW
PG
SYNC
LBO
12
11
10
TPS62110-EP
TPS62111-EP
TPS62112-EP
SLVS630C APRIL 2007 REVISED MAY 2008 ..............................................................................................................................................................
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TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
Enable. A logic high enables the converter; logic low forces the device into shutdown mode reducing theEN 4 I
supply current to less than 2 µ A.Feedback pin for the fixed output voltage option. For the adjustable version, an external resistive dividerFB 10 I
is connected to this pin. The internal voltage divider is disabled for the adjustable version.LBO 6 O Open-drain, low-battery output. This pin is pulled low if LBI is below its threshold.GND 11, 12 I GroundLBI 7 I Low-battery inputConnect the inductor to this pin. This pin is the switch pin and connected to the drain of the internalSW 14, 15 O
power MOSFETS.
Power good comparator output. This is an open-drain output. A pullup resistor should be connectedPG 13 O between PG and VOUT. The output goes active high when the output voltage is greater than 98.4% ofthe nominal value.PGND 1, 16 I Power ground. Connect all power grounds to this pin.AGND 9 I Analog ground, connect to GND and PGNDInput for synchronization to external clock signal. Synchronizes the converter switching frequency to anexternal clock signal with CMOS level:SYNC 5 I
SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forcedSYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabledVIN 2, 3 I Supply voltage input (power stage)VINA 8 I Supply voltage input (support circuits)PowerPAD™ Connect to AGND
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Product Folder Link(s): TPS62110-EP TPS62111-EP TPS62112-EP
_
+
_
+
_
+
_
+
_
+
REF
REF
LoadComparator
IAVG Comparator
CurrentLimitComparator
P-Channel
PowerMOSFET
Driver
Shoot-Through
Logic
Control
Logic
SoftStart
1-MHz
Oscillator
Comparator S
R
N-Channel
PowerMOSFET
ComparatorHigh
ComparatorLow
ComparatorHigh2
V(COMP)
Sawtooth
Generator
V
I
Undervoltage
Lockout
BiasSupply
_
+
ComparatorHigh
ComparatorLow
Compensation
V =1.153V
REF
R2
(SeeNote A)
R1
VI
EN
SW
FB PGND
Gm
Thermal
Shutdown
Vina
_
+
_
+
SKIP Comparator
_
+
_
+
PG
LBO
LBI GND
1.256V
TPS62110-EP
TPS62111-EP
TPS62112-EP
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.............................................................................................................................................................. SLVS630C APRIL 2007 REVISED MAY 2008
FUNCTIONAL BLOCK DIAGRAM
A. For the adjustable version (TPS62110), the internal feedback divider is disabled and the FB pin is directly connectedto the internal GM amplifier.
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TYPICAL CHARACTERISTICS
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
15V
12V
8.4V
V =5V
T
PWMMode
O
A=25 C
o
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
15V
12V
8.4V
V =5V
T
PFMMode
O
A=25 C
o
TPS62110-EP
TPS62111-EP
TPS62112-EP
SLVS630C APRIL 2007 REVISED MAY 2008 ..............................................................................................................................................................
www.ti.com
Table of Graphs
FIGURE
Efficiency vs Output current (5 V) 1, 2Efficiency vs Output current (3.3 V) 3, 4, 5Maximum output current vs Input voltage 6Efficiency vs Output current (1.8 V) 7, 8Efficiency vs Output current (1.5 V) 9, 10Line transient response 11Load transient response 12Output ripple 13Start-up timing 14Switching frequency vs Input voltage 15Quiescent current vs Input voltage 16
Graphs with V
O
= 1.8 V were taken using the circuit according to Figure 20 .
TPS62112 TPS62112EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 1. Figure 2.
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100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
5V
4.2V
12V
8.4V
V =3.3V
T
PWMMode
O
A=25 C
o
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
5V
4.2V
12V
8.4V
V =3.3V
T
PFMMode
O
A=25 C
o
2000
1600
1100
1800
1400
900
700
400
100
1900
1500
1000
1700
1200
1300
800
500
200
600
300
03.2 3.6 5.2
45.6 6
4.4 4.8
V -InputVoltage-V
I
I-OutputCurrent-mA
O
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
5V
12V
8.4V
V =3.3V
SYNC=1.4MHz
T
PFMMode
O
A=25 C
o
TPS62110-EP
TPS62111-EP
TPS62112-EP
www.ti.com
.............................................................................................................................................................. SLVS630C APRIL 2007 REVISED MAY 2008
TPS62111 TPS62111EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 3. Figure 4.
TPS62111 TPS62111EFFICIENCY MAXIMUM OUTPUT CURRENTvs vsOUTPUT CURRENT INPUT VOLTAGE
Figure 5. Figure 6.
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100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
5V
4.2V
12V
8.4V
V =1.8V
T
PFMMode
O
A=25 C
o
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
5V
4.2V
12V
8.4V
V =1.8V
T
PWMMode
O
A=25 C
o
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
5V
4.2V
12V
8.4V
V =1.5V
T
PFMMode
O
A=25 C
o
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I -OutputCurrent- A
O
Efficiency-%
5V
4.2V
12V
8.4V
V =1.5V
T
PWMMode
O
A=25 C
o
TPS62110-EP
TPS62111-EP
TPS62112-EP
SLVS630C APRIL 2007 REVISED MAY 2008 ..............................................................................................................................................................
www.ti.com
TPS62110 TPS62110EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 7. Figure 8.
TPS62110 TPS62110EFFICIENCY EFFICIENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 9. Figure 10.
10 Submit Documentation Feedback Copyright © 2007 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS62110-EP TPS62111-EP TPS62112-EP
t − Time = 2 ms/div
VI = 7.2 V to 12 V
VO = 3.3 V
ILOAD = 800 mA
TA = 25°C
C2 = 50 mV/div
C1 = 5 V/div
t − Time = 5 µs/div
CH1 = 20 mV/div
VI = 8.4 V, VO = 3.3 V
CH2 =
5 V/div
CH4 = 200 mA/div
ILOAD = 100 mA, TA = 25°C
t − Time = 200 µs/div
CH1 = 10 V/div
VI = 12 V, VO = 3.3 V
CH4 = 500 mA/div
ILOAD = 800 mA, TA = 25°C
CH3 = 5 V/div
CH2 = 1 V/div
TPS62110-EP
TPS62111-EP
TPS62112-EP
www.ti.com
.............................................................................................................................................................. SLVS630C APRIL 2007 REVISED MAY 2008
TPS62111 TPS62111LINE TRANSIENT LOAD TRANSIENT
Figure 11. Figure 12.
TPS62111 TPS62111OUTPUT RIPPLE START-UP TIMING
Figure 13. Figure 14.
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1000
970
930
940
900
980
950
910
990
960
920
37
59
48
6 10 1412 16
11 1513 17
V -InputVoltage-V
I
SwitchingFrequency-kHz
25 C
o
-40 C
o
85 C
o
V =12V
I
O
O=100mA
0
10
30
20
40
5
15
35
25
45
50
37
59
48
6 10 1412 16
11 1513 17
V -InputVoltage-V
I
QuiescentCurrent- Am
25 C
o
-40 C
o
85 C
o
SYNC
GND PGND
SW
R1
R2
VO
TDK6.8 H
SLF7032T-6R8M1R6
m
C 22 F/16V
TDK
Om
C3225X7R1C226M
VIN
LBI
C 10 F/25V
TDK
Im
C3225X5R1E106K
1 Fm
261kW
Vbat
VIN
EN
VINA
PGNDGND PwPD
open
VINor
GND
AGND
TPS62110 SW
LBO
PG
1MW1MW
FB
Cff
-EP
TPS62110-EP
TPS62111-EP
TPS62112-EP
SLVS630C APRIL 2007 REVISED MAY 2008 ..............................................................................................................................................................
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SWITCHING FREQUENCY QUIESCENT CURRENTvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 15. Figure 16.
The graphs were generated using the EVM with the setup according to Figure 17 unless otherwise noted. Theoutput voltage divider was adjusted according to Table 4 . Graphs for an output voltage of 5 V and 3.3 V weregenerated using TPS62111 and TPS62112 with R1 = 0 and R2 = open.
Figure 17. Test Setup
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DETAILED DESCRIPTION
OPERATION
CONSTANT FREQUENCY MODE OPERATION (SYNC = HIGH)
POWER SAVE MODE OPERATION (SYNC = LOW)
TPS62110-EP
TPS62111-EP
TPS62112-EP
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.............................................................................................................................................................. SLVS630C APRIL 2007 REVISED MAY 2008
The TPS6211x is a synchronous step-down converter that operates with a 1 MHz fixed frequency pulse widthmodulation (PWM) at moderate-to-heavy load currents and enters the power save mode at light load current.
During PWM operation, the converter uses a unique fast response voltage mode control scheme with inputvoltage feedforward. Good line and load regulation is achieved with the use of small input and output ceramiccapacitors. At the beginning of each clock cycle initiated by the clock signal (S), the P-channel MOSFET switchis turned on, and the inductor current ramps up until the comparator trips and the control logic turns the switchoff. The switch is turned off by the current limit comparator if the current limit of the P-channel switch isexceeded. After the dead time prevents current shoot through, the N-channel MOSFET rectifier is turned on, andthe inductor current ramps down. The next cycle is initiated by the clock signal turning off the N-channel rectifier,and turning on the P-channel switch.
The error amplifier as well as the input voltage determines the rise time of the sawtooth generator. Therefore,any change in input voltage or output voltage directly controls the duty cycle of the converter giving a very goodline and load transient regulation.
In constant frequency mode, the output voltage is regulated by varying the duty cycle of the PWM signal in therange of 100% to 10%. Connecting the SYNC pin to a voltage greater than 1.5 V forces the converter to operatepermanently in the PWM mode even at light or no-load currents. The advantage is that the converter operateswith a fixed switching frequency that allows simple filtering of the switching frequency for noise-sensitiveapplications. In this mode, the efficiency is lower compared to the power save mode during light loads. TheN-MOSFET of the devices stay on even when the current into the output drops to zero. This prevents the devicefrom going into discontinuous mode, and the device transfers unused energy back to the input. Therefore, thereis no ringing at the output, which usually occurs in discontinuous mode. The duty cycle range in constantfrequency mode is 100% to 10%.
It is possible to switch from forced PWM mode to the power save mode during operation by pulling the SYNC pinLOW. The flexible configuration of the SYNC pin during operation of the device allows efficient powermanagement by adjusting the operation of the TPS6211x to the specific system requirements.
As the load current decreases, the converter enters the power save mode operation. During power save mode,the converter operates with reduced switching frequency in pulse frequency modulation (PFM), and with aminimum quiescent current to maintain high efficiency. Whenever the average output current goes below the skipthreshold, the converter enters the power save mode. The average current depends on the input voltage. It isabout 200 mA at low input voltages and up to 400 mA with maximum input voltage. The average output currentmust be below the threshold for at least 32 clock cycles to enter the power save mode. During the power savemode, the output voltage is monitored with a comparator and the output voltage is regulated in to a typical valuebetween the nominal output voltage and 0.8% above the nominal output voltage. When the output voltage fallsbelow the nominal output voltage, the P-channel switch turns on. The P-channel switch is turned off as the peakswitch current is reached. The N-channel rectifier is turned on, and the inductor current ramps down. As theinductor current approaches zero, the N-channel rectifier is turned off and the switch is turned on starting thenext pulse. When the output voltage can not be reached with a single pulse, the device continues to switch withits normal operating frequency until the comparator detects the output voltage to be 0.8% above the nominaloutput voltage. This control method reduces the quiescent current to 20 µ A (typical), and reduces the switchingfrequency to a minimum that achieves the highest converter efficiency.
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V (nominal)
O
0.8%
1.6%
-1.6%
t
W
»
2 5
I
V
S K I P
I
(1)
SOFT START
100% DUTY CYCLE LOW DROPOUT OPERATION
( )
)(
max
)(
maxmaxmin L
R
onDS
r
O
I
O
V
I
V+×+=
(2)
TPS62110-EP
TPS62111-EP
TPS62112-EP
SLVS630C APRIL 2007 REVISED MAY 2008 ..............................................................................................................................................................
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DETAILED DESCRIPTION (continued)
Figure 18. Power Save Mode Output Voltage Thresholds
The typical PFM (SKIP) current threshold for the TPS6211x is given by:
Equation 1 is valid for input voltages up to 7 V. For higher voltages, the skip current threshold is not increasedfurther. The converter enters the fixed frequency PWM mode as soon as the output voltage falls below V
O
1.6% (nominal).
The TPS6211x has an internal soft-start circuit that limits the inrush current during start-up. This preventspossible voltage drops of the input voltage when a battery or a high-impedance power source is connected to theinput of the TPS6211x.
The soft start is implemented as a digital circuit increasing the switch current in steps of 300 mA, 600 mA,1200 mA. The typical switch current limit is 2.4 A. Therefore, the start-up time depends on the output capacitorand load current. Typical start-up time with a 22 µF output capacitor and 800-mA load current is 1 ms.
The TPS6211x offers the lowest possible input to output voltage difference while still maintaining operation withthe use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This isparticularly useful in battery-powered applications to achieve the longest operation time, taking full advantage ofthe whole battery voltage range. The minimum input voltage to maintain regulation depends on the load currentand output voltage, and is calculated as:
with:
I
O
max = maximum output current plus inductor ripple currentr
DS(on)
max = maximum P-channel switch r
DS(on)R
(L)
= dc resistance of the inductorV
O
max = nominal output voltage plus maximum output voltage tolerance
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ENABLE
UNDERVOLTAGE LOCKOUT
SYNCHRONIZATION
POWER GOOD COMPARATOR
LOW-BATTERY DETECTOR
TPS62110-EP
TPS62111-EP
TPS62112-EP
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.............................................................................................................................................................. SLVS630C APRIL 2007 REVISED MAY 2008
DETAILED DESCRIPTION (continued)
Logic low on EN forces the TPS6211x into shutdown. In shutdown, the power switch, drivers, voltage reference,oscillator, and all other functions are turned off. The supply current is reduced to less than 2 µA in the shutdownmode. When the device is in thermal shutdown, the bandgap is forced to be switched on even if the device is setinto shutdown by pulling EN to GND.
If an output voltage is present when the device is disabled, which could be due to an external voltage source or asuper capacitor, the reverse leakage current is specified under electrical characteristics. Pulling the enable pinhigh starts up the TPS6211x with the soft start. If the EN pin is connected to any voltage other than V
I
or GND,an increased leakage current of typically 10 µA and up to 20 µA can occur.
The undervoltage lockout circuit prevents the device from misoperation at low-input voltages. It prevents theconverter from turning on the switch or rectifier MOSFET under undefined conditions. The minimum input voltageto start up the TPS6211x is 3.4 V (worst case). The device shuts down at 2.8 V minimum.
If no clock signal is applied, the converter operates with a typical switching frequency of 1 MHz. It is possible tosynchronize the converter to an external clock within a frequency range from 0.8 MHz to 1.4 MHz. The deviceautomatically detects the rising edge of the first clock and synchronizes immediately to the external clock. If theclock signal is stopped, the converter automatically switches back to the internal clock and continues operation.The switch over is initiated if no rising edge on the SYNC pin is detected for a duration of four clock cycles.Therefore, the maximum delay time can be 6.25 µs if the internal clock has its minimum frequency of 800 kHz.
If the device is synchronized to an external clock, the power save mode is disabled, and the devices stay inforced PWM mode.
Connecting the SYNC pin to the GND pin enables the power save mode. The converter operates in the PWMmode at moderate-to-heavy loads, and in the PFM mode during light loads, which maintains high efficiency overa wide load current range.
The power good (PG) comparator has an open-drain output capable of sinking 1 mA (typical). The PG is activeonly when the device is enabled (EN=high). When the device is disabled (EN=low), the PG pin is pulled to GND.
The PG output is valid only after a 250- µs delay when the device is enabled, and the supply voltage is greaterthan the undervoltage lockout V
(UVLO)
. PG is low during the first 250 µs after shutdown and in shutdown.
The PG pin becomes active high when the output voltage exceeds 98.4% (typical) of its nominal value. Leavethe PG pin unconnected when not used.
The low-battery output (LBO) is an open-drain type which goes low when the voltage at the low-battery input(LBI) falls below the trip point of 1.256 V ± 1.5%. The voltage at which the low-battery warning is issued can beadjusted with a resistive divider as shown in Figure 19 . The sum of resistors (R1 + R2) as well as the sum of (R5+ R6) is recommended to be in the 100 k to 1 M range for high efficiency at low output current. An externalpullup resistor can be connected to OUT, or any other voltage rail in the voltage range of 0 V to 16 V. Duringstart-up, the LBO output signal is invalid for the first 500 µs. LBO is high impedance when the device is disabled.If the low-battery comparator function is not used, connect LBI to ground. The low-battery detector is disabledwhen the device is disabled.
The logic level of the LBO pin is not defined for the first 500 µs after EN is pulled high.
When the LBI is used to supervise the battery voltage and shut down the TPS62111 at low-input voltages, thebattery voltage rises when the current drops to zero. The implemented hysteresis on the LBI pin may not besufficient for all types of batteries. Figure 19 shows how an additional external hysteresis can be implemented.
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