AD2S44TM12B - ANALOG DEVICES

Low Cost, 14-Bit, Dual Channel

Synchro/Resolver-to-Digital Converter

Data Sheet

AD2S44

Rev. B

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FEATURES

Low per-channel cost

32-lead DIL hybrid package

2.6 arc minute accuracy

14-bit resolution

Built-in test

Independent reference inputs

High tracking rate

APPLICATIONS

Gimbal/gyro control systems

Robotics

Engine controllers

Coordinate conversion

Military servo control systems

Fire control systems

Avionic systems

Antenna monitoring

CNC machine tooling

GENERAL DESCRIPTION

The AD2S44 is a 14-bit dual channel, continuous tracking synchro/

resolver-to-digital converter. It has been designed specifically

for applications where space, weight, and cost are at a premium.

Each 32-lead hybrid device contains two independent Type II servo

loop tracking converters. The ratiometric conversion technique

employed provides excellent noise immunity and tolerance of

long lead lengths.

The core of each conversion is performed by state-of-the-art mono-

lithic, integrated circuits manufactured by the Analog Devices, Inc.,

proprietary BiMOS II process, which combines the advantages of

low power CMOS digital logic with bipolar linear circuits. The

use of these ICs keeps the internal component count low and

ensures high reliability.

The built-in test (BIT) facility can be used in failsafe systems to

provide an indication of whether the converter is tracking

accurately.

Each channel incorporates a high accuracy differential condi-

tioning circuit for signal inputs providing more than 74 dB of

common-mode rejection. Options are available for both synchro

and resolver format inputs. The converter output is via a three-state

transparent latch allowing data to be read without interruption

of the converter operation. The A/B and OE control lines select

the channel and present the digital position to the common

data outputs.

The AD2S44 also features independent reference inputs where

different reference frequencies can be used for each channel.

All components are 100% tested at −55°C, +25°C, and +125°C.

Devices are processed to high reliability screening standards

and receive further levels of testing and screening to ensure

high levels of reliability.

FUNCTIONAL BLOCK DIAGRAM

AD2S44

REFERENCE

CONDITIONER

SYNCHRO/

RESOLVER

CONDITIONER

PHASE-

SENSITIVE

DETECTOR

THREE-

STATE

OUTPUT

LATCHES DB1 (MSB)

DB14 (L S B)

PHASE-

SENSITIVE

DETECTOR

HIGH

SPEED

SIN/COS

MULTIPLIER

BUILT-IN

TEST

DETECTION

ERROR

AMP UP-DOWN

COUNTER

UP-DOWN

COUNTER

INTEGRATOR VCO

VCO

INTEGRATOR

ERROR

AMP

HIGH

SPEED

SIN/COS

MULTIPLIER

SYNCHRO/

RESOLVER

CONDITIONER

REFERENCE

CONDITIONER

S3 (A)

HI ( A)

RLO (A)

RHI ( B)

RLO (B)

+VS

–VS

GND

S4 (A)

S1 (A)

S2 (A)

S3 (B)

S4 (B)

S1 (B)

S2 (B)

A/B

BIT

02947-001

Figure 1.

AD2S44* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

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DOCUMENTATION

Application Notes

•AN-214: Ground Rules for High Speed Circuits

•AN-263: Resolver to Digital Conversion; Simple Alternative

to Optical Shaft Encoders

•AN-264: Dynamic Characteristics of Tracking Converter

Data Sheet

•AD2S44: Low Cost, 14-Bit, Dual Channel Synchro/

Resolver-to-Digital Converter Data Sheet

REFERENCE MATERIALS

Technical Articles

•DSP Motor Control in Domestic Appliance Applications

•Single Chip DSP Motor Control Systems Catching on in

Home Appliances

DESIGN RESOURCES

•AD2S44 Material Declaration

•PCN-PDN Information

•Quality And Reliability

•Symbols and Footprints

DISCUSSIONS

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AD2S44 Data Sheet

Rev. B | Page 2 of 12

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Table of Contents .............................................................................. 2

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Theory of Operation ........................................................................ 7

Connecting the Converter ........................................................... 7

Channel Select (A/B) ................................................................... 7

Output Enable (OE) ......................................................................8

Built-In Test (BIT) .........................................................................8

Scaling for Nonstandard Signals .................................................9

Dynamic Performance ..................................................................9

Acceleration Error .........................................................................9

Reliability ..................................................................................... 10

Processing for High Reliability (B Suffix) ............................... 10

Other Products ........................................................................... 10

Outline Dimensions ....................................................................... 11

Ordering Guide .......................................................................... 11

Ordering Information ................................................................ 11

REVISION HISTORY

10/11—Rev. A to Rev. B

Changes to Figure 1 .......................................................................... 1

Changes to Figure 3 .......................................................................... 7

08/08—Rev. 0 to Rev. A

Updated Format ................................................................ Universal

Changes to Specifications Section .................................................. 3

Changes to Absolute Maximum Ratings Section ......................... 5

Deleted Standard Processing Section ............................................. 7

Changes to Processing for High Reliability Section and

Other Products Section ................................................................. 10

Updated Outline Dimensions ....................................................... 11

Changes to Ordering Guide .......................................................... 11

Changes to Ordering Information ............................................... 11

10/89—Revision 0: Initial Version

Data Sheet AD2S44

Rev. B | Page 3 of 12

SPECIFICATIONS

VS = ±15 V at TA = 25°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

PERFORMANCE

Accuracy1

AD2S44-UMB2 −4.0 +4.0 Arc minutes −55°C to +125°C

−2.6 +2.6 Arc minutes −25°C to +85°C

AD2S44-TMB2 −4.0 +4.0 Arc minutes −55°C to +125°C

Tracking Rate 20 Rev/sec

Resolution (1 LSB = 1.3 Arc Minutes) 14 Bits Output coding parallel natural binary

Repeatability 1 LSB

Signal/Reference Frequency 400 2600 Hz

Bandwidth 100 Hz

SIGNAL INPUTS

Signal Voltage 11.8 or 90 V rms See the Ordering Information section

Input Impedance

90 V Signal 200 kΩ Resistive tolerance ±2%

11.8 V Signal 26 kΩ

Common-Mode Rejection 74 dB

Common-Mode Range

90 V Signal ±250 V dc

11.8 V Signal ±60 V dc

REFERENCE INPUTS

Reference Voltage 26 or 115 V rms See the Ordering Information section

Input Impedance

115 V 270 kΩ Resistive tolerance ±5%

26 V

270

kΩ

Common-Mode Range

115 V ±210 V dc

26 V ±210 V dc

ACCELERATION CONSTANT 62,000 sec–2

STEP RESPONSE

Large Step

1, 2

179° to 1 LSB of error

Small Step1, 2 25 30 ms 2° to 1 LSB of error

POWER LINES

+VS = +15 V1, 2 75 80 mA Quiescent condition

–VS = −15 V1, 2 40 45 mA Quiescent condition

Power Dissipation 1.7 1.9 W Quiescent condition

DIGITAL INPUTS

VIL 0.7 V dc IIL = 5 µA

VIH 2.0 V dc IIH = 5 µA

A/B

0.7

V dc

= 1.2 mA

VIH 2.0 V dc IIH = –60 µA

DIGITAL OUTPUTS (DB1 to DB14)

OL1, 2

0.4

V dc

= 1.2 mA

VOH1, 2 2.4 V dc IOH = 60 µA

Three-State Leakage Current ±40 µA

Drive Capability 3 LSTTL loads

AD2S44 Data Sheet

Rev. B | Page 4 of 12

Parameter Min Typ Max Unit Test Conditions/Comments

DATA TRANSFER See Figure 6

Time to Data Stable (After Negative Edge of OE

or Change of Level of A/B)

640 ns tS

Time to Data in High Impedance State

(After Positive Edge of OE)

200 ns tR

Time for Repetitive Strobing of Selected Channel 200 ns tP

BUILT-IN TEST OUTPUT (BIT)

Sense

Active low

Low = error condition

VOL 0.4 V dc IOL = 3.2 mA

VOH 2.4 V dc IOH = −160 µA

Drive Capability 8 LSTTL loads

Error Condition Set 55 LSB

Error Condition Cleared 45 LSB

1 Specified overtemperature range, −55°C to +125°C, and for: (a) ±10% signal and reference amplitude variation; (b) ±10% signal and reference harmonic distortion; (c)

±5% power supply variation; and (d) ±10% variation in reference frequency.

2 These parameters are 100% tested at nominal values of power supplies, input signal voltages, and operating frequency. All other parameters are guaranteed by

design, not tested.

Data Sheet AD2S44

Rev. B | Page 5 of 12

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter

Rating

+VS to GND +17.25 V dc

–VS to GND −17.25 V dc

Any Logic Input to GND +6.0 V dc (maximum)

Any Logic Input to GND −0.4 V dc (minimum)

Maximum Junction Temperature 150°C

S1, S2, S3, S4 Pins (Line-to-Line)1

90 V Option ±600 V dc

11.8 V Option

±80 V dc

S1, S2, S3, S4 Pins to GND

90 V Option ±600 V dc

11.8 V Option ±80 V dc

RHI Pins to RLO Pins

26 V, 115 V Options ±600 V dc

RHI Pins to RLO Pins to GND

26 V, 115 V Options ±600 V dc

Storage Temperature Range −65°C to +150°C

Operating Temperature Range −55°C to +125°C

1 On synchro input options, line-to-line voltage refers to the differential voltages

of S2 (A)/S2 (B) to S1 (A)/S1 (B), S1 (A)/S1 (B) to S3 (A)/S3 (B), and S3 (A)/S3 (B)

to S2 (A)/S2 (B). On resolver input options, line-to-line levels refer to the S1 (A)/

S1 (B) to S3 (A)/S3 (B) and S2 (A)/S2 (B) to S4 (A)/S4 (B) voltages.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

AD2S44 Data Sheet

Rev. B | Page 6 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DB9

DB10

DB11

DB14 (L S B)

DB13

DB12

DB8

DB6

DB5

DB4

DB1 (MS B)

DB2

DB3

A/B

BIT

S3 (A)

(A)

–V

GND

S3 (B)

S4 (A) S4 (B)

S1 (A) S1 (B)

S2 (A) S2 (B)

(B)

DB7

AD2S44

TOP VIEW

(No t t o Scal e)

02947-003

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 7 DB8 to DB14 (LSB) Parallel Output Data Bits.

8 OE Output Enable Input.

9 A/B Channel A or Channel B Select Input.

BIT

Built-In Test Error Output.

11 RLO (A) Input Pin for Channel A Reference Low.

12 RHI (A) Input Pin for Channel A Reference High.

13 to 16 S4 (A) to S1 (A) Channel A Input Signal.

17 to 20 S1 (B) to S4 (B) Channel B Input Signal.

21 RHI (B) Input Pin for Channel B Reference High.

22 RLO (B) Input Pin for Channel B Reference Low.

23 GND Power Supply Ground. This pin is electrically connected to the case.

24 –VS Negative Power Supply.

25 +VS Positive Power Supply.

26 to 32 DB1 (MSB) to DB7 Parallel Output Data Bits.

Data Sheet AD2S44

Rev. B | Page 7 of 12

THEORY OF OPERATION

The AD2S44 operates on a tracking principle. The output digital

word continually tracks the position of the synchro/resolver

shaft without the need for external convert commands and

status wait loops. As the transducer moves through a position

equivalent to the least significant bit weighting, the output

digital word is updated.

Each channel is identical in operation, sharing power supply

and output pins. Both channels operate continuously and

independently of each other. The digital output from either

channel is available after switching the channel select and

output enable inputs.

If the device is a synchro-to-digital converter, the 3-wire synchro

output is connected to the S1, S2, and S3 pins on the unit, and

a solid-state Scott T input conditioner converts these signals into

resolver format given by

V1 = K E0 sin ωt sin θ

V2 = K E0 sin ωt cos θ

where:

θ is the angle of the synchro shaft.

E0 sin ωt is the reference signal.

K is the transformation ratio of the input signal conditioner.

If the unit is a resolver-to-digital converter, the 4-wire resolver

output is connected directly to the S1, S2, S3, and S4 pins on

the unit.

To understand the conversion process, assume that the current

word state of the up-down counter is ϕ. V1 is multiplied by cos ϕ,

and V2 is multiplied by sin ϕ to give the following:

K E0 sin ωt sin θ cos ϕ

K E0 sin ωt cos θ sin ϕ

These signals are subtracted by the error amplifier to give

K E0 sin ωt (sin θ cos ϕ − cos θ sin ϕ)

K E0 sin ωt sin (θ − ϕ)

A phase sensitive detector, integrator, and voltage-controlled

oscillator (VCO) form a closed-loop system that seeks to null sin

(θ − ϕ). When this is accomplished, the word state of the up-down

counter (ϕ) equals the synchro/resolver shaft angle (θ), to within

the rated accuracy of the converter.

CONNECTING THE CONVERTER

The power supply voltages connected to −VS and +VS are to be

±15 V and cannot be reversed.

It is suggested that a parallel combination of a ceramic 100 nF

capacitor and a tantalum 6.8 µF capacitor be placed from each

of the supply pins to GND.

The pin marked GND is connected electrically to the case and

is to be taken to 0 V potential in the system.

The digital output is taken from Pin 26 to Pin 32 and from Pin 1

to Pin 7. Pin 26 is the MSB, and Pin 7 is the LSB.

The reference connections are made to the RHI pins and the RLO

pins. In the case of a synchro, the signals are connected to the

S1, S2, and S3 pins, according to the following convention:

ES1−S3 = ERLO−RHI sin ωt sin θ

ES3−S2 = ERLO−RHI sin ωt sin (θ − 120°)

ES2−S1 = ERLO−RHI sin ωt sin (θ – 240°)

For a resolver, the signals are connected to the S1, S2, S3, and S4

pins, according to the following convention:

ES1−S3 = ERLO−RHI sin ωt sin θ

ES2−S4 = ERLO−RHI sin ωt cos θ

CHANNEL SELECT (A/B)

A/B is the channel select input. A Logic 1 selects Channel A, and

a Logic 0 selects Channel B. Data becomes valid 640 ns after A/B

is toggled. Timing information is shown in Figure 4 and Figure 5.

AD2S44

REFERENCE

CONDITIONER

SYNCHRO/

RESOLVER

CONDITIONER

PHASE-

SENSITIVE

DETECTOR

THREE-

STATE

OUTPUT

LATCHES DB1 ( MSB)

DB14 (LSB)

PHASE-

SENSITIVE

DETECTOR

HIGH

SPEED

SIN/COS

MULTIPLIER

BUILT-IN

TEST

DETECTION

ERROR

AMP UP-DOWN

COUNTER

UP-DOWN

COUNTER

INTEGRATOR VCO

VCO

INTEGRATOR

ERROR

AMP

HIGH

SPEED

SIN/COS

MULTIPLIER

SYNCHRO/

RESOLVER

CONDITIONER

REFERENCE

CONDITIONER

S3 ( A)

(A)

(B)

–V

GND

S4 ( A)

S1 ( A)

S2 ( A)

S3 ( B)

S4 ( B)

S1 ( B)

S2 ( B)

A/B

BIT

02947-010

Figure 3. Functional Block Diagram

AD2S44 Data Sheet

Rev. B | Page 8 of 12

OUTPUT ENABLE (OE)

OE is the output enable input; the signal is active low. When set

to Logic 1, DB1 to DB14 are in high impedance state. When OE

is set to Logic 0, DB1 to DB14 represent the angle of the transducer

shaft to within the stated accuracy of the converter (see bit weights

in Table 4). Data becomes valid 640 ns after the OE is switched.

Timing information is shown in Figure 4 and Figure 5 and

detailed in Table 1.

Table 4. Bit Weight

Bit No. Weight (Degrees)

1 (MSB) 180.0000

90.0000

3 45.0000

4 22.5000

5 11.2500

6 5.6250

7 2.8125

8 1.4063

9 0.7031

10 0.3516

11 0.1758

12 0.0879

0.0439

14 ( LSB) 0.0220

CHANNEL B

VALID*CHANNEL A

VALID*

A/B

DATA

BITS

(1 TO 14)

*CONVE RTER D ATA OUTPUT IS INHIBITED FROM UPDATES

DURING CHANNEL VALID.

02947-005

Figure 4. Repetitive Reading of One Channel

A/B

DATA

BITS

(1 TO 14)

DATA

VALID*DATA

VALID*

*CONVE RTER DATA OUTPUT IS INHIBITED FROM UPDATES

DURING CHANNEL VALID.

02947-004

Figure 5. Alternative Reading of Each Channel

BUILT-IN TEST (BIT)

The BIT is the built-in test error output, which provides an over-

velocity or fault indication signal for the channel selected via A/B.

The error voltage of each channel is continuously monitored. When

the error exceeds ±50 bits for the currently selected channel, the

BIT output goes low, indicating that an error greater than approx-

imately one angular degree exists, and the data is, therefore, invalid.

The BIT signal has a built-in hysteresis; that is, the error required to

set the BIT is greater than the error required for it to be cleared.

The BIT is set when the error exceeds 55 LSBs and is cleared when

the error goes below 45 LSBs. This mode of operation guarantees

that the BIT does not flicker when the error threshold is crossed.

The BIT is valid for the selected channel approximately 50 ns after

the change in the state of A/B. In most instances, the error condi-

tion that sets the BIT must persist for at least one period of the

reference signal prior to the BIT responding to the condition.

Table 5. BIT Output Faults

Condition Description

Power-Up Transient

Response

The BIT returns to a logic high state after

the AD2S44 position output synchronizes

with the angle input to within 1°.

Normally, the BIT is low at power-up for

a period less than or equal to the large

signal step response settling time of the

AD2S44 after the ±VS supplies have

stabilized to within 5% of their final values.

Step Input > 1° The BIT returns to a logic high state after

the selected channel of the AD2S44 has

settled to within 1° of the input angle

resulting from an instantaneous step.

Excessive Velocity The BIT is driven to a logic low if the

maximum tracking rate of the AD2S44 is

exceeded (20 rps typical).

Signal Failure The BIT may be driven to a logic low state if

all signal voltages to the selected channel

are lost.

Converter/System

Failure

Any failure that causes the AD2S44 to fail

to track the input synchro/resolver angles

drives the BIT to a logic low. This may

include, but is not limited to, acceleration

conditions, poor supply voltage regulation,

or excessive noise on the signal connections.

Data Sheet AD2S44

Rev. B | Page 9 of 12

SCALING FOR NONSTANDARD SIGNALS

A feature of these converters is that the signal and reference inputs

can be resistively scaled to accommodate nonstandard input signal

and reference voltages that are outside the nominal ±10% limits of

the converter. Using this technique, it is possible to use a standard

converter with a personality card in systems where a wide range

of input and reference voltages are encountered.

The accuracy of the converter is affected by the matching accu-

racies of resistors used for external scaling. For resolver format

options, it is critical that the value of the resistors on the S1 (A)/

S1 (B) to S3 (A)/S3 (B) signal input pair be precisely matched to

the S4 (A)/S4 (B) to S2 (A)/S2 (B) input pair. For synchro options,

the three resistors on the S1, S2, and S3 pins must be matched. In

general, a 0.1% mismatch between resistor values contributes an

additional 1.7 arc minutes of error to the conversion. In addition,

imbalances in resistor values can greatly reduce the common-

mode rejection ratio of the signal inputs.

To calculate the values of the external scaling resistors, add

2.222 kΩ for each volt of signal in series with the S1, S2, S3, and

S4 pins (no resistor is required on the S4 pins for synchro options)

and add 3 kΩ extra per volt of reference in series with the RLO

pins and the RHI pins.

DYNAMIC PERFORMANCE

OUT

1 + sT

02947-006

Figure 6. Transfer Function of AD2S44

The transfer function of the converter is as follows:

Open-loop transfer function

OUT

×=

Closed-loop transfer function

OUT

KTsKssT

+++

where:

Ka = 62000 sec–2.

T1 = 0.0061 sec.

T2 = 0.001 sec.

The gain and phase diagrams are shown in Figure 7 and Figure 8.

FREQUENCY (Hz)

GAIN (d B)

–15

–12

–9

–6

–3

10 100

02947-007

Figure 7. Gain Plot

FREQUENCY (Hz)

PHASE ( Degrees)

180

135

–180

–135

–90

–45

10 100

02947-008

Figure 8. Phase Plot

ACCELERATION ERROR

A tracking converter employing a Type II servo loop does not

suffer any velocity lag. However, there is an additional error

due to acceleration. This error is defined using the acceleration

constant (Ka) of the converter

Ka = Input Acceleration/Error in Output Angle

The numerator and denominator must have consistent angular

units. For example, if Ka is expressed in sec–2, the input accelera-

tion is to be specified in degrees/sec2 and the output angle error is

to be specified in degrees. Alternatively, the angular unit of measure

can also be in units such as radians, arc minutes, or LSBs.

AD2S44 Data Sheet

Rev. B | Page 10 of 12

Ka does not define maximum acceleration; it defines only the

error due to acceleration. The maximum acceleration of which

the AD2S44 keeps track is approximate to 5 × Ka = 310,000°/sec2

or about 800 revolutions/sec2.

Ka can be used to predict the output position error due to input

acceleration. For example, an acceleration of 50 revolutions/sec2

with Ka = 62,000 is calculated using the following equation:

[ ]













=−2

sec

LSB

onAcceleratiInput

LSBsinErrors

[ ]

LSBs

rev

LSBrev

2.13

sec000,62

sec

























−

RELIABILITY

The reliability of these products is very high due to the extensive

use of custom chip circuits that decrease the active component

count. Calculations of the MTBF figure under various environ-

mental conditions are available upon request from Analog

Devices.

Figure 9 shows the MTBF in years vs. case temperature for

Naval Sheltered conditions calculated in accordance with the

Mil-Hdbk-217E.

TEMPERATURE ( °C)

MTBF (Years)

100

125 6545 85 105 125

02947-009

Figure 9. MTBF vs. Temperature

PROCESSING FOR HIGH RELIABILITY (B SUFFIX)

As a part of the high reliability manufacturing procedure, all

converters receive the processing shown in Tabl e 6.

Table 6.

Process1 Conditions

Precap Visual Inspection MIL-STD-883, Method 2017

Temperature Cycling 10 cycles, –65°C to +150°C

Constant Acceleration 5000 Gs, Y1 plane

Interim Electrical Tests @ 25°C

Operating Burn In

160 hours @ 125°C

Seal Test, Fine and Gross MIL-STD-883, Method 1014

Final Electrical Test Performed at TMIN, TAMB, TMAX

External Visual Inspection MIL-STD-883, Method 2009

1 Test and screening data supplied by request.

OTHER PRODUCTS

Analog Devices manufactures many other products concerned

with the conversion of synchro/resolver data, such as the

SDC/RDC1740 series and the AD2S80A series.

Hybrid

The SDC/RDC1740 is a hybrid synchro/resolver-to-digital

converter with internal isolating micro transformers.

Monolithic

The AD2S80A series are ICs performing resolver-to-digital

conversion with accuracies up to ±2 arc minutes and 16-bit

resolution.

Data Sheet AD2S44

Rev. B | Page 11 of 12

OUTLINE DIMENSIONS

NOTES:

1. INDEX AREA IS INDICATED BY A NOTCH OR LEAD ONE

IDENTIFICATION MARK LOCATED ADJACENT TO LEAD ONE.

2. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

0.023 (0.58)

0.014 (0.36)

0.910 (23.11)

0.890 (22.61)

116

1.728 (43.89) MAX

0.225 (5.72)

MAX

0.025 (0.64)

0.015 (0.38)

0.008 (0.20)

1.102 (27.99)

1.079 (27.41)

0.100 (2.54)

BSC 0.070 (1.78)

0.030 (0.76)

0.120 (3.05)

MAX

PIN 1

INDICATOR

(NOTE 1)

0.192 (4.88)

0.152 (3.86) 0.206 (5.23)

0.186 (4.72)

0.025 (0.64)

MIN

Figure 10. 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H]

(DH-32E)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD2S44–TM11B −55°C to +125°C 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] DH-32E

AD2S44–TM12B −55°C to +125°C 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] DH-32E

AD2S44–TM18B −55°C to +125°C 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] DH-32E

AD2S44–UM18B −55°C to +125°C 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] DH-32E

ORDERING INFORMATION

When ordering, the converter part numbers are to be suffixed by

a two-letter code defining the accuracy grade, and a two digit

numeric code defining the signal/reference voltage and frequency.

All the standard options, and their option codes, are shown in

Figure 11. For nonstandard configurations, contact Analog

Devices.

For example, the AD2S44–TM12B is the correct part number

for a component that operates with 90 V signal, 115 V reference

synchro format inputs and yields a ±4.0 arc minutes accuracy

over the −55°C to +125°C temperature range processed to high

reliability standards.

AD2S44-

BASE PART

NUMBER

HIGH-REL PROCESSING

XM Y BZ

02947-002

*MODEL IS OBSOLETE AND NO LO NGER AVAILABLE.

Z = 0* SIGNAL, 2V REFERENCE, 2 V RESO L VER

Z = 1 SIGNAL, 11 .8V REF ERENCE , 26V S YNCHRO

Z = 2 SIGNAL, 90 V REF ERENCE , 115 V SY NCHRO

Z = 3* SIGNAL, 11 . 8 V REFERENCE, 1 1.8V RESO LVER

Z = 4* SIGNAL, 26 V REFERENCE, 26 V RESO L VER

BASE PART

Z = 8 SIGNAL, 11 . 8 V REFERENCE, 2 6V RESOLVER

Y = 1 400Hz TO 2.6k Hz REF ERENCE F REQUENCY

X = U –55° C T O + 1 25 ° C OPERATING TEM P ERATURE

RANGE

±4. 0 ARC M IN ACCURACY

±2. 6 ARC M IN ACCURACY (–25 ° C T O + 85 ° C)

X = T –5 5 ° C TO + 1 2 5 ° C OPERATING T EMPERATURE

RANGE±4.0 ARC MI N ACCURACY

X = S* –55° C T O + 1 25 ° C OPERATING TEM P ERATURE

RANGE±5.2 ARC MI N ACCURACY

Figure 11.

AD2S44 Data Sheet

Rev. B | Page 12 of 12

registered trademarks are the property of their respective owners.

D02947-0-10/11(B)

NOTES