AT87F55WD-33AC - Atmel Corporation

PLCC

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

Features

•Compatible with MCS-51™ Products

•20K Bytes of One-time Programmable QuickFlash Memory

•4V to 5.5V Operating Range

•Fully Static Operation: 0 Hz to 33 MHz

•Three-level Program Memory Lock

•256 x 8-bit Internal RAM

•32 Programmable I/O Lines

•Three 16-bit Timer/Counters

•Eight Interrupt Sources

•Programmable Serial Channel

•Low-power Idle and Power-down Modes

•Interrupt Recovery from Power-down Mode

•Hardware Watchdog Timer

•Dual Data Pointer

•Power-off Flag

Description

The AT87F55WD is a low-power, high-performance CMOS 8-bit microcomputer with

20K bytes of QuickFlash one-time programmable (OTP) read only memory and 256

bytes of RAM. The device is manufactured using Atmel’s high-density nonvolatile

memory technology and is compatible with the industry standard 80C51 and 80C52

instruction set and pinout. The on-chip QuickFlash allows the program memory to be

user programmed by a conventional nonvolatile memory programmer. By combining a

versatile 8-bit CPU with QuickFlash on a monolithic chip, the Atmel AT87F55WD is a

powerful microcomputer which provides a highly-flexible and cost-effective solution to

many embedded control applications.

Rev. 1918A–08/00

8-bit

Microcontroller

with 20K Bytes

QuickFlash™

AT87F55WD

PDIP

(T2) P1.0

(T2EX) P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

P2.4 (A12)

P2.3 (A11)

P2.2 (A10)

P2.1 (A9)

P2.0 (A8)

Pin Configurations

TQFP

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

AT87F55WD

Block Diagram

PORT 2 DRIVERS

PORT 2

LATCH

P2.0 - P2.7

QUICK

FLASH

PORT 0

LATCH

RAM

PROGRAM

ADDRESS

BUFFER

INCREMENTER

PROGRAM

COUNTER

DUAL

DPTR

RAM ADDR.

INSTRUCTION

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

STACK

POINTER

ACC

TMP2 TMP1

ALU

PSW

TIMING

AND

CONTROL

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

OSC

GND

VCC

PSEN

ALE/PROG

EA / VPP

RST

PORT 0 DRIVERS

P0.0 - P0.7

WATCH

DOG

AT87F55WD

The AT87F55WD provides the following standard features:

20K bytes of QuickFlash, 256 bytes of RAM, 32 I/O lines,

three 16-bit timer/counters, a six-vector, two-level interrupt

architecture, a full-duplex serial port, on-chip oscillator, and

clock circuitry. In addition, the AT87F55WD is designed

with static logic for operation down to zero frequency and

supports two software selectable power saving modes. The

Idle Mode stops the CPU while allowing the RAM,

timer/counters, serial port, and interrupt system to continue

functioning. The Power-down mode saves the RAM con-

tents but freezes the oscillator, disabling all other chip func-

tions until the next external interrupt or hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open-drain bidirectional I/O port. As an

output port, each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 can also be configured to be the multiplexed low-

order address/data bus during accesses to external

program and data memory. In this mode, P0 has internal

pullups.

Port 0 also receives the code bytes during QuickFlash pro-

gramming and outputs the code bytes during program veri-

fication. External pullups are required during program

verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the

timer/counter 2 external count input (P1.0/T2) and the

timer/counter 2 trigger input (P1.1/T2EX), respectively, as

shown in the following table.

Port 1 also receives the low-order address bytes during

QuickFlash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @

DPTR). In this application, Port 2 uses strong internal pul-

lups when emitting 1s. During accesses to external data

memory that use 8-bit addresses (MOVX @ RI), Port 2

emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during QuickFlash programming and verifi-

cation.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

current (IIL) because of the pullups.

Port 3 also serves the functions of various special features

of the AT87F55WD, as shown in the following table.

Port 3 also receives some control signals for QuickFlash

programming and verification.

RST

Reset input. A high on this pin for two machine cycles while

the oscillator is running resets the device. This pin drives

high for 96 oscillator periods after the Watchdog times out.

The DISRTO bit in SFR AUXR (address 8EH) can be used

to disable this feature. In the default state of bit DISTRO,

the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Enable is an output pulse for latching the

low byte of the address during accesses to external

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2),

clock-out

P1.1 T2EX (Timer/Counter 2 capture/reload trigger

and direction control)

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (external interrupt 0)

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR (external data memory write strobe)

P3.7 RD (external data memory read strobe)

AT87F55WD

memory. This pin is also the program pulse input (PROG)

during QuickFlash programming.

In normal operation, ALE is emitted at a constant rate of 1/6

the oscillator frequency and may be used for external

timing or clocking purposes. Note, however, that one

ALE pulse is skipped during each access to external data

memory.

If desired, ALE operation can be disabled by setting bit 0 of

SFR location 8EH. With the bit set, ALE is active only dur-

ing a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no

effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro-

gram memory.

When the AT87F55WD is executing code from external

program memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are skipped during

each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from external pro-

gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be

internally latched on reset.

EA should be strapped to VCC for internal program execu-

tions.

This pin also receives the 12-volt programming enable volt-

age (VPP) during QuickFlash programming.

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Table 1. AT87F55WD SFR Map and Reset Values

0F8H 0FFH

0F0H B

00000000 0F7H

0E8H 0EFH

0E0H ACC

00000000 0E7H

0D8H 0DFH

0D0H PSW

00000000 0D7H

0C8H T2CON

00000000

T2MOD

XXXXXX00

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

TH2

00000000 0CFH

0C0H 0C7H

0B8H IP

XX000000 0BFH

0B0H P3

11111111 0B7H

0A8H IE

0X000000 0AFH

0A0H P2

11111111

AUXR1

XXXXXXX0

WDTRST

XXXXXXXX 0A7H

98H SCON

00000000

SBUF

XXXXXXXX 9FH

90H P1

11111111 97H

88H TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

AUXR

XXX00XX0 8FH

80H P0

11111111

00000111

DP0L

00000000

DP0H

00000000

DP1L

00000000

DP1H

00000000

PCON

0XXX0000 87H

AT87F55WD

Special Function Registers

A map of the on-chip memory area called the Special Func-

tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc-

cupied addresses may not be implemented on the chip.

Read accesses to these addresses will in general return

random data, and write accesses will have an indetermi-

nate effect.

User software should not write 1s to these unlisted loca-

tions, since they may be used in future products to invoke

new features. In that case, the reset or inactive values of

the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in

registers T2CON (shown in Table 2) and T2MOD (shown in

Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L)

are the Capture/Reload registers for Timer 2 in 16-bit cap-

ture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits

are in the IE register. Two priorities can be set for each of

the six interrupt sources in the IP register.

Table 2. T2CON – Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B

Bit Addressable

Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2

76543210

Symbol Function

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1

or TCLK = 1.

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When

Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared

by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port

Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer

2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.

C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).

CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0

causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When

either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

AT87F55WD

Dual Data Pointer Registers: To facilitate accessing both

internal and external data memory, two banks of 16-bit

Data Pointer Registers are provided: DP0 at SFR address

locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in

SFR AUXR1 selects DP0 and DPS = 1 selects DP1.

The user should always initialize the DPS bit to the appro-

priate value before accessing the respective Data Pointer

Power Off Flag: The Power Off Flag (POF) is located at bit

4 (PCON.4) in the PCON SFR. POF is set to “1” during

power up. It can be set and rest under software control and

is not affected by reset.

Table 3a. AUXR: Auxiliary Register

AUXR Address = 8EH Reset Value = XXX00XX0B

Not Bit Addressable

–––WDIDLE DISRTO ––DISALE

Bit 7 6 5 4 3 2 1 0

–Reserved for future expansion

DISALE Disable/Enable ALE

DISALE Operating mode

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency

1 ALE is active only during a MOVX or MOVC instruction

DISTRO Disable/Enable Reset out

DISRTO

0 Reset pin is driven High after WDT times out

1 Reset pin is input only

WDIDLE Disable/Enable WDT in IDLE mode

WDIDLE

0 WDT continues to count in IDLE mode

1 WDT halts counting in IDLE mode

Table 3b. AUXR1: Auxiliary Register 1

AUXR1 Address = A2H Reset Value = XXXXXXX0B

Not Bit Addressable

––– – – – –DPS

Bit 7 6 5 4 3 2 1 0

–Reserved for future expansion

DPS Data Pointer Register Select

DPS

0 Selects DPTR Registers DP0L, DP0H

1 Selects DPTR Registers DP1L, DP1H

AT87F55WD

Memory Organization

MCS-51 devices have a separate address space for Pro-

gram and Data Memory. Up to 64K bytes each of external

Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are

directed to external memory.

On the AT87F55WD, if EA is connected to VCC, program

fetches to addresses 0000H through 4FFFH are directed to

internal memory and fetches to addresses 5000H through

FFFFH are directed to external memory.

Data Memory

The AT87F55WD implements 256 bytes of on-chip RAM.

The upper 128 bytes occupy a parallel address space to

the Special Function Registers. That means the upper 128

bytes have the same addresses as the SFR space but are

physically separate from SFR space.

When an instruction accesses an internal location above

address 7FH, the address mode used in the instruction

specifies whether the CPU accesses the upper 128 bytes

of RAM or the SFR space. Instructions that use direct

addressing access SFR space.

For example, the following direct addressing instruction

accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper

128 bytes of RAM. For example, the following indirect

addressing instruction, where R0 contains 0A0H, accesses

the data byte at address 0A0H, rather than P2 (whose

address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect

addressing, so the upper 128 bytes of data RAM are avail-

able as stack space.

AT87F55WD

Hardware Watchdog Timer

(One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations

where the CPU may be subjected to software upsets. The

WDT consists of a 14-bit counter and the Watchdog Timer

Reset (WDTRST) SFR. The WDT is defaulted to disable

from exiting reset. To enable the WDT, a user must write

01EH and 0E1H in sequence to the WDTRST register

(SFR location 0A6H). When the WDT is enabled, it will

increment every machine cycle while the oscillator is run-

ning. There is no way to disable the WDT except through

reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will drive an output RESET HIGH pulse

at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in

sequence to the WDTRST register (SFR location 0A6H).

When the WDT is enabled, the user needs to service it by

writing 01EH and 0E1H to WDTRST to avoid a WDT over-

flow. The 14-bit counter overflows when it reaches 16383

(3FFFH), and this will reset the device. When the WDT is

enabled, it will increment every machine cycle while the

oscillator is running. This means the user must reset the

WDT at least every 16383 machine cycles. To reset the

WDT the user must write 01EH and 0E1H to WDTRST.

WDTRST is a write-only register. The WDT counter cannot

be read or written. When WDT overflows, it will generate an

output RESET pulse at the RST pin. The RESET pulse

duration is 98xTOSC, where TOSC=1/FOSC. To make the

best use of the WDT, it should be serviced in those sec-

tions of code that will periodically be executed within the

time required to prevent a WDT reset.

WDT During Power-down and Idle Mode

In Power-down mode the oscillator stops, which means the

WDT also stops. While in Power-down mode, the user

does not need to service the WDT. There are two methods

of exiting Power-down mode: by a hardware reset or via a

level-activated external interrupt which is enabled prior to

entering Power-down mode. When Power-down is exited

with hardware reset, servicing the WDT should occur as it

normally does whenever the AT87F55WD is reset. Exiting

Power-down with an interrupt is significantly different. The

interrupt is held low long enough for the oscillator to stabi-

lize. When the interrupt is brought high, the interrupt is ser-

viced. To prevent the WDT from resetting the device while

the interrupt pin is held low, the WDT is not started until the

interrupt is pulled high. It is suggested that the WDT be

reset during the interrupt service for the interrupt used to

exit Power-down.

To ensure that the WDT does not overflow within a few

states of exiting Power-down, it is best to reset the WDT

just before entering Power-down.

Before going into the IDLE mode, the WDIDLE bit in SFR

AUXR is used to determine whether the WDT continues to

count if enabled. The WDT keeps counting during IDLE

(WDIDLE bit = 0) as the default state. To prevent the WDT

from resetting the AT87F55WD while in IDLE mode, the

user should always set up a timer that will periodically exit

IDLE, service the WDT, and reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in

IDLE mode and resumes the count upon exit from IDLE.

UART

The UART in the AT87F55WD operates the same way as

the UART in the AT87F51 and AT87F52. For further infor-

mation, see the December 1997 Microcontroller Data Book,

page 2-48, section titled, “Serial Interface”.

Timer 0 and 1

Timer 0 and Timer 1 in the AT87F55WD operate the same

way as Timer 0 and Timer 1 in the AT87F51 and AT87F52.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either

a timer or an event counter. The type of operation is

selected by bit C/T2 in the SFR T2CON (shown in Table 2).

Timer 2 has three operating modes: capture, auto-reload

(up or down counting), and baud rate generator. The

modes are selected by bits in T2CON, as shown in Table 4.

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the

Timer function, the TL2 register is incremented every

machine cycle. Since a machine cycle consists of 12 oscil-

lator periods, the count rate is 1/12 of the oscillator fre-

quency.

Table 4. Timer 2 Operating Modes

In the Counter function, the register is incremented in

response to a 1-to-0 transition at its corresponding external

input pin, T2. In this function, the external input is sampled

during S5P2 of every machine cycle. When the samples

show a high in one cycle and a low in the next cycle, the

count is incremented. The new count value appears in the

RCLK +TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-reload

0 1 1 16-bit Capture

1 X 1 Baud Rate Generator

X X 0 (Off)

AT87F55WD

the transition was detected. Since two machine cycles (24

oscillator periods) are required to recognize a 1-to-0 transi-

tion, the maximum count rate is 1/24 of the oscillator fre-

quency. To ensure that a given level is sampled at least

once before it changes, the level should be held for at least

one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer

or counter which upon overflow sets bit TF2 in T2CON.

This bit can then be used to generate an interrupt. If

EXEN2 = 1, Timer 2 performs the same operation, but a 1-

to-0 transition at external input T2EX also causes the

current value in TH2 and TL2 to be captured into RCAP2H

and RCAP2L, respectively. In addition, the transition at

T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit,

like TF2, can generate an interrupt. The capture mode is

illustrated in Figure 5.

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when

configured in its 16-bit auto-reload mode. This feature is

invoked by the DCEN (Down Counter Enable) bit located in

the SFR T2MOD (see Table 5). Upon reset, the DCEN bit

is set to 0 so that timer 2 will default to count up. When

DCEN is set, Timer 2 can count up or down, depending on

the value of the T2EX pin.

Figure 5. Timer in Capture Mode

Figure 6 shows Timer 2 automatically counting up when

DCEN=0. In this mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to

0FFFFH and then sets the TF2 bit upon overflow. The

overflow also causes the timer registers to be reloaded with

the 16-bit value in RCAP2H and RCAP2L. The values in

Timer in Capture mode RCAP2H and RCAP2L are preset

by software. If EXEN2 = 1, a 16-bit reload can be triggered

either by an overflow or by a 1-to-0 transition at external

input T2EX. This transition also sets the EXF2 bit. Both the

TF2 and EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down,

as shown in Figure 6. In this mode, the T2EX pin controls

the direction of the count. A logic 1 at T2EX makes Timer 2

count up. The timer will overflow at 0FFFFH and set the

TF2 bit. This overflow also causes the 16-bit value in

RCAP2H and RCAP2L to be reloaded into the timer regis-

ters, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer

underflows when TH2 and TL2 equal the values stored in

RCAP2H and RCAP2L. The underflow sets the TF2 bit and

causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or

underflows and can be used as a 17th bit of resolution. In

this operating mode, EXF2 does not flag an interrupt.

OSC

EXF2

T2EX PIN

T2 PIN

TR2

EXEN2

C/T2 = 0

C/T2 = 1

CONTROL

CAPTURE

OVERFLOW

CONTROL

TRANSITION

DETECTOR TIMER 2

INTERRUPT

÷12

RCAP2LRCAP2H

TH2 TL2 TF2

AT87F55WD

Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)

Table 5. T2MOD – Timer 2 Mode Control Register

OSC

EXF2

TF2

T2EX PIN

T2 PIN

TR2

EXEN2

C/T2 = 0

C/T2 = 1

CONTR OL

RELOAD

CONTROL

TRANSITION

DETECTOR

TIMER 2

INTERRUPT

RCAP2LRCAP2H

TH2 TL2

OVERFLOW

T2MOD Address = 0C9H Reset Value = XXXX XX00B

Not Bit Addressable

––––––T2OE DCEN

Bit76543210

Symbol Function

–Not implemented, reserved for future

T2OE Timer 2 Output Enable bit.

DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.

AT87F55WD

Figure 7. Timer 2 Auto Reload Mode (DCEN = 1)

Figure 8. Timer 2 in Baud Rate Generator Mode

OSC

EXF2

TF2

T2EX PIN

COUNT

DIRECTION

1=UP

0=DO

T2 PIN

TR2

CONTROL

OVERFLOW

TOGGLE

TIMER 2

INTERRUPT

RCAP2LRCAP2H

0FFH0FFH

TH2 TL2

C/T2 = 0

C/T2 = 1

(DOWN COUNTING RELOAD VALUE)

(UP COUNTING RELOAD VALUE)

OSC

SMOD1

RCLK

TCLK

CLOCK

T2EX PIN

T2 PIN

TR2

CONTROL

"1"

"0"

TIMER 1 OVERFLOW

NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12

TIMER 2

INTERRUPT

RCAP2LRCAP2H

TH2 TL2

C/T2 = 0

C/T2 = 1

EXF2

CONTROL

TRANSITION

DETECTOR

EXEN2

AT87F55WD

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting

TCLK and/or RCLK in T2CON (Table 2). Note that

the baud rates for transmit and receive can be different if

Timer 2 is used for the receiver or transmitter and Timer 1

is used for the other function. Setting RCLK and/or TCLK

puts Timer 2 into its baud rate generator mode, as shown in

Figure 8.

The baud rate generator mode is similar to the auto-reload

mode, in that a rollover in TH2 causes the Timer 2 registers

to be reloaded with the 16-bit value in registers RCAP2H

and RCAP2L, which are preset by software.

The baud rates in modes 1 and 3 are determined by Timer

2’s overflow rate according to the following equation.

The Timer can be configured for either timer or counter

operation. In most applications, it is configured for timer

operation (CP/T2 = 0). The timer operation is different for

Timer 2 when it is used as a baud rate generator. Normally,

as a timer, it increments every machine cycle (at 1/12 the

oscillator frequency). As a baud rate generator, however, it

increments every state time (at 1/2 the oscillator fre-

quency). The baud rate formula is given below.

where (RCAP2H, RCAP2L) is the content of RCAP2H and

RCAP2L taken as a 16-bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 8. This

figure is valid only if RCLK or TCLK = 1 in T2CON. Note

that a rollover in TH2 does not set TF2 and will not gener-

ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0

transition in T2EX will set EXF2 but will not cause a reload

from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer

2 is in use as a baud rate generator, T2EX can be used as

an extra external interrupt.

Note that when Timer 2 is running (TR2 = 1) as a timer in

the baud rate generator mode, TH2 or TL2 should not be

read from or written to. Under these conditions, the Timer is

incremented every state time, and the results of a read or

write may not be accurate. The RCAP2 registers may be

read but should not be written to, because a write might

overlap a reload and cause write and/or reload errors. The

timer should be turned off (clear TR2) before accessing the

Timer 2 or RCAP2 registers.

Figure 9. Timer 2 in Clock-Out Mode

Mdes 1 and 3 Baud Rates Timer 2 Overflow Rate

------------------------------------------------------------=

Modes 1 and 3

Baud Rate

--------------------------------------- Oscillator Frequency

32 x [65536-RCAP2H,RCAP2L)]

--------------------------------------------------------------------------------------=

OSC

EXF2

P1.0

(T2)

P1.1

(T2EX)

TR2

EXEN2

C/T2 BIT

TRANSITION

DETECTOR

TIMER 2

INTERRUPT

T2OE (T2MOD.1)

2TL2

(8-BITS)

RCAP2L RCAP2H

TH2

(8-BITS)

AT87F55WD

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on

P1.0, as shown in Figure 9. This pin, besides being a regu-

lar I/O pin, has two alternate functions. It can be pro-

grammed to input the external clock for Timer/Counter 2 or

to output a 50% duty cycle clock ranging from 61 Hz to

4 MHz at a 16 MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit

C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)

must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator fre-

quency and the reload value of Timer 2 capture registers

(RCAP2H, RCAP2L), as shown in the following equation.

In the clock-out mode, Timer 2 roll-overs will not generate

an interrupt. This behavior is similar to when Timer 2 is

used as a baud-rate generator. It is possible to use Timer 2

as a baud-rate generator and a clock generator simulta-

neously. Note, however, that the baud-rate and clock-out

frequencies cannot be determined independently from one

another since they both use RCAP2H and RCAP2L.

Interrupts

The AT87F55WD has a total of six interrupt vectors: two

external interrupts (INT0 and INT1), three timer interrupts

(Timers 0, 1, and 2), and the serial port interrupt. These

interrupts are all shown in Figure 10.

Each of these interrupt sources can be individually enabled

or disabled by setting or clearing a bit in Special Function

disables all interrupts at once.

Note that Table 5 shows that bit position IE.6 is unimple-

mented. In the AT87F55WD, bit position IE.5 is also unim-

plemented. User software should not write 1s to these bit

positions, since they may be used in future AT89 products.

Timer 2 interrupt is generated by the logical OR of bits TF2

and EXF2 in register T2CON. Neither of these flags is

cleared by hardware when the service routine is vectored

to. In fact, the service routine may have to determine

whether it was TF2 or EXF2 that generated the interrupt,

and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at

S5P2 of the cycle in which the timers overflow. The values

are then polled by the circuitry in the next cycle. However,

the Timer 2 flag, TF2, is set at S2P2 and is polled in the

same cycle in which the timer overflows.

Table 6. Interrupt Enable (IE) Register

Figure 10. Interrupt Sources

Clock-out Frequency Oscillator Frequency

4 x [65536-(RCAP2H,RCAP2L)]

-------------------------------------------------------------------------------------=

(MSB) (LSB)

EA –ET2 ES ET1 EX1 ET0 EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

Symbol Position Function

EA IE.7 Disables all interrupts. If EA = 0,

no interrupt is acknowledged. If

EA = 1, each interrupt source is

individually enabled or disabled

by setting or clearing its enable

bit.

–IE.6 Reserved.

ET2 IE.5 Timer 2 interrupt enable bit

ES IE.4 Serial Port interrupt enable bit

ET1 IE.3 Timer 1 interrupt enable bit

EX1 IE.2 External interrupt 1 enable bit

ET0 IE.1 Timer 0 interrupt enable bit

EX0 IE.0 External interrupt 0 enable bit

User software should never write 1s to unimplemented bits,

because they may be used in future AT87 products.

IE1

IE0

TF1

TF0

INT1

INT0

TF2

EXF2

AT87F55WD

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier that can be configured for use as

an on-chip oscillator, as shown in Figure 11. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven, as shown in Figure 12.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is through a divide-by-two flip-flop, but minimum and maxi-

mum voltage high and low time specifications must be

observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware

reset, the device normally resumes program execution

from where it left off, up to two machine cycles before the

internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when idle mode is termi-

nated by a reset, the instruction following the one that

invokes idle mode should not write to a port pin or to exter-

nal memory.

Power-down Mode

In the Power-down mode, the oscillator is stopped, and the

instruction that invokes power-down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power-down mode is termi-

nated. Exit from power-down can be initiated either by a

hardware reset or by an enabled external interrupt. Reset

redefines the SFRs but does not change the on-chip RAM.

The reset should not be activated before VCC is restored to

its normal operating level and must be held active long

enough to allow the oscillator to restart and stabilize.

Figure 11. Oscillator Connections

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Figure 12. External Clock Drive Configuration

XTAL2

GND

XTAL1

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

Table 7. Status of External Pins During Idle and Power-down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data Data Data

AT87F55WD

Program Memory Lock Bits

The AT87F55WD has three lock bits that can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA pin

is sampled and latched during reset. If the device is pow-

ered up without a reset, the latch initializes to a random

value and holds that value until reset is activated. The

latched value of EA must agree with the current logic level

at that pin in order for the device to function properly.

Programming the QuickFlash

The AT87F55WD is shipped with the on-chip QuickFlash

memory array ready to be programmed. The programming

interface needs a high-voltage (12-volt) program enable

signal and is compatible with conventional third-party Flash

or EPROM programmers.

The AT87F55WD code memory array is programmed byte-

by-byte.

Programming Algorithm: Before programming the

AT87F55WD, the address, data, and control signals should

be set up according to the QuickFlash programming mode

table and Figure 13 and Figure 14. To program the

AT87F55WD, take the following steps:

1. Input the desired memory location on the address

lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V.

5. Pulse ALE/PROG once to program a byte in the

QuickFlash array or the lock bits. The byte-write

cycle is self-timed and typically takes no more than

50 µs. Repeat steps 1 through 5, changing the

address and data for the entire array or until the end

of the object file is reached.

Data Polling: The AT87F55WD features Data Polling to

indicate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of the written data on P0.7. Once the write cycle

has been completed, true data is valid on all outputs, and

the next cycle may begin. Data Polling may begin any time

after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can also

be monitored by the RDY/BSY output signal. P3.0 is pulled

low after ALE goes high during programming to indicate

BUSY. P3.0 is pulled high again when programming is

done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read back

via the address and data lines for verification. The lock bits

cannot be verified directly. Verification of the lock bits is

achieved by observing that their features are enabled.

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of

locations 000H, 100H, and 200H, except that P3.6 and

P3.7 must be pulled to a logic low. The values returned are

as follows.

(000H) = 1EH indicates manufactured by Atmel

(100H) = 87H indicates 87F family

(200H) = 05H indicates 87F55WD

Table 8. Lock Bit Protection Modes

Program Lock Bits

LB1 LB2 LB3 Protection Type

1 U U U No program lock features

2PUU

MOVC instructions executed

from external program

memory are disabled from

fetching code bytes from

internal memory, EA is

sampled and latched on reset,

and further programming of

the QuickFlash memory is

disabled.

3PPU

Same as mode 2, but verify is

also disabled

4PPP

Same as mode 3, but external

execution is also disabled

AT87F55WD

Programming Interface

Every code byte in the QuickFlash array can be pro-

grammed by using the appropriate combination of control

signals. The write operation cycle is self-timed and once

initiated, will automatically time itself to completion.

All major programming vendors offer worldwide support for

the Atmel microcontroller series. Please contact your local

programming vendor for the appropriate software revision.

Notes: 1. Each Prog pulse is 200 ns for Write Code Data and 100 µs for Write Lock Bits.

2. RDY/BSY signal is output on P3.0 during programming.

Figure 13. Programming the QuickFlash Memory Figure 14. Verifying the QuickFlash Memory

*Programming address line A14 (P3.4) is not the same as the external memory address line A14 (P2.6).

Table 9. QuickFlash Programming Modes

Mode VCC RST PSEN

ALE/

PROG

EA/

VPP P2.6 P2.7 P3.3 P3.6 P3.7

P0.7-0

Data

P3.4 P2.5-0 P1.7-0

Address

Write Code Data 5V H L 12V L HHHH D

IN A14 A13-8 A7-0

Read Code Data 5V H L H H/12V L L L H H DOUT A14 A13-8 A7-0

Write Lock Bit 16.5VH L 12VHHHHH X X X X

Write Lock Bit 2 6.5V H L 12V H H H L L X X X X

Write Lock Bit 3 6.5V H L 12V H L H H L X X X X

Read Lock Bits

1, 2, 3 5V H L H H H H L H L D2, 3, 4 X X X

Read Atmel ID 5V H L H H L L L L L 1EH X X 000H

Read Device ID 5V H L H H L L L L L 87H X X 100H

Read Device ID 5V H L H H L L L L L 05H X X 200H

P1.0-P1.7

P2.6

P3.6

P2.0 - P2.5

A0 - A7

ADDR.

0000H/4FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

3-33 MHz

A14*

+5V

P2.7

PGM

DATA

PROG

V/V

IH PP

VIH

ALE

P3.7

XTAL2 EA

RST

PSEN

XTAL1

GND

VCC

AT87F55WD

P3.4

P3.3

P3.0 RDY/

BSY

A8 - A13

P1.0-P1.7

P2.6

P3.6

P2.0 - P2.5

A0 - A7

ADDR.

0000H/4FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

3-33 MHz

+5V

P2.7

PGM DATA

(USE 10K

PULLUPS)

VIH

ALE

P3.7

XTAL 2 EA

RST

PSEN

XTAL1

GND

A14*

AT87F55WD

P3.4

P3.3

A8 - A13

AT87F55WD

QuickFlash Programming and Verification Characteristics

TA = 20°C to 30°C, VCC = 4.5V to 5.5V

Symbol Parameter Min Max Units

VPP Programming Supply Voltage 11.5 12.5 V

IPP Programming Supply Current 10 mA

ICC VCC Supply Current 30 mA

1/tCLCL Oscillator Frequency 3 33 MHz

tAVGL Address Setup to PROG Low 48tCLCL

tGHAX Address Hold After PROG 48tCLCL

tDVGL Data Setup to PROG Low 48tCLCL

tGHDX Data Hold After PROG 48tCLCL

tEHSH P2.7 (ENABLE) High to VPP 48tCLCL

tSHGL VPP Setup to PROG Low 10 µs

tGHSL VPP Hold After PROG 10 µs

tGLGH PROG Width 0.2 1 µs

tAVQV Address to Data Valid 48tCLCL

tELQV ENABLE Low to Data Valid 48tCLCL

tEHQZ Data Float After ENABLE 048t

CLCL

tGHBL PROG High to BUSY Low 1.0 µs

tWC Byte Write Cycle Time 80 µs

AT87F55WD

QuickFlash Programming and Verification Waveforms

tGLGH

tGHSL

tAVGL

tSHGL

tDVGL tGHAX

tAVQV

tGHDX

tEHSH tELQV

tWC

BUSY READY

tGHBL

tEHQZ

P1.0 - P1.7

P2.0 - P2.5

P3.4

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/V

VPP

P2.7

(ENABLE)

P3.0

(RDY/BSY)

PROGRAMMING

ADDRESS

VERIFICATION

ADDRESS

DATA I N DATA O U T

AT87F55WD

Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin: 10 mA

Maximum IOL per 8-bit port:

Port 0: 26 mA Ports 1, 2, 3: 15 mA

Maximum total IOL for all output pins: 71 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

2. Minimum VCC for Power-down is 2V.

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage ............................................ 6.6V

DC Output Current...................................................... 15.0 mA

DC Characteristics

The values shown in this table are valid for TA = -40°C to 85°C and VCC = 4.0V to 5.5V, unless otherwise noted.

Symbol Parameter Condition Min Max Units

VIL Input Low Voltage (Except EA)-0.50.2 V

CC-0.1 V

VIL1 Input Low Voltage (EA)-0.50.2 V

CC-0.3 V

VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V

VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V

VOL Output Low Voltage(1) (Ports 1,2,3) IOL = 1.6 mA 0.45 V

VOL1

Output Low Voltage(1)

(Port 0, ALE, PSEN)IOL = 3.2 mA 0.45 V

VOH

Output High Voltage

(Ports 1,2,3, ALE, PSEN)

IOH = -60 µA, VCC = 5V ± 10% 2.4 V

IOH = -25 µA 0.75 VCC V

IOH = -10 µA0.9 V

CC V

VOH1

Output High Voltage

(Port 0 in External Bus Mode)

IOH = -800 µA, VCC = 5V ± 10% 2.4 V

IOH = -300 µA 0.75 VCC V

IOH = -80 µA0.9 V

CC V

IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA

ITL

Logical 1 to 0 Transition Current

(Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA

ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA

RRST Reset Pulldown Resistor 50 300 KΩ

CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C10pF

ICC

Power Supply Current

Active Mode, 12 MHz 25 mA

Idle Mode, 12 MHz 6.5 mA

Power Down Mode(1) VCC = 5.5V 100 µA

AT87F55WD

AC Characteristics

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other

outputs = 80 pF.

External Program and Data Memory Characteristics

Symbol Parameter

12 MHz Oscillator Variable Oscillator

UnitsMin Max Min Max

1/tCLCL Oscillator Frequency 0 33 MHz

tLHLL ALE Pulse Width 127 2tCLCL-40 ns

tAVLL Address Valid to ALE Low 43 tCLCL-25 ns

tLLAX Address Hold After ALE Low 48 tCLCL-25 ns

tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns

tLLPL ALE Low to PSEN Low 43 tCLCL-25 ns

tPLPH PSEN Pulse Width 205 3tCLCL-45 ns

tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-60 ns

tPXIX Input Instruction Hold After PSEN 00ns

tPXIZ Input Instruction Float After PSEN 59 tCLCL-25 ns

tPXAV PSEN to Address Valid 75 tCLCL-8 ns

tAVIV Address to Valid Instruction In 312 5tCLCL-80 ns

tPLAZ PSEN Low to Address Float 10 10 ns

tRLRH RD Pulse Width 400 6tCLCL-100 ns

tWLWH WR Pulse Width 400 6tCLCL-100 ns

tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns

tRHDX Data Hold After RD 00ns

tRHDZ Data Float After RD 97 2tCLCL-28 ns

tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns

tAVDV Address to Valid Data In 585 9tCLCL-165 ns

tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns

tAVWL Address to RD or WR Low 203 4tCLCL-75 ns

tQVWX Data Valid to WR Transition 23 tCLCL-30 ns

tQVWH Data Valid to WR High 433 7tCLCL-130 ns

tWHQX Data Hold After WR 33 tCLCL-25 ns

tRLAZ RD Low to Address Float 0 0 ns

tWHLH RD or WR High to ALE High 43 123 tCLCL-25 tCLCL+25 ns

AT87F55WD

External Program Memory Read Cycle

External Data Memory Read Cycle

tLHLL

tLLIV

tPLIV

tLLAX

tPXIZ

tPLPH

tPLAZ

tPXAV

tAVLL tLLPL

tAVIV

tPXIX

ALE

PSEN

PORT 0

PORT 2

A8 - A15

A0 - A7 A0 - A7

A8 - A15

INSTR IN

tLHLL

tLLDV

tLLWL

tLLAX

tWHLH

tAVLL

tRLRH

tAVDV

tAVWL

tRLAZ tRHDX

tRLDV tRHDZ

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2

P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA IN INSTR IN

AT87F55WD

External Data Memory Write Cycle

External Clock Drive Waveforms

tLHLL

tLLWL

tLLAX

tWHLH

tAVLL

tWLWH

tAVWL

tQVWX tQVWH

tWHQX

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2

P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA OUT INSTR IN

tCHCX

tCLCX

tCLCL

tCHCL

tCLCH

V - 0.5V

0.45V

0.2 V - 0.1V

0.7 VCC

External Clock Drive

Symbol Parameter Min Max Units

1/tCLCL Oscillator Frequency 0 33 MHz

tCLCL Clock Period 30 ns

tCHCX High Time 12 ns

tCLCX Low Time 12 ns

tCLCH Rise Time 5 ns

tCHCL Fall Time 5 ns

AT87F55WD

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5V

for a logic 1 and 0.45V for a logic 0. Timing mea-

surements are made at VIH min. for a logic 1 and VIL

max. for a logic 0.

Float Waveforms(1)

Note: 1. For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when a 100 mV change from

the loaded VOH/VOL level occurs.

Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.

Symbol Parameter

12 MHz Osc Variable Oscillator

UnitsMin Max Min Max

tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs

tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns

tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-80 ns

tXHDX Input Data Hold After Clock Rising Edge 0 0 ns

tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

XHDV

QVXH

XLXL

XHDX

XHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

SET TI

SET RI

VALID VALIDVALID VALIDVALID VALIDVALID VALID

0.45V

TEST POINTS

V - 0.5V

CC 0.2 V + 0.9V

0.2 V - 0.1V

VLOAD+ 0.1V

Timing Reference

Points

LOAD - 0.1V

LOAD

VVOL+ 0.1V

VOL - 0.1V

AT87F55WD

Ordering Information

Speed

(MHz)

Power

Supply Ordering Code Package Operation Range

24 4.0V to 5.5V AT87F55WD-24AC

AT87F55WD-24JC

AT87F55WD-24PC

44A

44J

40P6

Commercial

(0°C to 70°C)

AT87F55WD-24AI

AT87F55WD-24JI

AT87F55WD-24PI

44A

44J

40P6

Industrial

(-40°C to 85°C)

33 4.5V to 5.5V AT87F55WD-33AC

AT87F55WD-33JC

AT87F55WD-33PC

44A

44J

40P6

Commercial

(0°C to 70°C)

Package Type

44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)

40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

= Preliminary Availability

AT87F55WD

Packaging Information

*Controlling dimension: millimeters

1.20(0.047) MAX

10.10(0.394)

9.90(0.386) SQ

12.21(0.478)

11.75(0.458) SQ

0.75(0.030)

0.45(0.018)

0.15(0.006)

0.05(0.002)

0.20(.008)

0.09(.003)

0.80(0.031) BSC

PIN 1 ID

0.45(0.018)

0.30(0.012)

.045(1.14) X 45°PIN NO. 1

IDENTIFY

.045(1.14) X 30° - 45°.012(.305)

.008(.203)

.021(.533)

.013(.330)

.630(16.0)

.590(15.0)

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.500(12.7) REF SQ

.032(.813)

.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)

.650(16.5)

.695(17.7)

.685(17.4)SQ

2.07(52.6)

2.04(51.8) PIN

.566(14.4)

.530(13.5)

.090(2.29)

MAX

.005(.127)

MIN

.065(1.65)

.015(.381)

.022(.559)

.014(.356)

.065(1.65)

.041(1.04)

15 REF

.690(17.5)

.610(15.5)

.630(16.0)

.590(15.0)

.012(.305)

.008(.203)

.110(2.79)

.090(2.29)

.161(4.09)

.125(3.18)

SEATING

PLANE

.220(5.59)

MAX

1.900(48.26) REF

44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flat Package (TQFP)

Dimensions in Millimeters and (Inches)*

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

40P6, 40-pin, 0.600" Wide, Plastic Dual Inline

Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-011 AC

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

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