PI74ALVCH162268 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs Product Features Product Description * PI74ALVCH162268 is designed for low voltage operation VCC = 2.3V to 3.6V * Hysteresis on all inputs * Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25C * Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25C * B-port outputs have equivalent 26 series resistors, no external resistors are required. * Bus Hold retains last active bus state during 3-state eliminates the need for external pullup resistors * Industrial operation at 40C to +85C * Packages available: 56-pin 240 mil wide plastic TSSOP (A56) 56-pin 300 mil wide plastic SSOP (V56) Pericom Semiconductors PI74ALVCH series of logic circuits are produced in the Companys advanced 0.5 micron CMOS technology, achieving industry leading speed. This 12-bit to 24-bit registered bus exchanger is designed for 2.3V to 3.6V Vcc operation. The PI74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA, OEB). These control terminals are registered so bus direction changes are synchronous with CLK. Logic Block Diagram The B outputs, which are designed to sink up to 12mA, include equivalent 26 resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE should be tied to VCC through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. Because OE is being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 1 PS8352 04/05/01 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Name OE CLK SEL CLKEN A,1B,2B GND VCC Product Pin Configuration Description Output Enable Input (Active LOW) Clock Select (Active Low) Clock Enable (Active Low) 3-State Outputs Ground Power 1 2 2B3 3 4 GND Truth Tables(1) Output Enable INPUTS OEA CLKEN1B A2 9 48 A3 10 47 2B8 2B9 46 GND 45 44 2B10 43 42 41 2B12 40 39 1B10 38 37 1B9 36 1B7 VCC 11 56-Pin A, V 12 A5 13 1B,2B A6 14 15 H H Z Z A7 A8 16 H L Z Active A9 GND 17 A10 19 A11 20 21 L L Z Active A12 Active VCC 1B1 1B2 A to B STORAGE (OEB = L) INPUTS CLKENA1 CLKENA2 OUTPUTS CLK A 1B GND 2B (3) H H X X 1B0 2B0 L L L L(2) X (2) X L L H X L L X L X L H X H H 1B3 CLKEN2B (3) 2B5 7 8 A Active 53 52 A1 6 OEB H 2B4 GND VCC OEA L 54 CLKENA2 5 CLK OEB 2B2 2B1 GND A4 OUTPUTS 56 55 SEL 18 51 50 49 2B6 VCC 2B7 2B11 1B12 1B11 GND 1B8 22 23 24 35 34 33 25 26 32 31 GND 27 28 30 29 CLKENA1 CLK 1B6 1B5 1B4 B to A STORAGE (OEA = L) INPUTS CLKEN1B CLKEN2B CLK SEL 1B 2B Outputs A H X X H X X A0(3) X H X L X X A0(3) L X H L X L L X H H X H X L L X L L X L L X H H Notes: 1. H = High Signal Level, L = Low Signal Level X = Irrelevant, Z = High Impedance = Transition, Low to High 2. Two CLK edges are needed to propagate data 3. Output level before the indicated steady state input conditions were established. 2 PS8352 04/05/01 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................. 65C to +150C Supply Voltage Range, VCC ........................................... 0.5V to 4.6V Input Voltage Range,VI : Except I/O ports (See Note 1): ........................................ 0.5V to 4.6V I/O ports (See Notes 1 and 2) .............................. 0.5V to VCC + 0.5V Output Voltage Range, VO (See Notes 1and 2) .. 0.5V to VCC + 0.5V Input Clamp current, IIK (VI < 0) .............................................. 50mA Output Clamp current, IOK (VO < 0 or VO > VCC) ................... 50mA Continous Output Current, IO (VO = 0 to VCC) ........................ 50mA Continous Current through each VCC or GND ........................ 100mA Maximum Power Dissipation: A package ................................................................... 1W V package ................................................................ 1.4W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = 40C to +85C, VCC = 3.3V 10%) Parame te rs De s cription Te s t Conditions (3) M in. M ax. VCC Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage VIN Input Voltage 0 VCC VOUT Output Voltage 0 VCC IOH IOL IOH IOL HIGH- level Output Current (A Port) LOW- level Output Current (A Port) HIGH- level Output Current (B Port) LOW- level Output Current (B Port) 2.3 Typ. VCC = 2.3V to 2.7V 1.7 VCC = 2.7V to 3.6V 2.0 Units 3.6 VCC = 2.3V to 2.7V 0.7 VCC = 2.7V to 3.6V 0.8 VCC = 2.3V - 12 VCC = 2.7V - 12 VCC = 3.0V - 24 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 VCC = 2.3V -6 VCC = 2.7V -8 VCC = 3.0V - 12 VCC = 2.3V 6 VCC = 2.7V 8 VCC = 3.0V 12 V mA Notes: 1. The input and output negative-voltage ratings maybe exceeded if the input and outputclamp-current ratings are observed. 2. This value is limited to 4.6V maximum. 3. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 PS8352 04/05/01 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics-Continued (Over the Operating Range, TA = -40C to +85C, VCC = 3.3V 10% Parame te rs VCC(1) M in. Min. toMax. VCC - 0.2 VIH = 1.7V 2.3V 2.0 VIH = 1.7V 2.3V 1.7 VIH = 2.0V 2.7V 2.2 VIH = 2.0V 3.0V 2.4 VIH = 2.0V 3.0V 2.0 Te s t Conditions IOH = - 100 IOH = - 6m VOH (A Port) IOH = - 12m IOH = - 24m IOH = - 100 Min. to Max. VCC - 0.2 VIH = 1.7V 2.3V 1.9 VIH = 1.7V 2.3V 1.7 VIH = 2.0V 3.0V 2.4 IOH = - 8m VIH = 2.0V 2.7V 2.0 IOH = - 12m VIH = 2.0V 3.0V 2.0 IOH = - 4m VOH (B Port) IOH = - 6m IOL = 100 IOL = 6m VOL(A Port) IOL = 12m IOL = 24m VOL(B Port) II VIL = 0.7V 2.3V 0.4 VIL = 0.7V 2.3V 0.7 VIL = 0.8V 2.7V 0.4 VIL = 0.8V 3.0V 0.55 Min. to Max. 0.2 VIL = 0.7V 2.3V 0.4 VIL = 0.7V 2.3V 0.55 VIL = 0.8V 3.0V 0.55 IOL = 8m VIL = 0.8V 2.7V 0.6 IOL = 12m VIL = 0.8V 3.0V 0.8 IOL = 6m VI = VCC or GND 3.6V 2.3V VI = 1.7V VI = 0.8V 3.0V VI = 2.0V IOZ(4) ICC CC CI Control Inputs CIO A or B Ports 5 45 - 45 75 - 75 VI = 0 to 3.6V(3) 3.6V 500 VO = VCC or GND VI = VCC or GND, IO = 0 3.6V 10 3.6V 40 3V to 3.6V 750 One input at VCC - 0.6V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND Units V 0.2 VI = 0.7V II (Hold) M ax. Min. to Max. IOL= 100 IOL = 4m Typ.(2) 3.3V 3.5 3.3V 9 pF Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient and maximum loading. 3. Bus hold maximum dynamic current required to switch the input from one state to another 4. For I/O ports, the IOZ includes the input leakage current. 4 PS8352 04/05/01 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements over Operating Range Parame te rs fCLOCK tW tSU VCC= 2.5 V 0.2 V De s cription M ax. M in. M ax. M in. M ax. 0 120 0 125 0 150 Pulse duration, CLK high or Low 3.3 3.3 3.3 A data before CLK 4.5 4 3.4 B data before CLK 0.8 1.2 1 SEL before CLK 1.4 1.6 1.3 CLK ENA1 or CLKENA2 before CLK 3.6 3.4 2.8 CLK ENB1 or CLK ENB2 before CLK 3.2 3 2.5 O E before CLK 4.2 3.9 3.2 A data after CLK 0 0 0.2 B data after CLK 1.3 1.2 1.3 1 1 1 CLKENA1 or CLK ENA2 after CLK 0.1 0.1 0.4 CLK ENB1 or CLK ENB2 after CLK 0.1 0 0.5 0 0 0.2 SEL after CLK tH Hold time O E after CLK t/v(1) VCC= 3.3 V 0.3 V M in. Clock frequency Setup time VCC= 2.7 V Input Transition Rise or Fall 0 10 0 10 0 Units Mhz ns ns ns 10 ns/V Notes: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. Switching Characteristics over Operating Range(1) Parame te rs From (INPUT) To (OUTPUT) fMAX VCC = 2.5V 0.2V M in.(2) M ax. VCC = 2.7V M in.(2) 120 M ax. VCC = 3.3V 0.3V M in.(2) 125 M ax.(2) 150 MHz tPD B 1.6 6.1 5.9 1.8 5.4 tPD A (1B) 1.6 5.8 5.4 1.7 4.8 tPD B (2B) 1.6 5.8 5.3 1.8 4.8 A (SEL) 2.5 7.3 6.5 2.4 5.8 B 2.7 7.2 6.8 2.6 6.1 tDIS B 2.8 7.2 6.1 2.5 5.9 tEN A 2 6.2 5.6 1.8 5.1 tDIS A 2 6.5 5.4 2.1 5 tPD tEN CLK Units ns Notes: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 5 PS8352 04/05/01 PI74ALVCH162268 12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Operating Characteristics, TA= 25C Parame te r Te s t Conditions Vcc = 2.5V 0.2V Vcc = 3.3V 0.3V Typical Typical CPD Power Dissipation Outputs Enabled Capacitance Outputs Disabled CL= 50pF, F = 10 MHz 87 120 80.5 118 Units pF Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 6 PS8352 04/05/01