1
PS8689G 01/17/06
Description
PI6CU877 is a PLL clock driver family, consisting of PI6CU877,
and PI6CUA877, developed for Registered DDR2 DIMM
applications with 1.8V operation and differential clock input and
output levels.
The device is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to eleven differential pairs of clock
outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT,
FBOUT).
The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the
LVCMOS inputs (OE, OS) and the Analog Power input (AV
DD
).
When OE is LOW the outputs except FBOUT, FBOUT, are disabled
while the internal PLL continues to maintain its locked-in frequency.
OS is a pin that must be tied to GND or V
DD.
When OS is high, OE
will function as described above. When OS is LOW, OE has no
effect on Y7/Y7, they are free running. When AV
DD
is grounded,
the PLL is turned off and bypassed for test purposes.
When CLK/CLK are logic low, the device will enter a low power
mode. An input logic detection circuit will detect the logic low level
and perform a low power state where all Y[0:9], Y[0:9]; FBOUT,
FBOUT, and PLL are OFF.
PI6CUx877 is a high-performance, low skew, and low jitter PLL
clock driver, and it is also able to track Spread Spectrum Clocking
(SSC) for reduced EMI.
Features
•
PLL clock distribution optimized for DDR2-667/533/400
SDRAM applications.
•
Distributes one differential clock input pair to eleven differ-
ential clock output pairs.
•
Differential Inputs (CLK, CLK) and (FBIN, FBIN)
•
Input OE/OS: LVCMOS
•
Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT)
•
External feedback pins (FBIN, FBIN) are used to
synchronize the outputs to the clock input.
•
Operates at AV
DD
= 1.8V for core circuit and internal PLL,
and V
DDQ
= 1.8V for differential output drivers
•
Packaging (Pb-free & Green):
– 52-ball VFBGA (NF)
•
PI6CU877 for DDR2-533/400 applications
•
PI6CUA877 for DDR2-667/533/400 applications
Pin Con guration
PI6CU877
PI6CUA877
PI6CUA877
PLL Clock Driver for
1.8V DDR2 Mem o ry
1
2
3
4
5
6
A
Y
1
Y
0
Y
0
Y
5
Y
5
Y
6
B
Y
1
GND
GND
GND
GND
Y
6
C
Y
2
GND
NB
NB
GND
Y
7
D
Y
2
V
DDQ
V
DDQ
V
DDQ
OS
Y
7
E
CK
V
DDQ
NB
NB
V
DDQ
FB
IN
F
CK
V
DDQ
NB
NB
OE
FB
IN
G
AGND
V
DDQ
V
DDQ
V
DDQ
V
DDQ
FB
OUT
H
AV
DD
GND
NB
NB
GND
FB
OUT
J
Y
3
GND
GND
GND
GND
Y
8
k
Y
3
Y
4
Y
4
Y
9
Y
9
Y
8
08-0298
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
Block Diagram
Y0
Y0
Y1
AVDD
OS
OE Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
PLL
CK
CK
FBIN
FBIN
10K - 100kΩ
LD* or OE
LD*, OS or OE
PLL bypass
* The Logic Detect (LD) powers down the device
when a logic low is applied to both CK and CK.
Powerdown
Control &
Test Logic
LD*
08-0298
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
Function Table
Inputs
Outputs
PLL State
AV
DD
OE
OS
CK
CK
Y
Y
FBOUT
FBOUT
GND
H
X
L
H
L
H
L
H
Bypass/Off
GND
H
X
H
L
H
L
H
L
Bypass/Off
GND
L
H
L
H
L(Z)
(1)
L(Z)
(1)
L
H
Bypass/Off
GND
L
L
H
L
L(Z)
(1)
,
Y7 active
L(Z)
(1)
,
Y7 active
H
L
Bypass/Off
Nom. V
DD
L
H
L
H
L(Z)
(1)
L(Z)
(1)
L
H
On
Nom. V
DD
L
L
H
L
L(Z)
(1)
,
Y7 active
L(Z)
(1)
,
Y7 active
H
L
On
Nom. V
DD
H
X
L
H
L
H
L
H
On
Nom. V
DD
H
X
H
L
H
L
H
L
On
Nom. V
DD
X
X
L
L
L(Z)
(1)
L(Z)
(1)
L(Z)
(1)
L(Z)
(1)
Off
Nom. V
DD
X
X
H
H
Reserved
Notes:
1.
L
(Z)
means the outputs are disabled to a low state meeting the I
ODL
limit on DC Speci cation
ODL limit on DC Speci cation
ODL
Pinout Table
Pin Name
Characteristics
Description
AGND
Ground
Analog ground
AV
DD
1.8V nominal
Analog power
CK
Differential Input
Clock input with a (10k - 100kΩ) pulldown resistor
CK
Differential Input
Complementary clock input with a (10k - 100kΩ) pulldown resistor
FB
IN
Differential Input
Feedback clock input
FB
IN
Differential Input
Complementary feedback clock input
FB
OUT
Differential Output
Feedback clock output
FB
OUT
Differential Output
Complementary feedback clock output
OE
LVCMOS input
Output enable (async.)
OS
LVCMOS input
Output select (tied to GND or V
DDQ
)
GND
Ground
Ground
V
DDQ
1.8V nominal
Logic and output power
Y[0:9]
Differential Outputs
Clock outputs
Y[0:9]
Differential Outputs
Complementary clock outputs
NB
No Ball
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
DC Speci cations
Recommended Operating Con di tions
Symbol
Parameter
Min.
Nom.
Max.
Units
V
DDQ
Output Supply Voltage
1.7
1.8
1.9
V
AV
DD
Supply voltage
(1)
V
DDQ
V
IL
Low-level input voltage
(2)
OE, OS, CK, CK
0.35 x
V
DDQ
V
IH
High-level input voltage
(2)
OE, OS, CK, CK
0.65 x
V
DDQ
I
OH
High-level output current, see Fig 2
-9
mA
I
OL
Low-level output current, see Fig. 2
9
V
IX
Input differential-pair crossing voltage
(V
DDQ
/2)
-0.15
(V
DDQ
/2)
-0.15
V
IN
Input voltage level
-0.3
V
DDQ
+0.3
V
V
ID
Input differential voltage, See Fig 9
(2)
DC
0.3
V
DDQ
+0.4
AC
0.6
V
DDQ
+0.4
T
A
TA
T
Operating free air temperature
0
70
ºC
Notes
:
1.
The PLL is turned off and bypassed for test purposes when AV
DD
is grounded. During this test mode, V
DDQ
remains within the recommended
operating conditions and no timing parameters are guaranteed.
2.
V
ID
is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for de nition. The CK and CK,
V
IH
and V
IL
limits are used to de ne the DC low and high levels for the logic detect state.
IL limits are used to de ne the DC low and high levels for the logic detect state.
IL
Absolute Maximum Ratings
(Over operating free-air temperature range)
Symbol
Parameter
Min.
Max.
Units
V
DDQ
, A
VDD
, A
VDD
, A
I/O supply voltage range and analog /core supply voltage range
-0.5
2.5
V
V
I
Input voltage range
-0.5
V
DDQ
+0.5
V
O
Output voltage range
-0.5
V
DDQ
+0.5
I
IK
Input clamp current
-50
50
mA
I
OK
Output clamp current
-50
50
I
O
Continuous output current, V
O
= 0 to V
DDQ
-50
50
I
O(PWR)
Continuous current through each V
DDQ
or GND
-100
100
T
STG
Storage temperature
-65
150
ºC
Note
:
1.
Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
08-0298
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
Timing Requirements
(Over recomended operating free-air temperature)
Symbol
Description
AV
DD
, V
DDQ
= 1.8V ±0.1V1
Units
Min
Max
t
DC
Input clock duty cycle
40
60
%
t
L
Stabilization time
(1)
15
µs
1.
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power
up . During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and
CK maybe left oating after they have been driven low for one complete clock cycle.
CK maybe left oating after they have been driven low for one complete clock cycle.
FCK Clock Frequency Speci cations
(AV
DD
, V
DDQ
= 1.8 ±0.1V)
PI6CUx877
Part Number
Operating Clock Frequency
(1,2)
Application Clock Frequency
(1,3)
Units
Min
Max
Min
Max
PI6CU877
125
300
160
270
MHz
PI6CUA877
125
410
160
360
MHz
Notes:
1.
The PLL is able to handle spread spectrum induced skew.
2.
Operating clock frequency indicates a range over which the PLL is able to lock, but in which it is not required to meet the other timing parameters.
(Used for low-speed debug or production testing of DIMM modules).
3.
Application clock frequency indicates a range over which the PLL must meet all timing parameters.
08-0298
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
DC Speci cations
Param-
eter
Description
Test Condition
AV
DD
,
V
DDQ
Min.
Typ.
Max.
Units
V
IK
All Inputs
I
I
= -18mA
1.7V
1.2
V
V
OH
HIGH output voltage
I
OH
= -100µA
1.7 to
1.9V
V
DDQ
-0.2
I
OH
= -9mA
1.7
1.1
I
ODL
Output disabled low current
OE = L, V
ODL
= 100mV
ODL = 100mV
ODL
1.7V
100
µA
V
OD
Output differential voltage, the magnitude of the difference
between the true and complimentary outputs, see g. 9 for
more details
0.6
V
I
I
CK, CK
V
I
= V
DDQ
or GND
1.9V
±250
µA
OE, OS, FB
IN
, FB
IN
V
I
= V
DDQ
or GND
±10
I
DDLD
Static Supple current, I
DDQ
+ I
ADD
CK and CK = L
500
I
DD
Dynamic supply current, I
DDQ
+
I
ADD
, see note 6 for CPD calcula-
tion
CK and CK = 360MHz,
all outputs are open (not
connected to a PCB)
300
mA
CI
CK, CK
V
I
= V
DDQ
or GND
1.8V
2
3
pF
FB
IN
, FB
IN
V
I
= V
DDQ
or GND
2
3
CI(∆)
CK, CK
V
I
= V
DDQ
or GND
0.25
FB
IN
, FB
IN
V
I
= V
DDQ
or GND
0.25
Notes
:
6.
Total I
DD
= I
DDQ +
I
ADD
= F
CK
*C
CK *C
CK
PD
*V
DDQ
, solving for C
PD
= (I
DDQ
+ I
ADD
)/(F
CK
*V
DDQ
) where F
CK
is the input fre quen cy, V
CK is the input fre quen cy, V
CK
DDQ
is the
power supply and C
PD
is the Power Dissipation Capacitance.
08-0298
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
AC Speci cations
Switching char ac ter is tics over rec om mend ed operating free-air temperature range (unless oth er wise noted)
(15)
Parameter
Description
Diagram
AV
DD
, V
DDQ
= 1.8 ±0.1V
Units
Min.
Nom.
Max.
ten
OE to and Y/Y
see Fig 11
8
ns
tdis
OE to and Y/Y
see Fig 11
8
tjit(cc+)
Cycle-to-cycle jitter
see Fig 4
0
40
ps
tjit(cc-)
0
-40
t(Ø)
Static phase offset
(11)
see Fig 5
-50
50
t(Ø)dyn
Dynamic phase offset
see Fig 10
-50
50
tsk(o)
Output clock skew
see Fig 6
40
tjit(per)
Period jitter
(12)
see Fig 7
-40
40
tjit(hper)
Half period jitter
(12)
160 to 270 MHz
see Fig 8
-75
75
Half period jitter
(12)
271 to 360 MHz
see Fig 8
-50
50
slr(i)
Input clock slew rate
see Fig 9
1
2.5
4
V/ns
Output enable (OE)
see Fig 9
0.5
slr(o)
Output clock slew rate
(14, 16)
see Fig 1, 9
1.5
2.5
3
V
OX
Outpu differential-pair cross voltage
(13)
see Fig 2
(V
DDQ
/2)
-0.1
(V
DDQ
/2)
+0.1
V
The PLL on the PI6CUx877 is capable of meeting all the above test parameters while supporting SSC synthesirers
with the following parameters:
SSC modulation frequency
30.00
33
kHz
SSC clock input frequency deviation
0.00
-0.50
%
PI6CUx877 PLL design should target the values below to minimize the SCC induced skew:
PLL Loop Bandwidth
2.0
MHz
Notes:
11.
Static Phase Offset does not include Jitter
12.
Period Jitter and Half-Period Jitter speci cations are separate speci cations that must be met independently of each other.
13.
VOX speci ed at the DRAM clock input or the test load.
14.
To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these
nominal values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered
DDR2 DIMM application.
15.
There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differen-
tial-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For con sis ten cy, equal length cables should be used.
16.
The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended.
08-0298
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
Figure 2. Output Load Test Circuit 1
Figure 1. IBIS Model Output Load
GND
VDD
Z = 120Ω
Z= 60Ω
Z= 60ΩVTT
R = 1MΩ
C= 1pF
SCOPE
L= 2.97"
L= 2.97"
GND
GND
C = 10pF
C = 10pF
VTT
R = 1MΩ
C= 1pF
Note : VTT = GND
PI6CxU877
Figure 3. Output Load Test Circuit 2
–VDD/2
VDD/2
–VDD/2
–VDD/2
C = 10pF
R = 10Ω
R = 10Ω
Z= 60Ω
Z= 60ΩZ= 50Ω
Z= 50Ω
C = 10pF VTT
R = 50Ω
R = 50Ω
SCOPE
L= 2.97"
L= 2.97"
VTT
Note: V
TT
= GND
PI6CUx877
VDD
PI6CUx877
GND
VCK
VCK
VDD/2
R = 60Ω
R = 60Ω
08-0298
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
Figure 4. Cycle-to-Cycle Jitter
Figure 5. Static Phase Off set
Figure 6. Output Skew
∑
t
sk (o)
08-0298
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
Figure 7. Period Jitter
(fo = average input frequency measured at CK/CK)
Figure 8. Half-Period Jitter
Figure 9. Input and Output Slew Rates
08-0298
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
Figure 10. Dynamic Phase Offset
Figure 11. Time Delay Between Output Enable (OE) and Clock Output (Y, Y)
OE
Y/Y
Y
Y
50% VDD
50% VDD
t
dis
50% VDD
50% VDD
t
en
OE
Y
Y
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PS8689G 01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
Packaging Mechanical: 52-Ball VFBGA (NF)
Ordering Information
(1,2)
Ordering Code
Package Code
Package Description
PI6CU877NFE
NF
Pb-free & Green, 52-ball VFBGA
PI6CUA877NFE
NF
Pb-free & Green, 52-ball VFBGA
Notes:
1.
Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/
2.
E = Pb-free and Green
Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com
08-0298
