SGN02G64D2BD1SA-DCWRT - Swissbit

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

Industriestrasse 4 Fon: +41 71 913 03 03 www.swissbit.com Page 1

CH – 9552 Bronschhofen Fax: +41 71 913 03 15 eMail: info@swissbit.com of 17

Switzerland

2048MB DDR3 – SDRAM SO-DIMM

204 Pin SO-DIMM

SGN02G64D2BD1SA-xxRT

2GByte in FBGA Technology

RoHS compliant

*) The refresh rate has to be doubled when 85°C<TC<95°C

Environmental Requirements:

 Operating temperature (ambient)

Standard Grade 0°C to 70°C

E-Grade 0°C to 85°C

W-Grade -40°C to 85°C

 Operating Humidity

10% to 90% relative humidity, noncondensing

 Operating Pressure

105 to 69 kPa (up to 10000 ft.)

 Storage Temperature

-55°C to 100°C

 Storage Humidity

5% to 95% relative humidity, noncondensing

 Storage Pressure

1682 PSI (up to 5000 ft.) at 50°C

Options:

 Data Rate / Latency Marking

DDR3 1066 MT/s CL7 -BB

DDR3 1333 MT/s CL9 -CC

DDR3 1600 MT/s CL11 -DC

 Module density

2048MB with 8 dies and 1 rank

 Standard Grade (TA) 0°C to 70°C

(TC) 0°C to 85°C

Grade E (TA) 0°C to 85°C

(TC) 0°C to 95°C *)

Grade W (TA) -40°C to 85°C

(TC) -40°C to 95°C *)

Figure: mechanical dimensions1

1if no tolerances specified ± 0.15mm

Features:

 204-pin 64-bit DDR3 Small Outline Dual-In-Line Double

Data Rate Synchronous DRAM module

 Module organization: single rank 256M x 64

 VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V

 1.5V I/O ( SSTL_15 compatible)

 Fly-by-bus with termination for C/A & CLK bus

 On-board I2C temperature sensor with integrated serial

presence-detect (SPD) EEPROM

 Gold-contact pads

 This module is fully pin and functional compatible to the

JEDEC PC3-12800 spec. and JEDEC- Standard MO-268.

(see www.jedec.org)

 The pcb and all components are manufactured according

to the RoHS compliance specification [EU Directive

2002/95/EC Restriction of Hazardous Substances (RoHS)]

 DDR3 - SDRAM component Samsung K4B2G0846D

 256Mx8 DDR3 SDRAM in PG-TFBGA-78 package

 8-bit prefetch architecture

 Programmable CAS Latency, CAS Write Latency, Additive

Latency, Burst Length and Burst Type.

 On-Die-Termination (ODT) and Dynamic ODT for improved

signal integrity.

 Refresh. Self Refresh and Power Down Modes.

 ZQ Calibration for output driver and ODT.

 System Level Timing Calibration Support via Write Leveling

and Multi Purpose Register (MPR) Read Pattern.

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

Industriestrasse 4 Fon: +41 71 913 03 03 www.swissbit.com Page 2

CH – 9552 Bronschhofen Fax: +41 71 913 03 15 eMail: info@swissbit.com of 17

Switzerland

This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM Small Outline Dual-In-line Memory

Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally

configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-

speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE

accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a

programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An

auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst

access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is

providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All

inputs and all full drive-strength outputs are SSTL_15 compatible.

The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM

using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are

utilized by the SO-DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and

several timing parameters. The second 128 bytes are available to the end user.

Module Configuration

Organization

DDR3 SDRAMs used

Row

Addr.

Device Bank

Addr.

Column

Addr.

Refresh

Module

Bank Select

256M x 64bit

8 x 256M x 8bit (2048Mbit)

15

BA0, BA1, BA2

10

8k

S0#

Module Dimensions

in mm

67.60 (long) x 30(high) x 3.80 [max] (thickness)

Timing Parameters

Part Number

Module Density

Transfer Rate

Clock Cycle/Data bit rate

Latency

SGN02G64D2BD1SA-BB[E/W]RT

2048 MB

8.5 GB/s

1.87ns / 1066MT/s

7-7-7

SGN02G64D2BD1SA-CC[E/W]RT

2048 MB

10.6 GB/s

1.5ns / 1333MT/s

9-9-9

SGN02G64D2BD1SA-DC[E/W]RT

2048 MB

12.8 GB/s

1.25ns / 1600MT/s

11-11-11

Pin Name

A0-9, A11 – A14

Address Inputs

A10/AP

Address Input / Autoprecharge Bit

BA0 – BA2

Bank Address Inputs

DQ0 – DQ63

Data Input / Output

DM0-DM7

Input Data Mask

DQS0 - DQS7

Data Strobe, positive line

DQS0# - DQS7#

Data Strobe, negative line (only used when differential data strobe mode is enabled)

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

CKE0

Clock Enable

S0#

Chip Select

CK0

Clock Inputs, positive line

CK0#

Clock Inputs, negative line

Event#

Temperature event: The EVENT# pin is asserted by the temperature sensor when critical

Figure 1: Mechanical Dimensions

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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Switzerland

VDD

Supply Voltage (1.5V± 0.075V)

VREFDQ

Reference voltage: DQ, DM (VDD/2)

VREFCA

Reference voltage: Control, command, and address (VDD/2)

VSS

Ground

VTT

Termination voltage: Used for control, command, and address (VDD/2).

VDDSPD

Serial EEPROM Positive Power Supply

SCL

Serial Clock for Presence Detect

SDA

Serial Data Out for Presence Detect

SA0 – SA1

Presence Detect Address Inputs

ODT0

On-Die Termination

NC

No Connection

Pin Configuration

Frontside

PIN#

Symbol

PIN#

Symbol

PIN#

Symbol

PIN#

Symbol

1

VREFDQ

53

DQ19

103

CK0#

155

VSS

3

VSS

55

VSS

105

VDD

157

DQ42

5

DQ0

57

DQ24

107

A10/AP

159

DQ43

7

DQ1

59

DQ25

109

BA0

161

VSS

9

VSS

61

VSS

111

VDD

163

DQ48

11

DM0

63

DM3

113

WE#

165

DQ49

13

VSS

65

VSS

115

CAS#

167

VSS

15

DQ2

67

DQ26

117

VDD

169

DQS6#

17

DQ3

69

DQ27

119

A13

171

DQS6

19

VSS

71

VSS

121

NC (S1#)

173

VSS

21

DQ8

KEY

123

VDD

175

DQ50

23

DQ9

73

CKE0

125

NC (TEST)

177

DQ51

25

VSS

75

VDD

127

VSS

179

VSS

27

DQS1#

77

NC

129

DQ32

181

DQ56

29

DQS1

79

BA2

131

DQ33

183

DQ57

31

VSS

81

VDD

133

VSS

185

VSS

33

DQ10

83

A12/BC#

135

DQS4#

187

DM7

35

DQ11

85

A9

137

DQS4

189

VSS

37

VSS

87

VDD

139

VSS

191

DQ58

39

DQ16

89

A8

141

DQ34

193

DQ59

41

DQ17

91

A5

143

DQ35

195

VSS

43

VSS

93

VDD

145

VSS

197

SA0

45

DQS2#

95

A3

147

DQ40

199

VDDSPD

47

DQS2

97

A1

149

DQ41

201

SA1

49

VSS

99

VDD

151

VSS

203

VTT

51

DQ18

101

CK0

153

DM5

(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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Backside

PIN#

Symbol

PIN#

Symbol

PIN#

Symbol

PIN#

Symbol

2

VSS

54

VSS

104

NC (CK1#)

156

VSS

4

DQ4

56

DQ28

106

VDD

158

DQ46

6

DQ5

58

DQ29

108

BA1

160

DQ47

8

VSS

60

VSS

110

RAS#

162

VSS

10

DQS0#

62

DQS3#

112

VDD

164

DQ52

12

DQS0

64

DQS3

114

S0#

166

DQ53

14

VSS

66

VSS

116

ODT0

168

VSS

16

DQ6

68

DQ30

118

VDD

170

DM6

18

DQ7

70

DQ31

120

NC (ODT1)

172

VSS

20

VSS

72

VSS

122

NC

174

DQ54

22

DQ12

KEY

124

VDD

176

DQ55

24

DQ13

74

NC (CKE1)

126

VREFCA

178

VSS

26

VSS

76

VDD

128

VSS

180

DQ60

28

DM1

78

NC (A15)

130

DQ36

182

DQ61

30

NC (RESET#)

80

A14

132

DQ37

184

VSS

32

VSS

82

VDD

134

VSS

186

DQS7#

34

DQ14

84

A11

136

DM4

188

DQS7

36

DQ15

86

A7

138

VSS

190

VSS

38

VSS

88

VDD

140

DQ38

192

DQ62

40

DQ20

90

A6

142

DQ39

194

DQ63

42

DQ21

92

A4

144

VSS

196

VSS

44

VSS

94

VDD

146

DQ44

198

EVENT#

46

DM2

96

A2

148

DQ45

200

SDA

48

VSS

98

A0

150

VSS

202

SCL

50

DQ22

100

VDD

152

DQS5#

204

VTT

52

DQ23

102

NC (CK1)

154

DQS5

(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR3 SDRAM SODIMM,

1 RANK AND 8 COMPONENTS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D0

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D1

DQSCS

DQ0

DQ1

DQ2

DQ3

DQ5

DQ4

DQ6

DQ7

S0

DQS0

DM0

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ13

DQ12

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D2

DQSCS

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ21

DQ20

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D3

DQSCS

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D4

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D5

DQSCS

DQ32

DQ33

DQ34

DQ35

DQ37

DQ36

DQ38

DQ39

DQS4

DM4

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ45

DQ44

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D6

DQSCS

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ53

DQ52

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D7

DQSCS

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ61

DQ60

DQ62

DQ63

VDDSPD SPD

VDD/VDDQ D0-D7

VREFDQ

VREFCA

D0-D7

VSS

BA0-BA2 BA0-BA2: SDRAM D0-D7

A0-A14 A0-A14: SDRAM D0-D7

RAS RAS: SDRAM D0-D7

CAS CAS: SDRAM D0-D7

WE WE: SDRAM D0-D7

ODT0 ODT: SDRAM D0-D7

CKE0 CKE: SDRAM D0-D7

CK0 CK: SDRAM D0-D7

RESET RESET: SDRAM D0-D7

Notes:

1. DQ-to-I/O wiring is shown as recommended but may

be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be

maintained as shown.

3. DQ, DM, DQS/DQS resistors: Refer to associated

topology diagram.

4. Refer to the appropriate clock wiring topology under

the DIMM wiring details section of the JEDED document.

5. For each DRAM, a unique ZQ resistor is connected to

GND. The ZQ resistor is 240Ω±1%.

6. Refer to associated figure for SPD details.

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

Industriestrasse 4 Fon: +41 71 913 03 03 www.swissbit.com Page 6

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MAXIMUM ELECTRICAL DC CHARACTERISTICS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Supply Voltage

VDD

-0.4

1.975

V

I/O Supply Voltage

VDDQ

-0.4

1.975

V

VDDL Supply Voltage

VDDL

-0.4

1.975

V

Voltage on any pin relative to VSS

VIN, VOUT

-0.4

1.975

V

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V

(All other pins not under test = 0V)

II

µA

Command/Address

RAS#, CAS#, WE#, S#, CKE

-16

16

CK, CK#

-16

16

DM

-2

2

OUTPUT LEAKAGE CURRENT

(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)

IOZ

-5

5

µA

DQ, DQS, DQS#

VREF LEAKAGE CURRENT ; VREF is on a valid level

IVREF

-8

8

µA

DC OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

NOM

MAX

UNITS

Supply Voltage

VDD

1.425

1.5

1.575

V

I/O Supply Voltage

VDDQ

1.425

1.5

1.575

V

VDDL Supply Voltage

VDDL

1.425

1.5

1.575

V

I/O Reference Voltage

VREF

0.49 x VDDQ

0.50 x VDDQ

0.51x VDDQ

V

I/O Termination Voltage (system)

VTT

0.49 x VDDQ-20mV

0.50 x VDDQ

0.51x VDDQ+20mV

V

Input High (Logic 1) Voltage

VIH (DC)

VREF + 0.1

VDDQ + 0.3

V

Input Low (Logic 0) Voltage

VIL (DC)

-0.3

VREF – 0.1

V

AC INPUT OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Input High (Logic 1) Voltage

VIH (AC)

VREF + 0.175

-

V

Input Low (Logic 0) Voltage

VIL (AC)

-

VREF - 0.175

V

CAPACITANCE

At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.

When inductance and delay parameters associated with trace lengths are used in simulations, they are

significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then

render a considerably more accurate result. JEDEC modules are now designed by using simulations to close

timing budgets.

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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IDD Specifications and Conditions

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

Parameter

& Test Condition

Symbol

max.

Unit

12800 CL11

10600 CL9

8500 CL7

OPERATING CURRENT *) :

One device bank Active-Precharge;

tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH

between valid commands;

DQ inputs changing once per clock cycle; Address and

control inputs changing once every two clock cycles

IDD0

360

320

280

mA

OPERATING CURRENT *) :

One device bank; Active-Read-Precharge;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address inputs changing once every two

clock cycles; Data Pattern is same as IDD4W

IDD1

440

400

360

mA

PRECHARGE POWER-DOWN CURRENT:

All device banks idle; Power-down mode;

tCK = tCK (IDD); CKE is LOW; All Control and

Address bus inputs are not changing; DQ’s

are floating at VREF

Fast Exit

IDD2P

120

mA

Slow Exit

96

PRECHARGE QUIET STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All Control and Address bus inputs are not changing;

DQ’s are floating at VREF

IDD2Q

160

136

mA

PRECHARGE STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD2N

160

136

mA

ACTIVE POWER-DOWN CURRENT:

All device banks open; tCK = tCK (IDD); CKE is LOW; All

Control and Address bus inputs are not changing; DQ’s

are floating at VREF (always fast exit)

IDD3P

160

136

mA

ACTIVE STANDBY CURRENT:

All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD3N

280

240

mA

OPERATING READ CURRENT:

All device banks open, Continuous burst reads; One

module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL

= 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are changing once every two clock

cycles; DQ inputs changing once per clock cycle

IDD4R

720

600

520

mA

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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Parameter

& Test Condition

Symbol

max.

Unit

12800 CL11

10600 CL9

8500 CL7

OPERATING WRITE CURRENT:

All device banks open, Continuous burst writes; One

module rank active; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are changing once every two clock

cycles; DQ inputs changing once per clock cycle

IDD4W

760

640

560

mA

BURST REFRESH CURRENT:

tCK = tCK (IDD); refresh command at every tRFC (IDD) interval,

CKE is HIGH, CS# is HIGH between valid commands; All

other Control and Address bus inputs are changing once

every two clock cycles; DQ inputs changing once per

clock cycle

IDD5

960

920

880

mA

SELF REFRESH CURRENT:

CK and CK# at 0V; CKE ≤ 0.2V; All other Control and

Address bus inputs are floating at VREF; DQ’s are floating

at VREF

IDD6

96

mA

OPERATING CURRENT*) :

Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL

= CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC

= tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are not changing during DESELECT;

DQ inputs changing once per clock cycle

IDD7

1120

1080

840

mA

*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)

mode.

TIMING VALUES USED FOR IDD MEASUREMENT

IDD MEASUREMENT CONDITIONS

SYMBOL

12800 CL11

10600 CL9

8500 CL7

Unit

CL (IDD)

11

9

7

tCK

tRCD (IDD)

13.75

13.5

13.125

ns

tRC (IDD)

48.75

49.5

50.625

ns

tRRD (IDD)

6.25

6

7.5

ns

tCK (IDD)

1.25

1.5

1.87

ns

tRAS MIN (IDD)

35

36

37.5

ns

tRAS MAX (IDD)

70’200

ns

tRP (IDD)

13.75

13.5

13.125

ns

tRFC (IDD)

128

107

86

tCK

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

AC CHARACTERISTICS

12800 CL11

10600 CL9

8500 CL7

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

Unit

Clock cycle time

CL = 11

tCK (11)

1.25

1.5

-

ns

CL = 10

tCK (10)

1.5

<1.875

1.5

<1.875

-

ns

CL = 9

tCK (9)

1.5

<1.875

1.5

<1.875

-

ns

CL = 8

tCK (8)

1.875

<2.5

1.875

<2.5

1.875

<2.5

ns

CL = 7

tCK (7)

1.875

<2.5

1.875

<2.5

1.875

<2.5

ns

CL = 6

tCK (6)

2.5

3.3

2.5

3.3

2.5

3.3

ns

CL = 5

tCK (5)

3.0

3.3

3.0

3.3

3.0

3.3

ns

Read CMD to 1st data

tAA

13.75

-

13.5

-

13.125

-

ns

CK high-level width

tCH (avg)

0.47

0.53

0.47

0.53

0.47

0.53

tCK

CK low-level width

tCL (avg)

0.47

0.53

0.47

0.53

0.47

0.53

tCK

Data-out high-impedance

window from CK/CK#

tHZ

-

225

250

300

ps

Data-out low-impedance window

from CK/CK#

tLZ

-450

225

-500

250

-600

300

ps

DQ and DM input setup time

relative to DQS

tDS(Base)

-

30

25

ps

DQ and DM input hold time

relative to DQS

tDH(Base)

-

65

100

ps

DQ and DM input setup time

relative to DQS VREF=1V/ns

tDS1V

160

-

180

200

ps

DQ and DM input hold time

relative to DQS VREF=1V/ns

tDH1V

145

-

165

200

ps

DQ and DM input pulse width

( for each input )

tDIPW

360

400

490

ps

DQS, DQS# to DQ skew, per

access

tDQSQ

-

100

125

150

ps

DQ-DQS hold, DQS to first DQ

to go non-valid, per access

tQH

0.38

-

0.38

tCK

(AVG)

DQS input high pulse width

tDQSH

0.45

0.55

0.45

0.55

0.45

0.55

tCK

DQS input low pulse width

tDQSL

0.45

0.55

0.45

0.55

0.45

0.55

tCK

DQS, DQS# rising to/from CK,

CK#

tDQSCK

-225

225

-255

255

-300

300

ps

DQS, DQS# rising to/from CK,

CK# when DLL disabled

tDQSCK

DLL_DIS

1

10

1

10

1

10

ns

DQS falling edge to CK rising

- setup time

tDSS

0.18

-

0.2

tCK

DQS falling edge from CK rising

- hold time

tDSH

0.18

-

0.2

tCK

DQS read preamble

tRPRE

0.9

Note1

0.9

Note1

0.9

Note1

tCK

DQS read postamble

tRPST

0.3

Note2

0.3

Note2

0.3

Note2

tCK

DQS write preamble

tWPRE

0.9

tCK

DQS write postamble

tWPST

0.3

tCK

Positive DQS latching edge to

associated clock edge

tDQSS

- 0.27

+ 0.27

- 0.25

+ 0.25

- 0.25

+ 0.25

tCK

Address and control input pulse

width ( for each input )

tIPW

560

-

620

780

ps

CTRL, CMD, Addr setup to CK,

CK#

tIS(Base)

45

-

65

125

ps

CTRL, CMD, Addr setup to CK,

CK# VREF @ 1V/ns

tIS(1V)

220

-

240

300

ps

1 The maximum preamble is bound by tLZDQS (MAX)

2 The maximum postamble is bound by tHZDQS (MAX)

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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Switzerland

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

AC CHARACTERISTICS

12800 CL11

10600 CL9

8500 CL7

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

Unit

CTRL, CMD, Addr hold to CK,

CK#

tIH(Base)

120

-

140

200

ps

CTRL, CMD, Addr hold to CK,

CK# VREF @ 1V/ns

tIH(1V)

220

-

240

300

ps

CAS# to CAS# command delay

tCCD

4

-

4

tCK

ACTIVE to ACTIVE (same bank)

command period

tRC

48.75

-

49.5

50.625

ns

ACTIVE bank a to ACTIVE bank

b command

tRRD

max

4nCK,6ns

max

4nCK,6ns

max

4nCK,7.5ns

ns

ACTIVE to READ or WRITE

delay

tRCD

13.75

-

13.5

13.125

ns

Four bank

Activate period

1K Page size

30

40

-

30

37.5

ns

2K Page size

-

45

50

ACTIVE to PRECHARGE

command

tRAS

35

70’200

36

70’200

37.5

70’200

ns

Internal READ to precharge

command delay

tRTP

max

4nCK,7.5ns

-

max

4nCK,7.5ns

max

4nCK,7.5ns

ns

Write recovery time

tWR

15

-

15

ns

Auto precharge write recovery +

precharge time

tDAL

tWR +

tRP/tCK

-

tWR +

tRP/tCK

tWR +

tRP/tCK

ns

Internal WRITE to READ

command delay

tWTR

max

4nCK,7.5ns

-

max

4nCK,7.5ns

max

4nCK,7.5ns

ns

PRECHARGE command period

tRP

13.75

-

13.5

13.125

ns

LOAD MODE command cycle

time

tMRD

4

-

4

tCK

REFRESH to ACTIVE or

REFRESH to REFRESH

command interval

tRFC

160

70’200

160

70’200

160

70’200

ns

Average periodic refresh interval

0 °C ≤ TCASE ≤ 85°C

tREFI

-

7.8

µs

85 °C < TCASE ≤ 95°C

tREFI (IT)

-

3.9

RTT turn-on from ODTL on

reference

tAON

-225

225

-250

250

-300

300

ps

RTT turn-on from ODTL off

reference

tAOF

0.3

0.7

0.3

0.7

0.3

0.7

tCK

Asynchronous RTT turn-on

delay (power Down with DLL off)

tAONPD

2

8,5

2

8,5

2

8,5

ns

Asynchronous RTT turn-off

delay (power Down with DLL off)

tAOFPD

2

8,5

2

8,5

2

8,5

ns

RTT dynamic change skew

tADC

0.3

0.7

0.3

0.7

0.3

0.7

tCK

Exit self refresh to commands

not requiring a locked DLL

tXS

max

5nCK,tR

FC + 10ns

-

max

5nCK,tR

FC + 10ns

max

5nCK,tR

FC + 10ns

ns

Write levelling setup from rising

CK, CK# crossing to rising DQS,

DQS# crossing

tWLS

165

-

195

245

ps

Write levelling setup from rising

DQS, DQS# crossing to rising

CK, CK# crossing

tWLH

165

-

195

245

ps

First DQS, DQS# rising edge

tWLMRD

40

-

40

tCK

DQS, DQS# delay

tWLDQSEN

25

-

25

tCK

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

Industriestrasse 4 Fon: +41 71 913 03 03 www.swissbit.com Page 11

CH – 9552 Bronschhofen Fax: +41 71 913 03 15 eMail: info@swissbit.com of 17

Switzerland

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

AC CHARACTERISTICS

12800 CL11

10600 CL9

8500 CL7

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

Unit

Exit reset from CKE HIGH to a

valid command

tXPR

max

5nCK,

tRFC + 10ns

max

5nCK,

tRFC + 10ns

max

5nCK,

tRFC + 10ns

Begin power supply ramp to

power supplies stable

tVDDPR

200

ms

RESET# LOW to power supplies

stable

tRPS

0

200

ms

RESET# LOW to I/O and RTT

High-Z

tIOz

-

20

ns

Exit precharge power-down to

any non-READ command

tXP

max

3nCK,6ns

-

max

3nCK,6ns

max

3nCK,7.5ns

CKE minimum high/low time

tCKE

max

3nCK,

5ns

-

max

3nCK,

5.625ns

max

3nCK,

5.625ns

Temperature Sensor with Serial Presence-Detect EEPROM

SCL SDA

EVENT

SA2

SA1

SA0

EVENT

WP/

R1

0Ω

Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions

Parameter / Condition

Symbol

MIN

MAX

Unit

Supply voltage

VDDSPD

+3

+3.6

V

Supply current: VDD = 3.3V

IDD

+2.0

mA

Input high voltage: Logic 1; SCL, SDA

VIH

+1.45

VDDSPD +1

V

Input low voltage: Logic 0; SCL, SDA

VIL

-

550

mV

Output low voltage: IOUT= 2.1mA

VOL

-

400

mV

Input current

IIN

-5.0

5.0

µA

Temperature sensing range

TBD

°C

Temperature sensor accuracy

TBD

°C

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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Switzerland

A.C. Characteristics of Temperature Sensor

VCC = 3.3 V ± 10%, TA = −40°C to +125°C

Symbol

Parameter / Condition

MIN

MAX

Unit

fSCL

SCL clock frequency

10

400

kHz

tBUF

Bus Free Time Between STOP and START

1300

ns

tF

SDA fall time

300

ns

tR

SDA rise time

300

ns

tHD:DAT

Data hold time (accepted for Input Data)

0

ns

Data Hold Time (guaranteed for Output Data)

300

900

ns

tH:STA

Start condition hold time

600

ns

tHIGH

High Period of SCL

600

ns

tLOW

Low Period of SCL

1300

ns

tSU:DAT

Data setup time

100

ns

tSU:STA

Start condition setup time

600

ns

tSU:STO

Stop condition setup time

600

ns

tTIMEOUT

SMBus SCL Clock Low Timeout

25

35

ms

tI

Noise Pulse Filtered at SCL and SDA Inputs

100

ns

tWR

Write Cycle Time

5

ms

tPU

Power-up Delay to Valid Temperature Recording

100

ms

Temperature Characteristics of Temperature Sensor

VCC = 3.3 V ± 10%, TA = −40°C to +125°C

Parameter

Test Conditions/Comments

MAX

Unit

Temperature Reading Error

Class B, JC42.4 compliant

+75°C ≤ TA ≤ +95°C, active range

±1.0

°C

+40°C ≤ TA ≤ +125°C, monitor range

±2.0

°C

-40°C ≤ TA ≤ +125°C, sensing range

±3.0

°C

ADC Resolution

12

Bits

Temperature Resolution

0.0625

°C

Conversion Time

100

Ms

Thermal Resistance1 θJA

Junction-to-Ambient (Still Air)

92

°C/W

1 Power Dissipation is defined as PJ = (TJ − TA)/θJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal

resistance value refers to the case of a package being used on a standard 2-layer PCB.

Slave Address Bits of Temperature Sensor

Device

Device Type Identifier

Select Address Signals

R/W#

b71

b6

b5

b4

b3

b2

b1

b0

EEPROM

1

0

1

0

A2

A1

A0

R/W#

Temp. Sensor

0

1

A2

A1

A0

R/W#

1 The most significant bit, b7, is sent first.

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

Industriestrasse 4 Fon: +41 71 913 03 03 www.swissbit.com Page 13

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Switzerland

SERIAL PRESENCE-DETECT MATRIX

Byte

Byte Description

12800 CL11

10600 CL9

8500 CL7

0

CRC RANGE, EEPROM BYTES, BYTES USED

0x92

1

SPD REVISON

0x11

0x10

2

DRAM DEVICE TYPE

0x0B

3

MODULE TYPE (FORM FACTOR)

0x03

4

SDRAM DEVICE DENSITY & BANKS

0x03

5

SDRAM DEVICE ROW & COLUMN COUNT

0x19

6

DDR3-MODULE NOMINAL VDD

0x00

7

MODULE RANKS & DEVICE DQ COUNT

0x01

8

ECC TAG & MODULE MEMORY BUS WIDTH

0x03

9

FINE TIMEBASE DIVIDEND/DIVISOR

0x11

0x52

10

MEDIUM TIMEBASE DIVIDEND

0x01

11

MEDIUM TIMEBASE DIVISOR

0x08

12

MIN SDRAM CYCLE TIME (tCK MIN)

0x0A

0x0C

0x0F

13

BYTE 13 RESERVED

0x00

14

CAS LATENCIES SUPPORTED (CL4 => CL11)

0xFE

0x3C

0x1E

15

CAS LATENCIES SUPPORTED (CL12 => CL18)

0x00

16

MIN CAS LATENCY TIME (tAA MIN)

0x69

17

MIN WRITE RECOVERY TIME (tWR MIN)

0x78

18

MIN RAS# TO CAS# DELAY (tRCD MIN)

0x69

19

MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN)

0x30

0x3C

20

MIN ROW PRECHARGE DELAY (tRP MIN)

0x69

21

UPPER NIBBLE FOR tRAS & tRC

0x11

22

MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN)

0x18

0x20

0x2C

23

MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN)

0x81

0x89

0x95

24

MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB

0x00

25

MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB

0x05

26

MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN)

0x3C

27

MIN INTERNAL READ TO PRECHARGE CMD DELAY

(tRTP MIN)

0x3C

28

MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB

0x00

0x01

29

MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB

0xF0

0x2C

30

SDRAM DEVICE OUTPUT DRIVERS SUPPORTED

0x83

31

SDRAM DEVICE THERMAL & REFRESH OPTIONS

0x01

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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Switzerland

Byte

Byte Description

12800 CL11

10600 CL9

8500 CL7

32

DDR3-MODULE THERMAL SENSOR

0x80

33-59

BYTES 32-59 RESERVED

0x00

60

MODULE HEIGHT (NOMINAL)

0x0F

61

MODULE THICKNESS (MAX)

0x11

62

REFERENCE RAW CARD ID

0x01

63

ADDRESS MAPPING EDGE CONECTOR TO DRAM

0x00

64-116

BYTES 64-116 RESEVED

0x00

117

MODULE MFR ID (LSB)

0x83

118

MODULE MFR ID (MSB)

0xDA

119

MODULE MFR LOCATION ID

0x01 (Switzerland)

0x02 (Germany)

0x03 (USA)

120

MODULE MFR YEAR

X

121

MODULE MFR WEEK

X

122-125

MODULE SERIAL NUMBER

X

126-127

CRC

0x4B46

0xA0D2

0xE27B

128-145

MODULE PART NUMBER

" SGN02G64D2BD1SA-xx "

146

MODULE DIE REV

n.a.

147

MODULE PCB REV

n.a.

148

DRAM DEVICE MFR ID (LSB)

0x80

149

DRAM DEVICE MFR (MSB)

0xCE

150-175

MFR RESERVED BYTES 150-175

0x00

176-255

CUSTOMER RESERVED BYTES 176-255

0xFF

Part Number Code

S

G

N

02G

64

D2

B

D

1

SA

-

DC

*

R

**

1

2

3

4

5

6

7

8

9

10

11

12

13

14

*RoHs compl.

Swissbit AG

DDR3-1600MT/s

SDRAM DDR3

204 Pin SoDIMM 1.5V

Chip Vendor (Samsung)

Depth (2GB)

1 Module Rank

Width

Chip Rev. D

PCB-Type (S3D3B101)

Chip organisation x8

* optional / additional information

** T= thermal sensor

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

Industriestrasse 4 Fon: +41 71 913 03 03 www.swissbit.com Page 15

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Switzerland

Revision History

Revision

Changes

Date

1.0

Initial Revision

29.06.2011

1.1

SPD Byte 14 change (additional support for CL5) for E-grade

05.08.2012

1.2

Added DDR3-1600 speed grade

23.03.2012

1.3

SPD CRC Bytes for DDR3-1066 and 1333 corrected, added CE conformity

17.09.2012

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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Switzerland

Locations

Swissbit AG

Industriestrasse 4

CH – 9552 Bronschhofen

Switzerland

Phone: +41 71 913 03 03

Fax: +41 71 913 03 15

_____________________________

Swissbit Germany GmbH

Wolfener Strasse 36

D – 12681 Berlin

Germany

Phone: +49 30 93 69 54 – 0

Fax: +49 30 93 69 54 – 55

_____________________________

Swissbit NA

1117 E Plaza Drive Unit E Suite 105/205

Eagle, Idaho 83616

USA

Phone: +1 208 938 4525

Fax: +1 914 935 9865

_____________________________

Swissbit Japan Inc.

4F, 2-40-16 Umesato

Suginami-ku, Tokyo 166-0011

Japan

Phone: +81 3 33 17 12 11

Fax: +81 3 33 17 12 22

Data Sheet Rev.1.3 17.09.2012

Swissbit AG

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Switzerland

Declaration of Conformity

We

Manufacturer: Swissbit AG

Industriestrasse 4

CH-9552 Bronschhofen

Switzerland

declare under our sole responsibility that the product

Product Type: 2GB DDR3 SODIMM

Brand Name: SWISSMEMORY TM

Product Series: DDR3 SODIMM

Part Number: SGN0xG64xxxxxxx-xxxx

to which this declaration relates is in conformity with the following directives:

2002/96/EC Category 3 (WEEE)

following the provisions of Directive

Restriction of the use of certain hazardous substances

2011/65/EU

Swissbit AG, Oktober 2012

Manuela Kögel

Head of Quality Management

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Swissbit:

SGN02G64D2BD1SA-DCWRT