Cover 88EM8010/88EM8011 Power Factor Correction Controller Datasheet Customer Use Only Doc. No. MV-S104861-01, Rev. - September 30, 2009 Marvell. Moving Forward Faster Document Classification: Proprietary 88EM8010/88EM8011 Datasheet For further information about Marvell(R) products, see the Marvell website: http://www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. 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No. MV-S104861-01 Rev. - Page 2 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 88EM8010/88EM8011 Power Factor Correction Controller Datasheet PRODUCT OVERVIEW The Marvell(R) 88EM8010/88EM8011 device is a high performance Power Factor Correction (PFC) Controller for boost applications. The device is used for universal PFC front-end boost converters in system or standalone products. General Features Both devices work at fixed frequencies. 88EM8010 at 60kHz while 88EM8011 at 120kHz. Marvell advanced mixed signal technology ensures low Total Harmonic Distortion (THD). The IC operates under average Continuous Conduction Mode (CCM). The 88EM8010/88EM8011 PFC controller improves the steady state and transient performance through Marvell's innovative Digital Signal Processing (DSP) solution. The proprietary adaptive over-current protection has the ability to ensure almost constant power constraint and provides safety provisions including open loop and over voltage protection protocols. The internal voltage loop compensation and current loop control guarantees system stability and thus reduces the external component count and costs. The 8-pin SOIC package further facilitates the application design process, saving board space. The resultant simple system design and minimum cost makes 88EM8010/88EM8011 the ideal choice for PFC controllers. Patented DSP control with adaptive loop coefficient Continuous Conduction Mode (CCM) operation Average current mode control Adaptive control loop achieves high power factor for a wide range of voltage and load conditions Adaptive over current protection for universal voltage Fixed frequency of operation High power factor and low harmonic distortion for a wide range of load conditions Up to 2A driver capability Minimal external components required Under voltage lockout (UVLO) Over voltage protection (OVP) Thermal shutdown Input line frequency range from 45Hz to 65Hz Applications Universal front-end PFC boost controller AC/DC adaptors and battery chargers Electronic Ballasts front-end with PFC Figure 1: PFC Boost Circuit Diagram L Bridge Retifier PFC DR2 VO ut iL Rgate C IN Q1 AC IN Load C O2 R sen R cs Ra Rb SW ISNS SGND R S1 Rc VDD VIN CVDD VDD 88EM8010/ 8011 PGND FB Copyright (c) 2009 Marvell September 30, 2009, 2.00 R S2 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 3 88EM8010/88EM8011 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104861-01 Rev. - Page 4 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Table of Contents Table of Contents Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables .............................................................................................................................................. 9 1 Signal Description ....................................................................................................................... 11 1.1 Pin Configurations ...........................................................................................................................................11 1.2 Pin Descriptions ..............................................................................................................................................11 2 Electrical Specifications ............................................................................................................. 13 2.1 Absolute Maximum Ratings ...........................................................................................................................13 2.2 Recommended Operating Conditions .............................................................................................................14 2.3 Electrical Characteristics ................................................................................................................................15 3 Functional Description................................................................................................................ 19 3.1 Overview .........................................................................................................................................................19 3.2 Signal Process and Functions.........................................................................................................................20 4 Functional Characteristics ......................................................................................................... 21 4.1 VDD Characteristics ........................................................................................................................................21 4.2 VFB Characteristics for Over Voltage Protection .............................................................................................23 4.3 Switching Frequency Characteristics ..............................................................................................................25 4.4 Over Current Threshold Characteristics..........................................................................................................26 5 Design and Applications Information ........................................................................................ 27 5.1 Input Voltage Resistor Divider on VIN Pin.......................................................................................................27 5.2 Voltage Loop & Output Voltage Feedback on FB Pin .....................................................................................30 5.3 Current Sensing and Over Current Protection ................................................................................................31 5.3.1 Current Sensing through ISNS Pin ...................................................................................................31 5.3.2 Over Current Limitation.....................................................................................................................33 5.4 SW Pin to MOSFET Gate ...............................................................................................................................33 5.5 VDD, Signal Ground (SGND) and Power Ground (PGND) .............................................................................34 5.6 Boost PFC Schematics ...................................................................................................................................35 6 Mechanical Drawings .................................................................................................................. 37 6.1 Mechanical Drawings ......................................................................................................................................37 7 Part Order Numbering/Package Marking .................................................................................. 39 7.1 Part Order Numbering ..................................................................................................................................39 7.2 Package Markings...........................................................................................................................................40 Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 5 88EM8010/88EM8011 Datasheet G Revision History .......................................................................................................................... 41 Doc. No. MV-S104861-01 Rev. - Page 6 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 List of Figures List of Figures Figure 1: 1 PFC Boost Circuit Diagram ................................................................................................................3 Signal Description ........................................................................................................................... 11 Figure 2: SOIC-8 Pin Diagram (Top View).......................................................................................................11 2 Electrical Specifications ................................................................................................................. 13 3 Functional Description.................................................................................................................... 19 Figure 3: 4 5 6 Top Level Block Diagram..................................................................................................................19 Functional Characteristics.............................................................................................................. 21 Figure 4: IDD Quiescent (IDD_QST) vs. VDD ...................................................................................................21 Figure 5a: IDD vs. VDD (VDD_ON) ........................................................................................................................21 Figure 5b: IDD vs. VDD (VDD_ON), VFB Enable...................................................................................................21 Figure 6a: IDD Sleep (IDD_OP) vs. Temperature...............................................................................................22 Figure 6b: IDD Operation (IDD_OP) vs. Temperature ........................................................................................22 Figure 7: VDD On/Off vs. Temperature ...........................................................................................................22 Figure 8: IDD vs. VFB (OVP) .............................................................................................................................23 Figure 9: VFB_OVP vs. Temperature ..............................................................................................................23 Figure 10: VFB_OVP Hysteresis vs. Temperature ............................................................................................23 Figure 11: VFB_OVP_LATCH vs. Temperature ................................................................................................23 Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature ...........................................................24 Figure 13: IDD vs. VFB (Enable) .......................................................................................................................24 Figure 14: VFB_EN (Enable) vs. Temperature ..................................................................................................24 Figure 15: VFB_EN Hysteresis vs. Temperature ...............................................................................................24 Figure 16: Switching Frequency vs. Temperature .............................................................................................25 Figure 17: Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................26 Figure 18: Over Current (VIOVER) vs. Temperature .........................................................................................26 Design and Applications Information ............................................................................................ 27 Figure 19: Internal Block for Zero-cross Detection, Brown-out Protection .........................................................28 Figure 20: Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................29 Figure 21: Input Voltage Resistor Divider Layout Guidelines ............................................................................30 Figure 22: Output Voltage Resistor Divider .......................................................................................................31 Figure 23: Current Sensing Circuit.....................................................................................................................31 Figure 24: SW Pin Layout Guidelines ................................................................................................................33 Figure 25: VDD Decoupling Capacitor and Ground Layout Guidelines .............................................................34 Figure 26: 64W/450V Front-End Boost PFC Schematic ....................................................................................35 Figure 27: 300W/380V Front-End Boost PFC Schematic ..................................................................................36 Mechanical Drawings ...................................................................................................................... 37 Figure 28: 8-Pin SOIC Mechanical Drawing ......................................................................................................37 Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 7 88EM8010/88EM8011 Datasheet 7 G Part Order Numbering/Package Marking....................................................................................... 39 Figure 29: 88EM8010/88EM8011 Sample Ordering Part Number ....................................................................39 Figure 30: Package Marking and Pin 1 Location ...............................................................................................40 Revision History ............................................................................................................................... 41 Doc. No. MV-S104861-01 Rev. - Page 8 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 List of Tables List of Tables 1 2 Signal Description ............................................................................................................................ 11 Table 1: Pin Descriptions ................................................................................................................................11 Table 2: Pin Descriptions ................................................................................................................................12 Electrical Specifications .................................................................................................................. 13 Table 3: Absolute Maximum Ratings ..............................................................................................................13 Table 4: Recommended Operating Conditions...............................................................................................14 Table 5: Electrical Characteristics ..................................................................................................................15 3 Functional Description..................................................................................................................... 19 4 Functional Characteristics............................................................................................................... 21 5 Design and Applications Information ............................................................................................. 27 Table 6: Current Sensing Resistor Selection ..................................................................................................32 Table 7: Current Sensing Resistor Selection Reference ................................................................................32 6 Mechanical Drawings ....................................................................................................................... 37 7 Part Order Numbering/Package Marking........................................................................................ 39 Table 8: G 88EM8010/88EM8011 Part Order Options .......................................................................................39 Revision History ............................................................................................................................... 41 Table 9: Revision History ................................................................................................................................41 Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 9 88EM8010/88EM8011 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104861-01 Rev. - Page 10 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Signal Description Pin Configurations 1 Signal Description 1.1 Pin Configurations Figure 2: SOIC-8 Pin Diagram (Top View) 1.2 PGND 1 8 SW SGND 2 7 VDD ISNS 3 6 NC VIN 4 5 FB/EN Pin Descriptions Table 1: Pin Descriptions Pi n # P in N a m e P in Ty p e 1 PGND Ground Power Ground 2 SGND Ground Signal Ground 3 ISNS Input Current Sense 4 VIN Input Voltage Input 5 FB/EN Input Feedback/Enable/Shutdown 6 NC NC 7 VDD Supply IC Supply Voltage 8 SW Output Switch Copyright (c) 2009 Marvell September 30, 2009, 2.00 Pin Description No Connect Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 11 88EM8010/88EM8011 Datasheet Table 2: Pi n # Pin Descriptions P in N a m e D e sc r ip ti o n 1 PGND Power Ground Connected to the source of the primary MOSFET. The PCB trace from the power ground to the source of the MOSFET must be kept as short as possible. To avoid any switching noise interruption on signal processing, PGND and SGND remain separate inside the IC. 2 SGND Signal Ground Must be connected to the power ground with Kelvin sensing connection, so that SGND has dedicated trace and connections and provides noiseless environment for the signal processing. 3 ISNS Current Sense Sense resistor varies for different loads. Pin used for current shaping and for over current protection. Please refer to Section 5, Design and Applications Information, on page 27. 4 VIN Voltage Input * Connects to resistive divider at input AC line "phase" to GND. Voltage applied is a half rectified sine wave scaled down by the input resistive divider. * Voltage input pin is a high impedance input pin. An impedance of 2M (typical) is recommended to be designed from the input AC "phase" to GND in order to reduce the standby power. Higher impedance is preferred with the right PCB design on this pin signal. * Voltage is compared with a threshold reference (VVIN_BR) to detect the zero-cross location of the input sine wave and synthesize (regenerate) the input sine wave. This sine wave is used to generate the current reference. * Brown-out protection1 function is also provided by this pin. A resistor devider with a 100:1 ratio from the highside resistor to the lowside resistor is corresponding to the "brown-out protection" input voltage as 50V (RMS). Increasing that raio will increase the "brown-out voltage". Please refer to footnote1 for further explaination. 5 FB/EN Feedback The output voltage is scaled to 2.5V with 100% rated value. Transition from soft start to normal regulation at 87.5% rated VFB. Over voltage shutdown SW gate signal at 107% rated VFB and recover once below VFB_OVP. There is another threshold (VFB_OVP_LATCH) as 3.77V on the FB pin. When FB Voltage reaches VFB_OVP_LATCH, SW signal is shutdown and latched until another VDD power on reset. EN: Enable/Shutdown * At VFB>VFB_EN (Table 5) IC is enabled. * Pulling this pin to VFB < VFB_SHDN (Table 5) disables the chip back to sleep mode Note: A 200k resistor inside IL between FB pin to SGND. This should be included in the calculation for the design of the output voltage feedback resistor devider. 6 NC 7 VDD IC Supply Voltage Nominal voltage is 12V (typical) and the Under Voltage Lockout (UVLO) for VDD <VDD_UVLO (Table 5). When VDD < VDD_UVLO, IC is shut down. Start voltage of IC is VDD_ON (Table 5) and maximum voltage is 16V (Table 5). It should be clamped by a Zener for protection in the system design. 8 SW Switch PWM gate signal for the boost switch. Connects to the gate of external boost MOSFET. It is the DSP core output for ON/OFF time buffered through the internal adaptive driver. No Connect Float this pin. 1. Brown-out voltage is determined by Ra , Rb, and Rc as shown in Figure 1. Please refer to Section 5.1 for a further understanding. Doc. No. MV-S104861-01 Rev. - Page 12 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Electrical Specifications Absolute Maximum Ratings 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings1 NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Sy m b o l P a r a m e t er Min Max U n i ts VDD Power Supply (Voltage to PGND=SGND) -0.3 18 V VIsns Voltage at ISNS pin -0.5 3 V VVIN Voltage at VIN pin -0.3 5.5 V VFB Voltage at FB pin -0.3 5.5 V VSW Output Driver Voltage 18 V JA Thermal Resistance SOIC-8 156.5 C/W Thermal Resistance DIP-8 89.5 C/W 85 C 125 C 150 C 2 kV TA Operating Ambient Temperature Range2 TJ Maximum Junction Temperature TSTOR Storage Temperature Range VESD ESD Rating3 -40 -65 1. Exceeding the absolute maximum rating may damage the device. 2. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization and correlation with statistical process controls. 3. Devices are ESD sensitive. Handling precautions recommended. Human Body model, 1.5k in series with 100pF. Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 13 88EM8010/88EM8011 Datasheet 2.2 Table 4: Recommended Operating Conditions Recommended Operating Conditions1 Sy m b o l P a r a m e te r M in TA Operating Ambient Temperature2 TJ Junction Temperature Ty p Max U ni ts -40 85 C -20 125 C 1. This device is not guaranteed to function outside the specified operating temperature range. 2. Over the -40C to 85C operating temperature ranges are assured by design, characterization, and correlation with statistical process controls. Doc. No. MV-S104861-01 Rev. - Page 14 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Electrical Specifications Electrical Characteristics 2.3 Table 5: Electrical Characteristics Electrical Characteristics NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25C. Sy m b o l Parameter C on d it io n s M in Ty p Max Units 7.0 12 16 V VDD Supply VDD Supply Voltage VDD_ON VDD Power On Threshold First time power on operation 11.9 12.22 V VDD_UVLO VDD Power Off Threshold (UVLO) After VDD is powered up and running 7.0 7.2 V VDD_UVLO_HYS VDD_UVLO Hysteresis 5.3 V IDD_QST VDD Quiescent Current1 VDD = 12V 95 A IDD_OP VDD Operating Current VDD = 12V; CGate = 1nF FSW = 118kHz VIN= 0 6.2 mA 4.7 5.2 Thermal Shutdown TSD Thermal Shutdown 150 C TSD_HYS Hysteresis for Thermal Shutdown 25 C 10.0 V Gate Driver VG_HI Minimum Gate High Voltage2 VDD = 12V CGate = 1nF Sourcing 500mA VG_LO Maximum Gate Low Voltage3 VDD = 12V CGate = 1nF Sinking 500mA RDSON Gate Drive Resistance Sourcing 75mA T=25 C 2.4 Gate Drive Resistance Sinking 20mA T=25 C 2.0 ISW_PK Driver Peak Current CGate = 10 nF VDD = 12 V tR Rise Time CGate = 1 nF 35 ns CGate = 10 nF 125 ns CGate = 1 nF 35 ns CGate = 10 nF 145 ns tF Fall Time Copyright (c) 2009 Marvell September 30, 2009, 2.00 2.0 2.0 V A Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 15 88EM8010/88EM8011 Datasheet Table 5: Electrical Characteristics NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25C. Sy m b o l Parameter DMAX Maximum Duty Cycle C on d it io n s M in Ty p Max Units 97 % Feedback/Overvoltage VFB_REG Normal Regulation Reference IC powered on 2.55 V VFB_EN VFB at Enable Threshold IC powered on by VDD_ON. Transition from sleep mode to IC enable at Enable Threshold of VFB_EN 0.278 V VFB_SHDN VFB at Shutdown Threshold IC powered on by VDD_ON. Transfe from IC enable to sleep mode at Shutdown Threshold of VFB_SHDN 0.248 V VFB_EN_HYS VFB at Enable Hysteresis 0.03 V VFB_OVP Over Voltage Protection Threshold VFB_OVP_HYS Over Voltage Protection Hysteresis VFB_OVP_LATCH Over Voltage Protection Latch At 107% of VFB_REG. 2.67 2.71 0.102 2.75 V 0.108 V 3.77 V Current Sensing and Current Protection4 VIOVER_TH1 Over Current Threshold Zone 15 Peak value of half-sine voltage at VIN: 1.26<VIN<1.89Vpk6 397 mV VIOVER_TH2 Over Current Threshold Zone 25 Peak value of half-sine voltage at VIN: 1.89<VIN<2.59Vpk7 329 mV VIOVER_TH3 Over Current Threshold Zone 35 Peak value of half-sine voltage at VIN: 2.59< VIN<3.43Vpk8 269 mV VIOVER_TH4 Over Current Threshold Zone 45 Peak value of half-sine voltage at VIN: 3.43<VIN<3.85Vpk9 202 mV 59 kHz 88EM8010 Switching Frequency Oscillator FSW Frequency 88EM8011 Switching Frequency Oscillator FSW Frequency 100.3 118 135.7 kHz 1. Quiescent Current: VDD power supply current before VDD first time reaches VDD_On. Doc. No. MV-S104861-01 Rev. - Page 16 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Electrical Specifications Electrical Characteristics 2. Considering the voltage drop on the internal driver MOSFET during current sourcing. 3. Considering the voltage drop on the internal driver MOSFET during current sinking. 4. To achieve almost constant power limit for the universal input range, current protection self-adjusts thresholds in four zones of input voltage levels. A margin of 50% compared to the rated current is considered for the threshold current values. 5. Threshold of negative voltage drop across Rsns due to instantaneous current 6. With input divider ratio of 1/100, these values are equivalent to 90 Vrms<Vline<135 Vrms. 7. With input divider ratio of 1/100, these values are equivalent to 135 Vrms<Vline<185 Vrms. 8. With input divider ratio of 1/100, these values are equivalent to 185 Vrms<Vline<245 Vrms. 9. With input divider ratio of 1/100, these values are equivalent to 245 Vrms<Vline<275 Vrms. Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 17 88EM8010/88EM8011 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104861-01 Rev. - Page 18 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Functional Description Overview 3 Functional Description 3.1 Overview The 88EM8010/88EM8011 is a high performance, low-cost with minimum component count Power Factor Correction (PFC) Controller. The device is used for Universal PFC front-end boost converters in systems or standalone products. The high performance of 88EM8010/88EM8011 is accompanied with its small system size and simplicity of application. Figure 3 shows the top level block diagram. Figure 3: Top Level Block Diagram 88EM8010/8011 T_over Vo_over I_over Over Temperature Clock Oscillator Protection Management Fault Current Protection ISNS Current Amplifier FB SW Vo_over Zero Cross Detect Current Protection Threshold Selection PGND SGND Power Distribution and Bandgaps Serial Data Interface Startup Setting or Frequency Setting VDD Copyright (c) 2009 Marvell September 30, 2009, 2.00 Gate Driver DSP Core State Machine Output Voltage Level Detect VIN Driver Disable MUX Switcher & ADC Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 19 88EM8010/88EM8011 Datasheet 3.2 Signal Process and Functions The 88EM8010/88EM8011 boost power board includes three inputs: Resistive divider signal from AC line voltage Feedback from the output DC bus Voltage across the current sense resistor The input phase voltage to ground (half rectified sine wave) scaled down by the input resistive divider is applied to pin VIN. This signal used for estimation of the AC line voltage and regeneration of the AC sine wave. It is also used for voltage level detection that produces adaptive multiple thresholds for the over current limit and guarantees a constant power limit from the AC source. Signal from the DC bus voltage through the output resistor devider and Analog-to-Digital Converter (ADC) provides the feedback data for the voltage PI control loop. HF switching current pulse signal is retrieved from the voltage drop across the current sense resistor. Current sensing signal is negative to the ground. This signal after HF noise filter and fixed gain amplification, is transferred through the ADC to the digital current loop and the current error amplifier. The reference current for the current control PI loop is provided by multiplying the voltage error amplifier output and the regenerated sinusoidal line voltage information. Doc. No. MV-S104861-01 Rev. - Page 20 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Functional Characteristics VDD Characteristics 4 Functional Characteristics The following applies unless otherwise noted: VIN = 60Hz half-wave sinusoidal from 0V to the peak voltage (VPK) given in the test conditions of each graph. TA = 25C. All measurement readings are typical. 4.1 VDD Characteristics Figure 4: IDD Quiescent (IDD_QST) vs. VDD 100 90 80 IDD (A) 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 VDD (V) Test Conditions: VIN = 0V FSW = 118kHz VFB = 0V CGate = 1nF V_Isns = 0V Figure 5a: IDD vs. VDD (VDD_ON) Figure 5b: IDD vs. VDD (VDD_ON), VFB Enable 0.18 7 0.16 6 0.14 IDD (mA) IDD (mA) 5 VDD Falling VDD Rising 0.12 0.10 0.08 0.06 VDD Falling VDD Rising 4 3 2 0.04 1 0.02 0.00 0 5 10 15 20 0 0 2 4 6 VDD (V) Test Conditions: VIN = 0V FSW = 118kHz VFB = 0V CGate = 1nF V_Isns = 0V Test Conditions: VIN = 0V FSW = 118kHz Copyright (c) 2009 Marvell September 30, 2009, 2.00 8 10 12 14 16 VDD (V) VFB = 2.4V CGate = 1nF V_Isns = 0V Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 21 88EM8010/88EM8011 Datasheet Figure 6a: IDD Sleep (IDD_OP) vs. Temperature Figure 6b: IDD Operation (IDD_OP) vs. Temperature 0.25 7 0.20 5 IDD (mA) IDD (mA) 6 0.15 0.10 0.05 4 3 2 1 0.00 -40 -20 0 20 40 60 80 Temperature ( C) 0 -40 -20 0 20 40 60 80 Temperature ( C) Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz VFB = 0V CGate = 1nF V_Isns = 0V Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Figure 7: VDD On/Off vs. Temperature 14 On 12 VDD (V) 10 Off 8 6 4 Hysteresis 2 0 -40 -20 0 20 40 60 80 Temperature ( C) Test Conditions: VIN = 0V FSW = 118kHz FFB = 2.4V CGate = 1nF V_Isns = 0V Doc. No. MV-S104861-01 Rev. - Page 22 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Functional Characteristics VFB Characteristics for Over Voltage Protection 4.2 VFB Characteristics for Over Voltage Protection Figure 8: IDD vs. VFB (OVP) Figure 9: VFB_OVP vs. Temperature 6.5 3.0 6.0 2.5 5.0 Recovery Threshold 2.0 VFB Falling V F B (V ) IDD (mA) 5.5 OVP Threshold VFB Rising 4.5 1.5 1.0 4.0 3.5 0.5 3.0 2.0 2.2 2.4 2.6 2.8 0.0 3.0 -40 -20 0 VFB (V) Test Conditions: VDD = 12V VIN = 0V 20 40 60 80 Temperature ( C) Test Conditions: FSW = 118kHz CGate = 1nF V_Isns = 0V Figure 10: VFB_OVP Hysteresis vs. Temperature VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Figure 11: VFB_OVP_LATCH vs. Temperature 4.0 0.30 3.5 0.25 3.0 2.5 VFB (V) VFB (V) 0.20 0.15 2.0 1.5 0.10 1.0 0.05 0.5 0.00 0.0 -40 -20 0 20 40 60 80 -40 -20 0 Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V 40 Test Conditions: VDD = 12V VIN = 0V Copyright (c) 2009 Marvell September 30, 2009, 2.00 20 60 80 Temperature (C) Temperature ( C) FSW = 118kHz CGate = 1nF V_Isns = 0V Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 23 88EM8010/88EM8011 Datasheet Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature Figure 13: IDD vs. VFB (Enable) 7 6 3.0 2.9 5 IDD (mA) 2.8 VFB (V) 2.7 2.6 2.5 2.4 VFB Falling VFB Rising 4 3 2 2.3 1 2.2 2.1 0 0.0 2.0 -40 -20 0 20 40 60 0.2 0.4 80 0.6 0.8 1.0 VFB (V) Temperature (C) Test Conditions: VDD = 12V VIN = 2V FSW = 118kHz CGate = 1nF V_Isns = 0V Test Conditions: VDD = 12V VIN = 0V Figure 14: VFB_EN (Enable) vs. Temperature FSW = 118kHz CGate = 1nF V_Isns = 0V Figure 15: VFB_EN Hysteresis vs. Temperature 0.30 0.40 0.35 0.25 Enable High 0.25 VFB_En_hys (V) VFB (V ) 0.30 Enable Low 0.20 0.15 0.10 0.05 0.20 0.15 0.10 0.05 0.00 -40 -20 0 20 40 60 80 0.00 -40 -20 Temperature ( C) Test Conditions: VDD = 12V VIN = 0V 20 40 60 80 Temperature ( C) FSW = 118kHz CGate = 1nF V_Isns = 0V Test Conditions: VDD = 12V VIN = 0V Doc. No. MV-S104861-01 Rev. - Page 24 0 FSW = 118kHz CGate = 1nF V_Isns = 0V Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Functional Characteristics Switching Frequency Characteristics 4.3 Switching Frequency Characteristics Figure 16: Switching Frequency vs. Temperature 140 FSW (8011) Frequency (kHz) 120 100 80 FSW (8010) 60 40 20 0 -40 -20 0 20 40 60 80 Temperature (C) Test Conditions: VDD = 12V VIN = 0V VFB = 2.4V CGate = 1nF V_Isns = 0V Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 25 88EM8010/88EM8011 Datasheet 4.4 Over Current Threshold Characteristics Figure 17: Over Current (VIOVER) vs. Input Voltage VIN Peak Value) 0.50 0.45 0.40 V C S (V ) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 1 2 3 4 5 VIN (V) Test Conditions: VDD = 12V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Figure 18: Over Current (VIOVER) vs. Temperature 450 VIN = 1.5V 400 350 VIN = 2.25V VCS (V) 300 VIN = 3V 250 VIN = 3.7V 200 150 100 50 0 -40 -20 0 20 40 60 80 Temperature ( C) Test Conditions: VDD = 12V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Doc. No. MV-S104861-01 Rev. - Page 26 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Design and Applications Information Input Voltage Resistor Divider on VIN Pin 5 Design and Applications Information The boost converter is the most popular topology for two stage front-end PFC pre-regulator system. The 88EM8010/88EM8011 chip control algorithm uses Average Current Mode Control for power factor correction applications based on Boost topology with low harmonic distortion and good noise immunity. The IC senses the output voltage and forces it to follow the reference voltage to produce a stable DC output voltage matching the design requirement. It also senses the inductor current and forces the average signal of the inductor current to follow the sinusoidal current reference, therefore achieving unity power factor. Marvell's innovative PFC control technology improves the performance of the Boost converter used in PFC applications. The 88EM8010/88EM8011 provides the higher drive current capability than that of the competitors' ICs. The 88EM8010/8011 also achieves high power factor/low THD at high line low load condition which is benefited from Marvell mixed signal technology. The Boost PFC solution based on the 88EM8010/88EM8011 provides customers with the simplest structure, lowest cost and best performance compared with the other industry solutions currently on the market. The following sections provide guidelines for the application design, component selection, and board layout in order to improve front-end Boost PFC performance. There are three analog input signals listed below are required from the power train to the controller IC 88EM8010/88EM8011. 1. 2. 3. Input voltage signal at VIN pin is a half sinusoidal waveform. It is fed into the VIN pin through the input voltage resistor divider. This is for the line frequency zero-cross detection for PFC. Output voltage signal at FB pin is the output voltage through the resistor divider to feedback on FB pin. This is for the voltage loop regulation. Current sensing signal through the sensing resistor to the ISNS pin. This is for the average current mode control to achieve a good sinusoidal current waveform and high power factor. The output signal from the 88EM8010/88EM8011 is the PWM gate drive signal from the SW pin. The switching frequency on the 88EM8010 device is fixed to 60kHz (typical) while the 88EM8011 is fixed to 120kHz (typical). Both device tolerances are shown in Table 5, Electrical Characteristics, on page 15. 5.1 Input Voltage Resistor Divider on VIN Pin An accurate peak detection signal and zero-cross detection for regenerating the input sinusoidal voltage is the most important issue for a proper current shaping and total harmonic distortion (THD) improvement. If the threshold reference is too high, near the peak area, the calculation may lose accuracy because of the low slope. On the other hand, if the threshold reference is too low due to the possible distortions near the zero-crossing, there could be an error on zero-cross detection. For a universal input voltage range (85VAC~270VAC) the optimum accuracy would be achieved if the threshold level is around 30 degree of the line cycle. Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 27 88EM8010/88EM8011 Datasheet Figure 19: Internal Block for Zero-cross Detection, Brown-out Protection 88EM8010 /8011 Brown-Out Protection Vline _ pk AC IN Predictive Sinusoidal AC Voltage Phase ( ) Ra Rb VIN Rc Peak detecting pulse Zero Crossing Power Limit Threshold Selection To get a proper sinusoidal AC voltage, UVLO, and peak voltage detection, we need to choose the right value for the sensing resistors: Ra, Rb, and Rc (See Figure 19). If the value is too small there will be higher power loss and if the value is too big the resistor will not properly work due to the picking noise of the VIN signal. The recommended values are shown below: R a + R b 100 1.8M = = Rc 1 18k Equation (1) For the input voltage resistor divider, the appropriate combination based on the voltage / power rating of the resistors should also be considered. Doc. No. MV-S104861-01 Rev. - Page 28 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Design and Applications Information Input Voltage Resistor Divider on VIN Pin Figure 20: Peak Detecting Signal for Predictive Sinusoidal AC Voltage Vline_pk Vline_pk VVIN_BR = 0.72V (Typ.) V ( ) = Vline_pk x sin Half line cycle Half line cycle N M N Peak detecting Pulse As can be seen in Figure 20, the internal peak detecting circuit generates peak detecting pulse through the inside comparator which has a threshold voltage of 0.72V (typical). Processing of this pulse in DSP core calculates the mid-point (peak point) and the zero-crossing point of the sinusoidal waveform. The phase angle of is calculated using the width of the high and low signal M&N. N = ( - 2) Equation (2) M = ( + 2) Equation (3) (M - N) = ------------------- Equation (4) 4 Peak value of the sinusoidal waveform is introduced by the relation: V() V line_pk = --------------sin ( ) Equation (5) The signal that appears on the VIN pin is a half sinusoidal voltage waveform and its peak line value has to be higher than VVIN_BR of 0.72V (typical) for normal operation. Whenever the VVIN_BR is less than 0.72V at the peak line value, it is considered as a Brown-out condition. The IC only generates 6% duty during the brown-out condition. To adjust the brown-out protection point, the resistance value of Ra, Rb and Rc can be changed. With the recommended resistor values in Equation (1) the brown-out protection voltage is 72V peak value, which is around a 50V RMS value for the input line voltage. The layout of Rb, Rc and Cc should be kept as close as possible to the VIN pin, as shown in Figure 21 in order to have a proper layout on the input voltage resistor divider and to avoid noise picking. It is also recommended that a 0.1nF-10nF capacitor is connected between the VIN pin and ground with the layout also close to this pin. Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 29 88EM8010/88EM8011 Datasheet Figure 21: Input Voltage Resistor Divider Layout Guidelines Ra SW ISNS 88EM8010/ 8011 Rb Rc Cc PGND SGND V IN VDD FB Keep layout of Rb, Rc and Cc as close as possible to Vin pin to have high noise immunity 5.2 Voltage Loop & Output Voltage Feedback on FB Pin The 88EM8010/88EM8011 IC integrates the voltage loop into digital DSP core. This internal voltage loop has the lower corner frequency for the PFC requirement. The FB pin is the internal voltage loop feedback signal input. The voltage reference of the IC is 2.5V for the rated output voltage. It is well known that the front-end PFC with Boost topology has to maintain low enough bandwidth (less than 20Hz) in order to achieve a good sinusoidal current waveform and power factor under a wide input voltage and load condition. In order to achieve a good sinusoidal current waveform and power factor, the voltage loop regulation coefficient should also be designed properly corresponding to the different input voltages. The adaptive voltage loop coefficient is designed inside the IC to select different voltage regulation parameters corresponding to the different input voltage. This achieves a much better power factor and sinusoidal current waveform compared to any of PFC power system on the market now. The design of RS1and RS2, as shown in Figure 22, is based on the rated output voltage and the power loss of the resistor divider. In order to keep low power consumption on the resistor divider and good signal to noise immunity, a total resistance of several M is recommended for the pair of resistors RS1 and RS2. Because there is a 200k resistor inside of the IC between the FB pin to the SGND, the value of RS1 and RS2 is designed based on Equation (6) as: V out - V ref V ref V ref --------- + --------- = -----------------------R s2 R 0 R s1 Equation (6) Where Vref is 2.5V and R0 is 200k. Doc. No. MV-S104861-01 Rev. - Page 30 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Design and Applications Information Current Sensing and Over Current Protection Figure 22: Output Voltage Resistor Divider VOUT 88EM8010/ 8011 RS1 FB R S2 5.3 Current Sensing and Over Current Protection 5.3.1 Current Sensing through ISNS Pin The voltage drop on the current sense resistor should be kept very small in order to reduce the power consumption on the sense resistor (Rsen). The voltage drop (Vsen) across resistor (Rsen) represents the Boost current signal. As shown in Figure 23. Vsen is feedback to the ISNS pin through a resistor RCS, which is around 200. This resistor is necessary for the protection of the ISNS pin during inrush and lightning surge condition. The resistor (Rsen) should be designed and calculated such as the example in Table 6 where Rsen is designed for a 64W Boost converter. The specification are: output power = 64W, input voltage range = 85-264V, output voltage = 450V, 30% margin of over current on top of the normal current. Figure 23: Current Sensing Circuit L DR2 iL Q1 Vsen C O2 R sen R cs SW VIN VDD Using Kelvin sensing connection for current sensing signal and SGND with separate trace from PGND ISNS SGND 88EM8010/ 8011 PGND FB Copyright (c) 2009 Marvell September 30, 2009, 2.00 Load Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 31 88EM8010/88EM8011 Datasheet . Table 6: Current Sensing Resistor Selection Input Power PIN 64W Minimum Input Voltage VINMIN 85V Maximum Average Input Current I INMAX = Assume 30% Switching Frequency Ripple Peak Current with Ripple P IN 2 x -----------------V INMIN ripple = I INMAX x 30 % i peak = I INMAX + ripple 1.06A 0.32A 1.38A 0.391V Over Current Threshold Zone 1 (Table 5) VIOVERTH1 Over Current Margin IMARGIN Current Sensing Resistor Calculation V IOVERTH1 R sns = -----------------------------------------------------i peak x ( 1 + I MARGIN ) Current Sensing Resistor Selection Rsns 30% 0.22 0.25 Table 7 shows the reference value of the current sensing resistor. In the practical design, the current sensing resistor value could be fine tuned around the value shown in the table based on the specification and the primary inductance of the Boost transformer. Table 7: Current Sensing Resistor Selection Reference Input Power (W) 32 64 125 250 Current Sensing Resistor () 0.40-0.50 0.20-0.25 0.10-0.125 0.05-0.06 As the layout guideline, the current sensing signal should use Kelvin sensing connection, as shown in Figure 23. It means the SGND should layout as a separate trace from the PGND to avoid any heavy current and spike current sharing on that trace. The Vsen net should be layout as close as possible to the Rsen resistor. The same time, the Rsen resistor should be layout as close as possible to the ground as shown in Figure 23. Doc. No. MV-S104861-01 Rev. - Page 32 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Design and Applications Information SW Pin to MOSFET Gate 5.3.2 Over Current Limitation An adaptive current protection threshold is designed in the IC corresponding to the different input voltage in order to get the cycle by cycle current protection to avoid the transformer saturation. The four level threshold is shown in the electrical characteristic table. The universal input voltage is identified into four range from 90V to 275V. With the input voltage resistor divider ratio value as 100:1, these four ranges are 90-135V, 135-185V, 185-245V and 245V to 275V. If the resistor divider ratio value is increased from 100:1 to a higher value, these ranges will shift to the higher voltage side. On the other hand, if the resistor divider ratio value is decreased from 100:1 to a lower value, these ranges will shift to the lower voltage side. Therefore, the customer has the flexibility to adjust these ranges during the design by tuning the input voltage resistor divider ratio around the default value as 100:1. 5.4 SW Pin to MOSFET Gate The 88EM8010/88EM8011 provides a maximum 2A drive current, which is the strongest drive to date in comparison with the competition on the market. A default resistor of 10 is designed to go between the SW pin and the gate of the external MOSFET. The gate driver loop is subject to fast rise and the layout trace should be kept as short as possible in order to minimize the parasitic inductance, as shown in Figure 24. Figure 24: SW Pin Layout Guidelines Rgate Q1 Keep this trace as short as possible in layout SW VIN VDD ISNS SGND 88EM8010/ 8011 PGND FB Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 33 88EM8010/88EM8011 Datasheet 5.5 VDD, Signal Ground (SGND) and Power Ground (PGND) VDD is the IC power supply pin. It has a typical value of 12V and a maximum operating voltage of 16V. A Zener circuit below 16V is recommended in order to guarantee that the voltage on VDD will not go any higher than 16V. The IC begins to function when VDD powers on at 12V. Once the IC powers on, it keeps functioning as long as the VDD is higher than VDD_UVLO, which is 7V (typical). In a practical design, an electrolytic capacitor is recommended to connect between VDD and ground in order to retain the IC functionality during startup. That capacitor will need to keep the VDD higher than 7V before the bias transformer winding takes over and provides enough energy for the power IC. A 0.01-0.1F ceramic capacitor is strongly recommended to be placed between the VDD and IC ground with the layout trace as close to the IC as possible. This capacitor is used for decoupling the noise to VDD and clamping the VDD voltage during the switching of the internal driver circuit. SGND is directly connected to the system ground by a Kelvin connection trace. The system ground is the source of the MOSFET, as shown in Figure 25. PGND connects to the system ground separately and can not share the same trace with SGND. This is due to pulse current on PGND while driving the external MOSFET on and off. This pulse current produces pulse voltage drops on the PGND trace and may cause the current sensing signal to be distorted if the SGND shares the same trace. Figure 25: VDD Decoupling Capacitor and Ground Layout Guidelines Rgate Q1 Using Kelvin sensing connection for SGND with separate trace from PGND SW ISNS SGND PGND VIN FB 88EM8010/ 8011 C Keep this trace right beside IC and as short as possible VDD Doc. No. MV-S104861-01 Rev. - Page 34 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 September 30, 2009, 2.00 Copyright (c) 2009 Marvell Document Classification: Proprietary + C3 100uF D3 15V 1W R2 100k 1/4W R1 100k 1/4W HVDC R3 10R 1/4W C7 4.7uF SEC_2 VDD12 AC input 3A F1 C8 4.7uF D2 1N914 D1 1N91 4 R7 18k R6 600k R5 600k R4 600k SEC_1 T1 EMI FILTER 0.1nF C11 VIN C1 0.22uF 305 VAC D8 S1M D5 S1M HVDC I-SENSE D7 S1M D6 S1M 1 2 3 4 PGND SGND SW VDD N/C FB/EN 8 7 6 5 FB-EN GATE RGATE 10 C9 0.1uF VDD12 R11 8.66k R10 487k 88EM8011 R15 499k R13 499k 0.2R 1W R9 R14 10k C10 0.01uF 630VDC D4 STTH806DTI R8 200R I-SENSE ISNS VIN U1 SEC_2 Q1 GATE STP8NM60 T2 C2 0.22uF 305 VAC SEC_1 EP + C4 47uF 250V + C5 47uF 250V +450VDC DC output J2 5.6 9 J1 Design and Applications Information Boost PFC Schematics Boost PFC Schematics Figure 26: 64W/450V Front-End Boost PFC Schematic Doc. No. MV-S104861-01 Rev. - Page 35 N +20VDC VAC L G R1 ZERO 1/4W Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary R3 12.0k 1 2 Q3 MMBT2222A 3 R29 187k ZD3 18V R4 3 OPEN ZD2 15V 1 4 ZD1 15V 2 R2 1 10K 4 1 4 R6 22.0k 1206 2 R10 22.0k 1206 R11 22.0k 1206 3 220uF/25V + C1 C12 220pF/250V C5 470pF/250V C4 C3 470pF/250V 1uF/275V +15VDC Q2 PZT3904T1G SOT223 LF2 C6 1uF/275V 2 3 OPTIONAL Q4 1N60 SOT223 R5 1.8M 1206 R7 1.8M 1206 R8 1.8M 1206 + R21 665k 1206 R20 665k 1206 R22 665k 1206 380VDC C2 330uF/25V C9 470pF/250V C8 470pF/250V LF1 4 2 3 4.5mH 4AMPS 1 R19 200k 1206 R9 200k 1206 3 4 - 1 BD1 + KBU605G C19 10nF C7 0.33uF/630V R24 6.04k R23 200k 1206 2 6 4 60T 3T 9 U1 N/C VIN 88EM8011 R16 0 R13 4.99 1206 FB/EN VDD 8 1 R12 20K 2 C18 OPEN 3 1 3 R25 200 R26 0.040 2512 5 7 D4 IDH08SG60C C10 2 1500pF/630V 14 L1: 250uH Q1 IPW50R250CP 1278 16 D2 UF4002 ISNS NTC1 5 D1 UF4002 +20VDC SGND FA1 5A C13 10uF SENSE GROUND PGND POWER GROUND SW Page 36 C14 10uF D3 1N5406 C11 330uF/450V 380VDC C15 OPEN C16 0.1uF C17 1uF +15VDC + R14 12.7k R18 604k 1206 R27 604k 1206 R28 604k 1206 VDC 88EM8010/88EM8011 Datasheet Figure 27: 300W/380V Front-End Boost PFC Schematic September 30, 2009, 2.00 Copyright (c) 2009 Marvell Mechanical Drawings 6 Figure 28: 8-Pin SOIC Mechanical Drawing Document Classification: Proprietary Mechanical Drawings Copyright (c) 2009 Marvell September 30, 2009, 2.00 6.1 All dimensions in mm. See Section 7, Part Order Numbering/Package Marking, on page 39 for package marking and pin 1 location. Mechanical Drawings Mechanical Drawings Page 37 Doc. No. MV-S104861-01 Rev. - Notes: 88EM8010/88EM8011 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104861-01 Rev. - Page 38 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 Part Order Numbering/Package Marking Part Order Numbering 7 Part Order Numbering/Package Marking 7.1 Part Order Numbering Figure 29 shows the part order numbering scheme. For complete ordering information, contact your Marvell FAE or sales representative. Figure 29: 88EM8010/88EM8011 Sample Ordering Part Number 88EM8011 xx-SAG2C000-xxxx Custom code (optional) Part number Custom code Custom code Temperature code C = Commercial Custom code Environmental code + = RoHS 0/6 - = RoHS 5/6 1 = RoHS 6/6 2 = Green Halogen Free Package code The standard ordering part number for the respective solution is shown in Table 8. Table 8: 88EM8010/88EM8011 Part Order Options1 P a c k a g e Ty p e Part Order Number 8-Pin SOIC 88EM8010xx-SAG2C000-xxxx 8-Pin SOIC 88EM8010xx-SAG2C000-T (Tape and Reel) 8-Pin SOIC 88EM8011xx-SAG2C000-xxxx 8-Pin SOIC 88EM8011xx-SAG2C000-T (Tape and Reel) 1. Please note that the 88EM8010 device is 60kHz and the 88EM8011 device is 120kHz. Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 39 88EM8010/88EM8011 Datasheet 7.2 Package Markings Figure 30 shows a sample package marking and pin 1 location. Figure 30: Package Marking and Pin 1 Location MRVL 801X Marvell company abbreviation Abbreviated Part number XXXX = 4 character abbreviated part number YWWG Pin 1 location Date code and lot traceability code Y = Last digit of year WW = Work Week G = lot traceability code Note: The above example is not drawn to scale. Location of markings are approximate. Doc. No. MV-S104861-01 Rev. - Page 40 Copyright (c) 2009 Marvell Document Classification: Proprietary September 30, 2009, 2.00 G Table 9: Revision History Revision History D o cu m e n t Ty p e D o c u m e n t R e v is i o n 88EM8010/88EM8011 (Document = Rev. B) Break-out 8010 (60kHz) and 8011 (120kHz) Edits to Signals - Pin Descriptions EC Table edits - change in values Reworked Applications section Copyright (c) 2009 Marvell September 30, 2009, 2.00 Doc. No. MV-S104861-01 Rev. - Document Classification: Proprietary Page 41 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster