List of Figures
Copyright © 2009 Marvell Doc. No. MV-S104861-01 Rev. –
September 30, 2009, 2.00 Document Classification: Proprietary Page 7
List of Figures
Figure 1: PFC Boost Circuit Diagram ................................................................................................................3
1 Signal Description ........................................................................................................................... 11
Figure 2: SOIC-8 Pin Diagram (Top View).......................................................................................................11
2 Electrical Specifications ................................................................................................................. 13
3 Functional Description.................................................................................................................... 19
Figure 3: Top Level Block Diagram..................................................................................................................19
4 Functional Characteristics.............................................................................................................. 21
Figure 4: IDD Quiescent (IDD_QST) vs. VDD ...................................................................................................21
Figure 5a: IDD vs. VDD (VDD_ON)........................................................................................................................21
Figure 5b: IDD vs. VDD (VDD_ON), VFB Enable...................................................................................................21
Figure 6a: IDD Sleep (IDD_OP) vs. Temperature...............................................................................................22
Figure 6b: IDD Operation (IDD_OP) vs. Temperature ........................................................................................22
Figure 7: VDD On/Off vs. Temperature ...........................................................................................................22
Figure 8: IDD vs. VFB (OVP) .............................................................................................................................23
Figure 9: VFB_OVP vs. Temperature ..............................................................................................................23
Figure 10: VFB_OVP Hysteresis vs. Temperature ............................................................................................23
Figure 11: VFB_OVP_LATCH vs. Temperature ................................................................................................23
Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature ...........................................................24
Figure 13: IDD vs. VFB (Enable) .......................................................................................................................24
Figure 14: VFB_EN (Enable) vs. Temperature ..................................................................................................24
Figure 15: VFB_EN Hysteresis vs. Temperature...............................................................................................24
Figure 16: Switching Frequency vs. Temperature .............................................................................................25
Figure 17: Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................26
Figure 18: Over Current (VIOVER) vs. Temperature .........................................................................................26
5 Design and Applications Information............................................................................................ 27
Figure 19: Internal Block for Zero-cross Detection, Brown-out Protection.........................................................28
Figure 20: Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................29
Figure 21: Input Voltage Resistor Divider Layout Guidelines ............................................................................30
Figure 22: Output Voltage Resistor Divider .......................................................................................................31
Figure 23: Current Sensing Circuit.....................................................................................................................31
Figure 24: SW Pin Layout Guidelines ................................................................................................................33
Figure 25: VDD Decoupling Capacitor and Ground Layout Guidelines .............................................................34
Figure 26: 64W/450V Front-End Boost PFC Schematic ....................................................................................35
Figure 27: 300W/380V Front-End Boost PFC Schematic..................................................................................36
6 Mechanical Drawings ...................................................................................................................... 37
Figure 28: 8-Pin SOIC Mechanical Drawing ......................................................................................................37