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STLC60133
October 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
■LOW NOISE : 4nV/
■
HIGH PEAK OUTPUT C UR RE NT: 500 mA
■
HIGH SPEED
– 140MHz Gain Bandwidth
– 30MHz Gain Flatness
– 400 V/us Sl e w Rate
■LOW POWER OP ERATION
– ±5V to ±15V Voltage Supply
– 12.5 mA/A mp (typ) Supply current
– Power reduced Current
■LOW SINGLE TONE DISTORTION
■
THERMAL AND OVERLOAD PRO TECTION
■
HTSSOP28 PACKAGE
■
-40 TO +85°C OPERAT ING RANGE
DESCRIPTION
The STLC60133 is a dual amplifier featuring a high
slew rate and a large bandw idth optimized for XDS L
applicatio ns. The device i s available i n a HTSSOP 28
pin package (4x9 mm) with an exposed leadframe.
Thanks to its small pack age thi s l ine dr iv er is sui table
for high density ADSL line card.
Two digital pins (PWDN0 and PWDN1) allow the driv-
er to work in full performance mode, in low-power
mode or two intermediate bias states.
The low-pow er mode biases the output stage in order
to provide a low impedance at the amplifier outputs
for back termination.
The STLC60133 is designed optimizing bandwidth
and distorti on performances . For proper devic e oper-
ating it is necessary to work with a gain level greater
than 15.6dB.
Typ ical differential gain is normally +27dB, w hile typ-
ical common mode gain is 15.6dB
Hz
HTSSOP28
ORDERING NUMBER: STLC60133
Temperature Range: -40°C to +85°C
PRELIMINARY DATA
XDSL LINE DRIVER
Figure 1. BLOCK DIAGRAM
TH DETCT.
OUT1
+V
S
-V
S
OUT2
IN1N
IN1P
PWDN0
PWDN1
BIAS
DGND
IN2N
IN2P
Op1
-
+
-
+Op2
LOGIC
D00TL462A
STLC60133
2/9
PIN CONNECTION
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
Symbol Parameter Value Unit
VCC Positive Supply voltage (note1) +16.5 V
VSS Negative Supply voltage (note1) -16.5 V
Vid Differential Input Voltage (note2) ±5 V
ViCommon mode Input Voltage ±1 V
Top Operating Free Air Temperature Range -40 to +85 °C
Tstg Storage temperature -65 to +150 °C
TjJunction temperature 150 °C
Symbol Parameter Value Unit
Rthj-amb Thermal resistance junction to ambient (note 3) 29 °C/W
RES
N.C.
N.C.
IN2P
IN2N
+VS
OUT2
+VS
OUT1 DGND
-VS
-VS
PWDN1
BIAS
N.C.
N.C.
N.C.
RES1
3
2
4
5
6
7
8
9
26
25
24
23
22
20
21
19
27
10
28
IN1N N.C.
D00TL463A
IN1P
N.C
N.C. N.C.
N.C.
PWDN011
12
13
18
16
17
1514N.C. N.C.
3/9
STLC60133
OPERATING RANGE
Notes
1) All vol t ages values , ex cept diff erential volt age , are with respect to network groun d terminal .
2) Di ff erential volt ages are non-in verting i nput terminal with respect to the inve rting input te rm i nal
3) Specification is for device on a 4 layer board within 10 square inches of oz. copper at +85°C and 200m/s air vel ocity. With 0m/s air velocity
the param e t er i n creases up to 33°C/W
.
PIN DESCRIPTION
Power Down Management
The STLC60133 provides several quiescent bias levels from full performance, to reduced bias (in three steps
through PWDN0/1 pins) or to full OFF operation (through BIAS pin). According to the different XDSL application
(both site CO and CPE), different bias levels can be chosen maintaining good MTPR performances. In the fol-
lowing table are shown the bias levels versus the PWDN values.
Symbol Parameter Value Unit
Top Operating Temperature Range -40 to 85 °C
VCC Positive Supply voltage (note1) +5 to +15 V
VSS Negative Supply voltage (note1) -5 to -15 V
VDGND Digital Ground level VSS+5<VDGND<VCC-5 V
Vicm Common Mode Input Voltage Range ±1 V
N° Pin Description
2, 3, 12, 13, 14,
15, 16, 17, 19,
25, 26, 27
NC Not Connected
4 IN2P Non Inverting Input of Op. Amplifier 2
5 IN2N Inverting Input of Op. Amplifier 2
6 OUT2 Ouput of Op. Amplifier 2
7, 8 +Vs Positive Supply Voltage
9 OUT1 Ouput of Op. Amplifier 1
10 IN1N Inverting Input of Op. Amplifier 1
11 IN1P Non Inverting Input of Op. Amplifier 1
14 PWDN1 Power Down 1 logic input
18 PWDN0 Power Down 0 logic input
21, 22 -Vs Negative Supply Voltage
23 BIAS Bias Control pin
1, 28 RES To be left not connected
PWDN1 PWDN0 Bias Level
1 1 100%
1 0 60%
0 1 40%
0 0 25% (low Zout but not OFF)
X X Full OFF (High Zout via 250uA pulled out of BIAS pin)
STLC60133
4/9
The bias level is programmed by the TTL logic level applied to the PWDN pins. The DGND pin is the logic
ground reference for the PWDN pins. For normal operation the BIA S pin shall be left open.
The BIAS control pin can be used to adjust the internal biasing and thus the quiescent current. By pulling out a
current of 0
µ
A to 200
µ
A, the quiescent current can be adjusted from 100% (full ON) to a full OFF condition.
However, considering the internal parameter spread to full shutdown the STLC60133 is recommended to pull
down a 250
µ
A current from the BIAS pin. In the following figure is shown an implementation of a complete am-
plifier shutdown. To partially reduce the internal biasing also the PWDN pins can be used.
Figu re 2. Lo gi c dri ve of bia s pin fo r com plete Am pl i fier S hu t down.
THERMAL SHUTDOWN
A thermal protection is embedded in the STLC60133. In case of thermal overload the device is shut down at
160°C and returns to normal operation when the temperature becomes lower than 145°C.
During the therma l shutdown the voltage at the BIAS pin goes to the DGND rail; when the device retur ns to the
normal operation the voltage at the BIAS pin goes to the pos itive rail. In thi s condi tion the BI AS pin can be used
as thermal overload indicator.
MAX IMUM POWER DISSIP ATION
Maximum Junction Temperature allowed for proper device operation is T
j
= 140°C. A Typical Thermal Resis-
tance J unction to ambient of 29°C/W can be obtai ned moun ting the devi ce on a 4 lay er board whithi n 10 square
inches of copper and having the exposed pad contacting a proper copper area . It shall be noted that the ex-
posed pad of the device is electrically connected to the V
SS
negative supply.
Figure 3. Shutd ow n and alarm circu it
3.3V
BIAS
50KΩ
R1
D01TL492
R1 = 47KΩ for ± 12V
R1 = 22KΩ for ± 6V
R2
STLC60133
VCC
VCC+5V
ALARM
OR
VEE
BIAS
BIAS BIAS
BIAS
VBIAS=VCC -1.5V
OR 0-200µA
10KΩ
PWDN0 PWDN1
1/4 HCF40109B
ST
SHUT
DOWN
200µA10KΩ
1MΩ10KΩ
100KΩ
ALARM
D01TL491
MIN β 350
+5V
STLC60133
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STLC60133
ELECTRICAL CHARACTERISTCS
Test Condit ions: (V
CC
= ±12V , Tamb = 0 to 70°C , Single amplifier in normal condition (PWDN0 = 1, PWDN1 = 1),
unless otherwise specified). The limits listed below are guaranted in the above temperature range (0-70°C) by
specific testing at different temperature or by product characterisation.
TR ANSMISSION PATH
Notes: 1. The output stage of the STLC60133 is designed for maximum load current capability. As a result, shorting the output to common
can cause the STLC60133 to source or si nk 1.4A.
2. Guaranteed by product cha racter i zation.
Symbol Para mete r Test Cond ition Mi n. Typ. Max. Unit
SR Slew Rate G = 6, Vout = 2Vpp 400 V/us
GBW Gain Bandwidth G = 6, Vout = 2Vpp, f = 5MHz 90 140 MHz
THD Single ended Distortion G = 6, f = 1MHz, Vout = 12Vpp,
Rl = 16.5Ω
Rl = 100Ω-40
-45 -47
-52 dBc
DTHD Differential THD (2) G = 6, f = 1MHz, Vout = 24Vpp,
Rl = 33Ω
Rl = 100Ω-50
-55 dBc
IMD Single ended IMD G = 6, Vout = 3Vp each tone,
f = 500KHz, ∆f = 10KHz
Rl = 16.5Ω
Rl = 100Ω-54
-60 -70
-75 dBc
DIMD Differential IMD (2) G = 6, Vout = 6Vp each tone,
f = 500KHz, ∆f = 10KHz
Rl = 33Ω
Rl = 100Ω-66
-72 dBc
IB Input Biasing 5 µA
OZ Output Impedance PWDN0 = PWDN1 = 0; f = 1MHz 2 Ω
VN Voltage Noise (RTI) f = 30KHz 4 10 nV/
IOV Input Offset Voltage 6mV
ICMR Input Common Mode Voltage
Range f = 1 MHz -1 +1 V
CMRR Common Mode Rejection Ratio f = 1 MHz, Vin = 100mV 40 dB
OVS Output Voltage Swing Single ended, Rl = 100Ω, G = 6 -10.8 +10.8 V
LOC Linear Output Current Single ended, Rl = 10Ω, G = 6 400 600 mA
SCC Short Circuit Current (1) Single ended 1000 1400 mA
QC Quiescent Current PWDN1, PWDN0 = 1,1
PWDN1, PWDN0 = 1,0
PWDN1, PWDN0 = 0,1
PWDN1, PWDN0 = 0,0
12
8
5
4
16.2
10.7
7.5
5.3
mA/Amp
SC Shutdown Current 250µA out of Bias pin 1.5 2.0 mA/Amp
PSRR Power Supply Rejection ratio f = 500kHz, V = 100mV 30 dB
BIASV Bias Pin Voltage 10 10.5 V
DCG DC Gain 80 dB
Hz
STLC60133
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ELECTRICAL CHARACTERISTICS
Test conditions (V
CC
= ±6V, T
amb
= 0 to 70°C ,Single amplifier in normal condition (PWDN0 = 1, PWDN1 = 1),
unless otherwise specified.)
The limits listed below are guaranted in the above temperature range by (0-70°C)
specific testing at different temperature or by product characterisation.
TR ANSMISSION PATH
Notes: 1. The output stage of the STLC60133 is designed for maximum load current capability. As a result, shorting the output to common
can cause the STLC60133 to source or si nk 1.4A.
2. Guaranteed by product cha racter i zation.
Symbol Parameter Test Condition Min. Typ. Max. Unit
SR Slew Rate G = 6, Vout = 2Vpp 400 V/us
GBW Gain Bandwidth G = 6, Vout = 2Vpp, f = 5MHz 90 140 MHz
THD Single Ended Distortion G = 6, f = 1MHz, Vout = 6Vpp,
Rl = 25Ω
Rl = 100Ω-40
-45 -46
-51 dBc
DTHD Differential THD (2) G = 6, f = 1MHz, Vout = 12Vpp,
Rl = 25Ω
Rl = 100Ω-50
-55 dBc
IMD Single Ended IMD G = 6, Vout = 1.5Vp each tone,
f = 500KHz, ∆f = 10KHz
Rl = 25Ω
Rl = 100Ω-65
-70 -76
-81 dBc
DIMD Differential IMD (2) G = 6, Vout = 3Vp each tone,
f = 500KHz, ∆f = 10KHz
Rl = 25Ω
Rl = 100Ω-77
-82 dBc
IB Input Biasing 5 µA
VN Voltage Noise (RTI) f = 30KHz 4 10 nV/
IOV Input Offset Voltage 6mV
ICMR Input Common Mode Voltage
Range f = 1 MHz -1 +1 V
CMRR Common Mode Rejection Ratio f = 1 MHz, Vin = 100mV 40 dB
OVS Output Voltage Swing Single ended, Rl = 100Ω,
G = 6 -5 +5 V
LOC Linear Output Current Single ended, Rl = 10Ω,
G = 6 300 420 mA
SCC Short Circuit Current (1) Single ended, 1000 1400 mA
QC Quiescent Current PWDN1, PWDN0 = 1,1
PWDN1, PWDN0 = 1,0
PWDN1, PWDN0 = 0,1
PWDN1, PWDN0 = 0,0
10
7
5
3.5
13.7
9
6.5
4.5
mA/Amp
SC S hutdown Curre nt 25 0 µA out of Bias pin 1.5 2.0 mA/Amp
PSRR Power Supply Rejection ratio f = 500kHz, V = 100mV 30 40 dB
BIASV Bias Pin Voltage 4 4.5 V
DCG DC Gain 80 dB
Hz
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STLC60133
DIGITAL INTERFAC E (PWDN0, PWDN1, Vcc = ±12 V or ±6 V)
THERMAL PROTECTION
Figu re 4. S in gl e e nded Test C ir cui t G = 6
Figu re 5. Diffe r e nti a l Tes t Circuit G = 6
Symbol Parameter Test Condition Min. Typ. Max. Unit
Vil Input low voltag e 0 0.8 V
Vih I nput high voltage 2.2 5.5 V
Symbol Parameter Test Condition Min. Typ. Max. Unit
Thsd Thermal shut down threshold 160 °C
Thist Thermal detector histeresys 15 °C
10µF0.1µF
10µF0.1µF
200Ω1200Ω
R
L
VIN V
OUT
+
-
+V
S
-V
S
D00TL464
+VOUT
-VOUT
VIN
200Ω
200Ω
RL
1200Ω
1200Ω
10µF
0.1µF
+VS
+
-
-
+
D00TL465A
10µF
0.1µF
-VS
STLC60133
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OUTLINE AND
M E CHANICAL DATA
E1
A1 c
A
A2
be
D
D1
EE2
28 15
11 4
HTSSO28M
k
GAUGE PLANE
C
SEATING
PLANE
L
L1
Caaa
0.25mm
0.10inch
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.2 0.0
A1 0.15 0.006
A2 0.8 1.0 1.05 0.031 0.039 0.041
b 0.19 0.3 0.007 0.012
c 0.09 0.2 0.003 0.008
D (*) 9.6 9.7 9.8 0.377 0.382 0.385
D1 5.5 0.216
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 (*) 4.3 4.4 4.5 0.169 0.173 0.177
E2 3.0
e 0.65 0.026
L 0.45 0.6 0.75 0.018 0.024 0.029
L1 1.0 0.039
k 0˚ (min), 8˚ (max)
aaa 0.1 0.004
(*) Dimensions D and E1 does not include mold flash
or protusions. Mold flash or protusions shall not
exceed 0.15mm per side.
HTSSOP28
(Exposed Pad)
0.118
Information furnished is believed to be accurate and relia ble. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grant ed
by i m pl i cation or otherwise under an y paten t or patent r i ghts of STMicroel ectronic s. Sp ecificat i ons me ntione d i n thi s public ation are subj ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroel ectronics products are not
authorized for use as c ri tical com pone nts in lif e support d evices or sy st em s without express written ap proval of STM i croel ectronics.
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STLC60133
