256/512/1K/2K/4K x 9 Asynchronous FIFO
CY7C419/21/25/29/33
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06001 Rev. *A Revised December 30, 2002
19/21/25/29/
Features
• Asynchronous first-in first-ou t (FIF O) buffe r me morie s
• 256 x 9 (CY7C419)
• 512 x 9 (CY7C421)
• 1K x 9 (CY7C425)
• 2K x 9 (CY7C429)
• 4K x 9 (CY7C433)
• Dual-ported RAM cell
• High-spe ed 50.0- MHz read/w rite inde pend ent of
depth/width
• Low operating power: ICC = 35 mA
• Empty and Full flags (Half Full flag in standalon e)
• TTL compatible
• Retransmit in standalone
• Expan dable in width
• PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP
• Pin compatible and functionally equivalent t o IDT7200,
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
600-mil wide and 300-mil wide packages. They are, respec-
tively, 256, 5 12, 1,024, 2,0 48, and 4,096 words by 9-bit s wide.
Each FIFO memory is organized such that the data is read in
the same sequential order that it was written. Full and Empty
flags are pro vided to prevent ov errun and underrun. Three ad-
ditional pins are also prov ided to facilitat e unlimited exp ansion
in width, depth, or both. The depth expansion technique steers
the contro l signa ls from on e devic e to anoth er in paral lel, thu s
eliminating the serial addition of propagation delays, so that
throughp ut is not reduc ed. Data is s teered in a si milar manne r .
The read and write operations may be asynchronous; each
can occur at a rate of 50.0 MHz. The write operation occurs
when the write (W) signal is LOW . Read occ urs when read (R)
goes LOW. The nine data outputs go to the high-impedance
state when R is HIGH.
A Half Full (H F) outpu t flag is provided th at is valid in the stan-
dalone and width expansion configurations. In the depth ex-
pansion configuration, this pin provides the expansion out
(XO) informa tion that i s used t o tell the next FIFO th at it will b e
activated.
In the sta nda lone a nd width expan sion c onfigu rati ons, a LO W
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable (W) must both be
HIGH during retransmit, and then R is used to access the dat a.
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C4 28, CY7C429, CY 7C432, and C Y7C433 are fab ricated
using an advanced 0.65-micron P-well CMOS technology. In-
put ESD protec tio n is greater tha n 200 0V and latch-up is pr e-
vented by careful layout and guard rings.
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 2 of 22
Maximum Rating [1]
(Above w hi ch the useful life may be impaired. For user g uid e-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
Power Dissipation ..........................................................1.0W
Output Current, into Outputs (LOW)............................20 mA
Static Discharge Voltage...........................................>2000V
(per MIL–STD–883, Method 3015)
Latch-Up Current.....................................................>200 mA
Note:
1. Single Power Supply: The voltage on any input or I/O pin can not exceed the power pin during power-up.
RAMARRAY
256x 9
512x 9
1024x 9
2048x 9
4096x 9
LogicBlock Diagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
Top View
DIP
7C420/1
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
GND
Vcc
D4
FL/RT
MR
EF
XO/HF
Q7
R
PLCC/LCC
Top View
Q3
Q8
D5
D6
D7
Q6
Q5
Q4
4 3 2 1 323130
14 151617 181920
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
FL/RT
MR
EF
XO/HF
Q7
D6
Q6
D7
NC
READ
CONTROL
WRITE
CONTROL
WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
DATAINPUTS
(D0–D8)
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q0–Q8)
W
READ
POINTER
FLAG
LOGIC
R
XI
EF
FF
XO/HF
MR
FL/RT
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
D
D
W
NC
V
D
D
3
8
cc
4
5
Q
Q
GND
NC
R
Q
Q
3
8
4
5
C420–1
C420–2
C420–3
7C419
7C421/5/9
7C433 7C424/5
7C428/9
7C432/3
7C419
26
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 101112131415
32 3130 29 28 27 25
Q1
XI
Q0
D1
D0
NC
NC
FF
D
6
D
5
D
4
V
CC
W
D
8
D
3
D
2
D7
FL/RT
NC
NC
MR
EF
XO/HF
Q7
C420–4
Top View
TQFP
Q
2
Q
3
Q
8
GND
R
Q
4
Q
5
Q
6
16
7C419
7C421/5/9
7C433
Selection Guide
256 x 9 7C419–10 7C419–15 7C419–30 7C419–40
512 x 9 (600-mil only) 7C420–20 7C420–25 7C420–40 7C420–65
512 x 9 7C421–10 7C421–15 7C421–20 7C421–25 7C421–30 7C421–40 7C421–65
1K x 9 (600-mil only) 7C424–20 7C424–25 7C424–30 7C424–40 7C424–65
1K x 9 7C425–10 7C425–15 7C425–20 7C425–25 7C425–30 7C425–40 7C425–65
2K x 9 (600-mil only) 7C428–20 7C428–65
2K x 9 7C429–10 7C429–15 7C429–20 7C429–25 7C429–30 7C429–40 7C429–65
4K x 9 (600-mil only) 7C432–25 7C432–40
4K x 9 7C433–10 7C433–15 7C433–20 7C433–25 7C433–30 7C433–40 7C433–65
Frequency (MHz) 50 40 33.3 28.5 25 20 12.5
Maximum Access Time (ns) 10 15 20 25 30 40 65
ICC1 (mA) 35 35 35 35 35 35 35
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 3 of 22
Operating Range
Range Ambient Temperatu re[2] VCC
Commercial 0°C to + 70°C 5V ± 10%
Industrial –40°C to +85°C5V ± 10%
Military –55°C to +125°C 5V ± 10%
Electrical Characteristics Ov er the Op erating Range[3]
7C419–10, 15, 30, 40
7C420/1–10, 15, 20, 25, 30, 40, 65
7C424/5–10, 15, 20, 25, 30, 40, 65
7C428/9–10, 15, 20, 25, 30, 40, 65
7C432/3–10, 15, 20, 25, 30, 40, 65
Parameter Description Test Conditions Min. Max. Unit
VOH Output H IGH Voltage VCC = Min., IOH = –2.0 mA 2.4 V
VOL Output LO W Voltage VCC = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage Com’l2.0 VCC V
Mil/Ind 2.2 VCC
VIL Input LOW Voltage Note 4 0.8 V
IIX Input Leakage Current GND < VI < VCC –10 +10 µA
IOZ Output Lea ka ge Cu rren t R > VIH, GND < VO < VCC –10 +10 µA
IOS Output Short Circuit Current[5] VCC = Max., VOUT = GND –90 mA
Electrical Characteristics Ov er the Op erating Range[3] (continued)
7C419–10
7C421–10
7C425–10
7C429–10
7C433–10
7C419–15
7C421–15
7C425–15
7C429–15
7C433–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C433–20
7C420–25
7C421–25
7C424–25
7C425–25
7C429–25
7C432–25
7C433–25
Parameter Description Te st Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Operati ng Curren t VCC = Max.,
IOUT = 0 mA
f = fMAX
Com’l85 65 55 50 mA
Mil/Ind 100 90 80
ICC1 Operati ng Curren t VCC = Max.,
IOUT = 0 mA
F = 20 MHz
Com’l35 35 35 35 mA
ISB1 Standby C urren t All Inputs =
VIH Min. Com’l10 10 10 10 mA
Mil/Ind 15 15 15
ISB2 Power-Down Current All Inputs >
VCC –0.2V Com’l 5 5 5 5 mA
Mil/Ind 8 8 8
Notes:
2. TA is the “instant on” case temperature.
3. See the last page of thi s specifi cat io n for Gro up A subgro up testing informa t ion .
4. VIL (Min.) = –2.0V for pulse durations of less than 20 ns.
5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 4 of 22
Electrical Characteristics Ov er the Op erating Range[3] (continued)
7C419–30
7C421–30
7C424–30
7C425–30
7C429–30
7C433–30
7C419–40
7C420–40
7C421–40
7C424–40
7C425–40
7C429–40
7C432–40
7C433–40
7C420–65
7C421–65
7C424–65
7C425–65
7C428–65
7C429–65
7C433–65
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Units
ICC Operating Current VCC = Max.,
IOUT = 0 mA
f = fMAX
Com’l40 35 35 mA
Mil/Ind 75 70 65
ICC1 Operating Current VCC = Max.,
IOUT = 0 mA
F = 20 MHz
Com’l35 35 35 mA
ISB1 Standby Current All Inputs =
VIH Min. Com’l10 10 10 mA
Mil 15 15 15
ISB2 Power-Down Current All Inputs >
VCC –0.2V Com’l 5 5 5 mA
Mil 888
Capacitance[6]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 4.5V 6pF
COUT Output Capacitance 6pF
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 500Ω
R2
333Ω
30 pF
INCLUDING
JIGAND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
5V
OUTPUT
R1 500Ω
R2
333Ω
5pF
INCLUDING
JIGAND
SCOPE
OUTPUT 2V
Equivalent to: THÉ VENIN EQUIVALENT
(b)
C420–6C420–7C420–8
(a)
ALL INPUT PULSES
200Ω
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 5 of 22
Switching Characteristics Over the Operating Range[7, 8]
7C419–10
7C421–10
7C425–10
7C429–10
7C433–10
7C419–15
7C421–15
7C425–15
7C429–15
7C433–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C433–20
7C420–25
7C421–25
7C424–25
7C425–25
7C429–25
7C432–25
7C433–25
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cyc le Time 20 25 30 35 ns
tAAccess Time 10 15 20 25 ns
tRR Read Recovery Time 10 10 10 10 ns
tPR Read Puls e Wid th 10 15 20 25 ns
tLZR[6,9] Read LOW to Low Z 3 3 3 3 ns
tDVR[9,10] Data Valid After Read HIGH 5 5 5 5 ns
tHZR[6,9,10] Re ad HIGH to High Z 15 15 15 18 ns
tWC Write Cycle Time 20 25 30 35 ns
tPW Write Pulse Width 10 15 20 25 ns
tHWZ[6,9] Write HIGH to Low Z 5 5 5 5 ns
tWR Write Recovery Time 10 10 10 10 ns
tSD Data Set-Up Time 6 8 12 15 ns
tHD Data Hold Time 0 0 0 0 ns
tMRSC MR Cycle Time 20 25 30 35 ns
tPMR MR Pulse Width 10 15 20 25 ns
tRMR MR Recovery Time 10 10 10 10 ns
tRPW Read HIGH to MR HIGH 10 15 20 25 ns
tWPW Write HIGH to MR HIGH 10 15 20 25 ns
tRTC Retransmit Cycle T ime 20 25 30 35 ns
tPRT Re tran sm it Puls e Width 10 15 20 25 ns
tRTR Retransm it Recovery Ti me 10 10 10 10 ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30 pF load
capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
8. See the last page of thi s specifi cat io n for Gro up A subgro up testing informa t ion .
9. tHZR transition is measured at +200 mV from VOL and –200 mV from VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR transition is measured
at ±100 mV from the steady state.
10. tHZR and tDVR use capacitance loading as in part (b) of AC Test Load and Waveforms.
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 6 of 22
tEFL MR to EF LOW 20 25 30 35 ns
tHFH MR to HF HIGH 20 25 30 35 ns
tFFH MR to FF HIGH 20 25 30 35 ns
tREF Read LOW to EF LOW 10 15 20 25 ns
tRFF Read HIGH to FF HIGH 10 15 20 25 ns
tWEF Write HIGH to EF HIGH 10 15 20 25 ns
tWFF Write LOW to FF LOW 10 15 20 25 ns
tWHF Write LOW to HF LOW 10 15 20 25 ns
tRHF Read HIGH to HF HIGH 10 15 20 25 ns
tRAE Effective Read from Write HIGH 10 15 20 25 ns
tRPE Effec tive Read Pulse Wi dth After EF HIGH 10 15 20 25 ns
tWAF Effective Write from Read HIGH 10 15 20 25 ns
tWPF Effective Write Pulse Width After FF HIGH 10 15 20 25 ns
tXOL Expansion Out LOW Delay from Clock 10 15 20 25 ns
tXOH Expansion Out HIGH Delay from Clock 10 15 20 25 ns
Switching Characteristics Over the Operating Range[7, 8] (continued)
7C419–10
7C421–10
7C425–10
7C429–10
7C433–10
7C419–15
7C421–15
7C425–15
7C429–15
7C433–15
7C420–20
7C421–20
7C424–20
7C425–20
7C428–20
7C429–20
7C433–20
7C420–25
7C421–25
7C424–25
7C425–25
7C429–25
7C432–25
7C433–25
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 7 of 22
Switching Characteristics Over the Operating Range[7, 8] (continued)
7C419–30
7C421–30
7C424–30
7C425–30
7C429–30
7C433–30
7C419–40
7C420–40
7C421–40
7C424–40
7C425–40
7C429–40
7C432–40
7C433–40
7C420–65
7C421–65
7C424–65
7C425–65
7C428–65
7C429–65
7C433–65
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 40 50 80 ns
tAAccess Time 30 40 65 ns
tRR Read Recovery Time 10 10 15 ns
tPR Read Pulse Width 30 40 65 ns
tLZR[6,9] Read LOW to Low Z 3 3 3 ns
tDVR[9,10] Data Valid After Read HIGH 5 5 5 ns
tHZR[6,9,10] Read HIGH to High Z 20 20 20 ns
tWC W rite Cyc le Time 40 50 80 ns
tPW Wr ite Puls e Wid th 30 40 65 ns
tHWZ[6,9] W rite HIGH to Low Z 5 5 5 ns
tWR W rite R eco ve r y Time 10 10 15 ns
tSD Data Set-Up Time 18 20 30 ns
tHD Data Hold Time 0 0 0 ns
tMRSC MR Cycle Time 40 50 80 ns
tPMR MR Pulse Widt h 30 40 65 ns
tRMR MR Reco ve r y Time 10 10 15 ns
tRPW Read HIGH to MR HIGH 30 40 65 ns
tWPW Write HIGH to MR HIGH 30 40 65 ns
tRTC Re tran smit Cycle Time 40 50 80 ns
tPRT Retransmit Pulse Width 30 40 65 ns
tRTR Retransmit Recovery Time 10 10 15 ns
tEFL MR to EF LOW 40 50 80 ns
tHFH MR to HF HIGH 40 50 80 ns
tFFH MR to FF HIGH 40 50 80 ns
tREF Read LOW to EF LOW 30 35 60 ns
tRFF Read HIGH to FF HIGH 30 35 60 ns
tWEF Write HIGH to EF HIGH 30 35 60 ns
tWFF Write LOW to FF LOW 30 35 60 ns
tWHF Write LOW to HF LOW 30 35 60 ns
tRHF Read HIGH to HF HIGH 30 35 60 ns
tRAE Effective Read from Write HIGH 30 35 60 ns
tRPE Effective Read Pulse Width After EF HIGH 30 40 65 ns
tWAF Effective Write from Read HIGH 30 35 60 ns
tWPF Effective Writ e Pulse Width After FF HIGH 30 40 65 ns
tXOL Expansion Out LOW Del ay from Clo c k 30 40 65 ns
tXOH Expansion Out HIGH Delay from Clock 30 40 65 ns
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 8 of 22
Switching Waveforms
Notes:
11. W and R ≥ VIH around the rising edge of MR.
12. tMRSC = tPMR + tRMR.
DATA VALIDDATA VALID
DATA VALID DATA VALID
Asynchronous ReadandWrite
tSD tHD
tRC tPR
tAtRR tA
tLZR tDVR tHZR
tWC
tPW tWR
R
Q0–Q8
W
D0–D8
Master Reset
MR
R,W
HF
FF
EF
tMRSC
tPMR
tEFL
tHFH
tFFH
tRPW
tWPW tRMR
HALF FULL+1HALF FULL HALF FULL
W
R
HF tWHF
tRHF
Half-FullFlag
C420–9
C420–10
C420–11
[11]
[12]
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 9 of 22
Notes:
13. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC.
14. tRTC = tPRT + tRTR.
Switching Waveforms (continued)
Last Write to First Read Full Flag
Last Read to First Write Empty Flag
C420–12
C420–13
C420–14
LAST WRITE FIRST READ ADDITIONAL
READS FIRST WR ITE
VALID
LAST READ FIRST WRITE ADDITIONAL
WRITES FIRST READ
VALID
tREF tWEF
tRTC
tPRT
tRTR
tWFF tRFF
tA
W
R
EF
R
W
FF
DATA OUT
FL/RT
R,W
Retransmit[13]
[14]
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 10 of 22
Switching Waveforms (continued)
Empty Flag and Read Data Flow-Through Mode
Full Flag and Write Data Flow-Through Mode
C420–15
C420–16
R
W
FF
W
R
EF
DATA IN
DATA OUT
DATA IN
DATA OUT
DATA VALID
DATA VALID
DATA VALID
tRAE
tREF
tWEF tHWZ tA
tWAF tWPF
tWFF
tRFF
tSD
tHD
tA
tRPE
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 11 of 22
Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9,
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of du-
al-port RAM cells), a read pointer, a write pointer, control sig-
nals (W , R, XI, XO, FL, RT, MR), and Fu ll, Half Full, a nd Empty
flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory
cell us ed in the RAM. Th e cell itself en ables the read and wri te
operations to be independent of each other, which is neces-
sary to achieve trul y asynchronous operation of the inputs an d
outputs. A second benefit is that the time required to increment
the read and write pointers is much less than the time that
would be required for data propagation through the memory,
which would be the case if the memory were implemented
using the conventional register array architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycl e. This causes the FIF O to enter the empt y condition
signifi ed by the Em pty flag (EF) being LOW, and both the Ha lf
Full (HF) and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH tRPW/tWPW before and tRMR after the ris ing
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Note:
15. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2).
Switching Waveforms (continued)
ExpansionTiming Diagrams
C420–17
R
W
XO1(XI2)
D0–D8DA TA VALID
DATA DATA
VALID VALID
tXOL tXOH
tHD
tSD tSD tHD
tXOL
tLZR
tA
tDVR
tXOH
tA
tDVR
tHZR
XO1(XI2)
Q0–Q8
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1 WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1 READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
C420–18
tWR
tRR
DATA VALID
[15]
[15]
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 12 of 22
Writing Data to the FIFO
The ava ilabi lity o f at leas t one e mpty locat ion is indi cat ed by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D0–D8) tSD before and tHD after the
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW tWHF after the fa lli ng ed ge of W following the FIFO actu-
ally be ing H al f Ful l. Therefore, the HF is active once the FIFO
is fill ed to half its capaci ty plus one word . H F will remain LOW
while less than one half of total memory is available for writing.
The LOW -to-HIGH transi tion of HF occurs tRHF after t he ri sing
edge of R when the FIFO goe s from half full +1 to half full. HF
is available in standalone and width expansion modes. FF
goes L OW tWFF after the falling ed ge of W, during the cycl e in
which the last available location is filled. Internal logic prevents
overrunning a full FIFO . Writes to a full FIFO are ignored and
the write po inter is not incr emented. FF goe s HIGH tRFF after
a read from a full FIFO.
Reading Data from the FIFO
The fall ing edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q0–Q8) are in a high-impedance condition be-
tween read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the dep th expansio n
mode.
When one word is in the FIFO, the falling edg e o f R i n it iat e s a
HIGH-to-LOW transition of EF . The rising edge of R causes the
data outputs to go to the high-impedance state and remain
such until a write is performed. Reads to an empty FIFO are
ignored and do not increment the read pointer . From the empty
condition, the FIFO can be read tWEF after a valid write.
The retrans mi t featu re is be neficial when transferring pac ket s
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a numb er of wr ites equa l to or less than t he dep th of th e
FIFO have occurred since the last MR cycle . A LO W pu ls e o n
RT resets th e internal read poin ter to the fi rst physi cal locatio n
of the FIFO. R and W must both be HIGH while and tRTR after
retransm it is LOW. With every rea d cycle afte r retransmi t, pre-
viously accessed data as well as not previously accessed data
is read and the read pointer is incremented until it is equal to
the write po inter. Full, Half Full, and Empty fla gs are governe d
by the relativ e loc ations of th e read and wr ite p ointers and a re
updated during a retransmit cycle. Data written to the FIFO
after acti vation of RT are transmitted also.
Up to the full depth of the FIFO can be repeatedly retransmit-
ted.
Standalone /W idth Expa nsio n Modes
Standalone and width expansion modes are set by grounding
Expansi on I n (XI) an d tying First Load (FL) to VCC. FI FOs ca n
be expan ded in width to pro vide word widths g reater than nin e
in increments of nine. During width expansion mode, all control
line inputs are common to all devices, and flag outputs from
any device can be monitored.
Depth Expansion Mode (see Fig ure 1)
Depth expansion mode is entered when, during a MR cycle,
Expansi on O ut (XO) of one device is c onn ec ted t o Exp ans io n
In (XI) of the next device, with XO of the last device connecte d
to XI of the first dev ice. In the depth expans ion mod e the First
Load (FL) input, when gro un ded , indicates that th is pa rt is th e
first to be loaded. All other devices must have this pin HIGH.
To enable the correct FIFO, XO is pulsed LOW when the last
physic al loc ation of th e previo us FIFO is written to an d pulse d
LOW again when the last physical location is read. Only one
FIFO is enabled for read and one for write at any gi ven time.
All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and
width. Consequently, any depth or width FIFO can be created
of word widths in increments of 9. When ex panding in depth,
a composite FF must be created by ORing the FFs together.
Likew ise, a composite EF is cr eated by ORing th e EFs togeth-
er. HF and RT functions are not available in depth expansion
mode.
Use of the Empty and Full Flags
In order to ach ieve the m aximu m freq uency, the flags must be
valid at the beginning of the next cycle. However, because
they c an be updat ed by eithe r e dge o f the read o f wri te sig nal,
they mus t be valid by one-ha lf of a cycle. Cyp ress FIFOs me et
this requirement; some competitors’ FIFOs do not.
The reason why the flags are required to be valid by the next
cycle is fairly complex. It has to do with the “effective pulse
width violation” phenomenon, which can occur at the full and
empty boundary conditions, if the flags are not properly used.
The empty flag must be used to prevent reading from an empty
FIFO and the full flag must be used to prevent writing into a full
FIFO.
For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are ig-
nored by the FIFO , and nothi ng ha ppe ns . Next, a si ngl e wo rd
is written into the FIFO, with a signal that is asynchronous to
the read s ignal . The (in ternal) state m achine i n the FIF O goe s
from empty to empty+1. However, it does this asynchro nously
with respec t to the read sign al, so that it cannot b e determined
what the effective pulse width of the read signal is, because
the sta te machi ne do es no t loo k at the rea d signal u ntil it goe s
to the empty+1 state. In a similar manner, the minimum write
pulse width may be violated by attempting to write into a full
FIFO, and as yn chronously perfor mi ng a rea d. Th e em pty an d
full flags are used to avoid these effective pulse width viola-
tions, but in order to do this and operate at the maximum fre-
quency, the flag must be valid at the beginning of the next
cycle.
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 13 of 22
Figure 1. Depth Expansion
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
W
MR
XI
FL
EF
XO
FF
XI
FL
EF
XO
XI
FL
EF
XO
FF
R
EMPTY
FULL
Q
9
9
9
9
FF
VCC
* FIRSTDEVICE
*
C420–19
9CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
CY7C419
CY7C420/1
CY7C424/5
CY7C428/9
CY7C432/3
D
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 14 of 22
Ordering Information
Speed
(ns) Ordering Code Package
Type Package Type Operating
Range
10 CY7C419–10AC A32 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C419–10JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C419–10PC P21 28-Lead (300-Mil) Molded DIP
CY7C419–10VC V21 28-Lead (300-Mil) Molded SOJ
15 CY7C419–15AC A32 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C419–15JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C419–15VC V21 28-Lead (300-Mil) Molded SOJ
CY7C419–15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
30 CY7C419–30JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
40 CY7C419–40AC A32 32-Pin Thin Plastic Quad Flatpack
CY7C419–40JC J65 32-Lead Plastic Leaded Chip Carrier
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Type Package Type Operating
Range
25 CY7C420–25PC P15 28-Lead (600-Mil) Molded DIP Commercial
40 CY7C420–40PC P15 28-Lead (600-Mil) Molded DIP
65 CY7C420–65PC P15 28-Lead (600-Mil) Molded DIP
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Type Package Type Operating
Range
10 CY7C421–10AC A32 32-Pin Thin Plast ic Quad Flatpack Commercial
CY7C421–10JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C421–10PC P21 28-Lead (300-Mil) Molded DIP
CY7C421–10VC V21 28-Lead (300-Mil) Molded SOJ
15 CY7C421–15AC A32 32-Pin Thin Plast ic Quad Flatpack Commercial
CY7C421–15JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C421–15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C421–15VI V21 28-Lead (300-Mil) Molded SOJ
CY7C421–15DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C421–15LMB L55 32-Pin Rectangular Leadless Chip Carrier
20 CY7C421–20JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C421–20PC P21 28-Lead (300-Mil) Molded DIP
CY7C421–20VC V21 28-Lead (300-Mil) Molded SOJ
CY7C421–20JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
25 CY7C421–25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C421–25PC P21 28-Lead (300-Mil) Molded DIP
CY7C421–25VC V21 28-Lead (300-Mil) Molded SOJ
CY7C421–25JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C421–25PI P21 28-Lead (300-Mil) Molded DIP
CY7C421–25DMB D22 28-Lead (300-Mil) CerDIP Military
30 CY7C421–30JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C421–30PC P21 28-Lead (300-Mil) Molded DIP
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 15 of 22
30 CY7C421–30JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C421–30DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C421–30LMB L55 32-Pin Rectangular Leadless Chip Carrier
40 CY7C421–40JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C421–40PC P21 28-Lead (300-Mil) Molded DIP
CY7C421–40VC V21 28-Lead (300-Mil) Molded SOJ
CY7C421–40JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
65 CY7C421–65JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C421–65PC P21 28-Lead (300-Mil) Molded DIP
CY7C421–65VC V21 28-Lead (300-Mil) Molded SOJ
CY7C421–65JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C421–65DMB D22 28-Lead (300-Mil) CerDIP Military
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Type Package Type Operating
Range
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Type Pack age Type Operating
Range
40 CY7C424–40PC P15 28-Lead (600-Mil) Molded DIP Commercial
65 CY7C424–65PC P15 28-Lead (600-Mil) Molded DIP Commercial
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Type Package Type Operating
Range
10 CY7C425–10AC A32 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C425–10JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C425–10PC P21 28-Lead (300-Mil) Molded DIP
CY7C425–10VC V21 28-Lead (300-Mil) Molded SOJ
15 CY7C425–15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C425–15PC P21 28-Lead (300-Mil) Molded DIP
CY7C425–15DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C425–15LMB L55 32-Pin Rectangular Leadless Chip Carrier
20 CY7C425–20JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C425–20PC P21 28-Lead (300-Mil) Molded DIP
CY7C425–20VC V21 28-Lead (300-Mil) Molded SOJ
25 CY7C425–25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C425–25PC P21 28-Lead (300-Mil) Molded DIP
CY7C425–25JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C425–25VI V21 28-Lead (300-Mil) Molded SOJ
CY7C425–25DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C425–25LMB L55 32-Pin Rectangular Leadless Chip Carrier
30 CY7C425–30JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C425–30PC P21 28-Lead (300-Mil) Molded DIP
CY7C425–30VC V21 28-Lead (300-Mil) Molded SOJ
CY7C425–30VI V21 28-Lead (300-Mil) Molded SOJ Industrial
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 16 of 22
40 CY7C425–40JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C425–40PC P21 28-Lead (300-Mil) Molded DIP
CY7C425–40VC V21 28-Lead (300-Mil) Molded SOJ
CY7C425–40JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
65 CY7C425–65JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C425–65PC P21 28-Lead (300-Mil) Molded DIP
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Type Package Type Operating
Range
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Type Package Type Operating
Range
20 CY7C428–20PC P15 28-Lead (600-Mil) Molded DIP Commercial
25 CY7C428–25DMB D16 28-Lead (600-Mil) CerDIP Military
65 CY7C428–65PC P15 28-Lead (600-Mil) Molded DIP Commercial
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Type Package Type Operating
Range
10 CY7C429–10AC A32 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C429–10JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C429–10PC P21 28-Lead (300-Mil) Molded DIP
15 CY7C429–15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C429–15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C429–15DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C429–15LMB L55 32-Pin Rectangular Leadless Chip Carrier
20 CY7C429–20JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C429–20PC P21 28-Lead (300-Mil) Molded DIP
CY7C429–20VC V21 28-Lead (300-Mil) Molded SOJ
CY7C429–20DMB D22 28-Lead (300-Mil) CerDIP Military
25 CY7C429–25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C429–25PC P21 28-Lead (300-Mil) Molded DIP
CY7C429–25VC V21 28-Lead (300-Mil) Molded SOJ
CY7C429–25JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C429–25DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C429–25LMB L55 32-Pin Rectangular Leadless Chip Carrier
30 CY7C429–30JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C429–30PC P21 28-Lead (300-Mil) Molded DIP
CY7C429–30VC V21 28-Lead (300-Mil) Molded SOJ
CY7C429–30DMB D22 28-Lead (300-Mil) CerDIP Military
40 CY7C429–40AC A32 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C429–40JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C429–40PC P21 28-Lead (300-Mil) Molded DIP
65 CY7C429–65JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C429–65PC P21 28-Lead (300-Mil) Molded DIP
CY7C429–65JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 17 of 22
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
25 CY7C432–25PC P15 28-Lead (600-Mil) Molded DIP Commercial
40 CY7C432–40PC P15 28-Lead (600-Mil) Molded DIP Commercial
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
10 CY7C433–10AC A32 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C433–10JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C433–10PC P21 28-Lead (300-Mil) Molded DIP
CY7C433–10VC V21 28-Lead (300-Mil) Molded SOJ
15 CY7C433–15AC A32 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C433–15JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C433–15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C433–15PI P21 28-Lead (300-Mil) Molded DIP
CY7C433–15DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C433–15LMB L55 32-Pin Rectangular Leadless Chip Carrier
20 CY7C433–20AC A32 32-Pin Thin Plastic Quad Flatpack Commercial
CY7C433–20JC J65 32-Lead Plastic Leaded Chip Carrier
CY7C433–20PC P21 28-Lead (300-Mil) Molded DIP
25 CY7C433–25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C433–25PC P21 28-Lead (300-Mil) Molded DIP
CY7C433–25VC V21 28-Lead (300-Mil) Molded SOJ
CY7C433–25JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
30 CY7C433–30JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C433–30PC P21 28-Lead (300-Mil) Molded DIP
CY7C433–30JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
CY7C433–30PI P21 28-Lead (300-Mil) Molded DIP
CY7C433–30DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C433–30LMB L55 32-Pin Rectangular Leadless Chip Carrier
40 CY7C433–40JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C433–40PC P21 28-Lead (300-Mil) Molded DIP
CY7C433–40VC V21 28-Lead (300-Mil) Molded SOJ
CY7C433–40JI J65 32-Lead Plastic Leaded Chip Carrier Industrial
65 CY7C433–65JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C433–65PC P21 28-Lead (300-Mil) Molded DIP
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 18 of 22
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL Max. 1, 2, 3
IIX 1, 2, 3
ICC 1, 2, 3
ICC1 1, 2, 3
ISB1 1, 2, 3
ISB2 1, 2, 3
IOS 1, 2, 3
Switching Characteristics
Parameters Subgroups
tRC 9, 10, 11
tA9, 10, 11
tRR 9, 10, 11
tPR 9, 10, 11
tDVR 9, 10, 11
tWC 9, 10, 11
tPW 9, 10, 11
tWR 9, 10, 11
tSD 9, 10, 11
tHD 9, 10, 11
tMRSC 9, 10, 11
tPMR 9, 10, 11
tRMR 9, 10, 11
tRPW 9, 10, 11
tWPW 9, 10, 11
tRTC 9, 10, 11
tPRT 9, 10, 11
tRTR 9, 10, 11
tEFL 9, 10, 11
tHFH 9, 10, 11
tFFH 9, 10, 11
tREF 9, 10, 11
tRFF 9, 10, 11
tWEF 9, 10, 11
tWFF 9, 10, 11
tWHF 9, 10, 11
tRHF 9, 10, 11
tRAE 9, 10, 11
tRPE 9, 10, 11
tWAF 9, 10, 11
tWPF 9, 10, 11
tXOL 9, 10, 11
tXOH 9, 10, 11
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 19 of 22
Package Diagrams
32-Lead Thin PlasticQuad Flat Pack A32
28-Lead (600-Mil) CerDIP D16
MIL-STD-1835 D- 10Config.A 28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D- 15 Config.A
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 20 of 22
Package Diagrams (continued)
32-Lead Plastic Leaded Chip Carrier J65
32-Pin Rectangular Leadless Chip CarrierL55
MIL-STD-1835 C-12
28-Lead (600-Mil) Molded DIP P15
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 21 of 22
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
28-Lead (300-Mil) Molded DIP P21
28-Lead (300-Mil) Molded SOJ V21
CY7C419/21/25/29/33
Document #: 38-06001 Rev. *A Page 22 of 22
Document Title: CY7C419, CY7C421, CY7C425, CY7C429, CY7C433 256/512/1K/2K/4Kx9 Asynchronous FIFO
Document Number: 38 -06001
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 106462 07/11/01 SZV Change from Spec Number: 38-00079 to 38-06001
*A 122332 12/30/02 RBI Added power up requirements to maximum ratings information.
