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FEATURES
§ Integrates NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
§ Clock registers are accessed identically to the
static RAM. These registers are resident in
the eight top RAM locations
§ Totally nonvolatile with over 10 years of
operation in the absence of power
§ Access time of 120 ns and 150 ns
§ BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100
§ Power-fail write protection allows for ±10%
VCC power supply tolerance
§ DS1646 only (DIP Module)
− Standard JEDEC byte-wide 128k x 8
RAM pinout
§ DS1646P only (PowerCap Module Board)
− Surface mountable package for direct
connection to PowerCap containing
battery and crystal
− Replaceable battery (PowerCap)
− Power-fail output
− Pin-for-pin compatible with other
densities of DS164XP Timekeeping
RAM
ORDERING INFORMATION
DS1646-XXX 32-pin DIP module
-120 120 ns access
-150 150 ns access
*DS1646P-XXX 34-pin PowerCap Module
Board
-120 120 ns access
-150 150 ns access
*DS9034PCX Power Cap
(Required; must be ordered
separately)
PIN ASSIGNMENT
DS1646/DS1646P
Nonvolatile Timekeeping RAM
www.dalsemi.com
1
NC
2
3
A15
A16
PFO
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
NC
X1
GND
VBAT
X2
34-PIN POWERCAP MODULE BOARD
(USES DS9034PCX POWERCAP)
13
1
2
3
4
5
6
7
8
9
10
11
12
14
31
32-PIN ENCAPSULATED PACKAGE
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
V
CC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
NC
DQ2
GND
15
16
18
17
DQ4
DQ3
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PIN DESCRIPTION
A0-A16 - Address Input
CE - Chip Enable
OE - Output Enable
WE - Write Enable
VCC - +5 Volts
GND - Ground
DQ0-DQ7 - Data Input/Output
NC - No Connection
PFO - Power-fail Output
(DS1646P only)
X1, X2 - Crystal Connection
VBAT - Battery Connection
DESCRIPTION
The DS1646 is a 128k x 8 nonvolatile static RAM with a full-function real time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any
JEDEC standard 128k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real
time clock information resides in the eight uppermost RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access
of incorrect data that can occur during clock update cycles. The double-buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1644
also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low VCC as errant access and update cycles are avoided.
PACKAGES
The DS1644 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1646P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS - READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1646 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1646 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.
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BLOCK DIAGRAM DS1646 Figure 1
TRUTH TABLE DS1646 Table 1
VCC CE OE WE MODE DQ POWER
VIH X X DESELECT HIGH-Z STANDBY
X X X DESELECT HIGH-Z STANDBY
VIL X VIL WRITE DATA IN ACTIVE
VIL VIL VIH READ DATA OUT ACTIVE
5 VOLTS ± 10%
VIL VIH VIH READ HIGH-Z ACTIVE
<4.5 VOLTS >VBAT X X X DESELECT HIGH-Z CMOS STANDBY
<VBAT X X X DESELECT HIGH-Z DATA RETENTION
MODE
SETTING THE CLOCK
The 8th bit of the control register is the write bit. Setting the write bit to a 1, like the read bit halts updates
to the DS1646 registers. The user can then load them with the correct day, date and time data in 24-hour
BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and
allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the second’s registers. Setting it
to a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the second’s register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e., CE low, OE low, and address for seconds register remain valid and stable).
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CLOCK ACCURACY (DIP MODULE)
The DS1646 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1646P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 PPM) at 25°C.
DS1646 REGISTER MAP - BANK1 Table 2
DATA
ADDRESS B7B6B5B4B3B2B1B0FUNCTION
1FFF -------- YEAR 00-99
1FFE XXX -----MONTH 01-12
1FFD X X ------ DATE 01-31
1FFC XFT XXX --- DAY 01-07
1FFB X X ------ HOUR 00-23
1FFA X-------MINUTES 00-59
1FF9 OSC -------SECONDS 00-59
1FF8 WRXXXXXXCONTROL A
OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = UNUSED
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1646 is in the read mode whenever WE (write enable) is high; CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NVSRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip-enable access (t CEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1646 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE and CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of t
WR prior to the initiation of
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for t
DH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
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DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5 volts) the DS1646 can be accessed as described above with
read or write cycles. However, when V
CC is below the power-fail point V
PF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal (PFO) will be
driven active low and will remain active until V
CC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the V
CC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until V
CC is returned to nominal
level.
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -20°C to +70°C
Soldering Temperature 260°C for 10 seconds (See Note 7)
*This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70 °C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage VCC 4.5 5.0 5.5 V1
Logic 1 Voltage All Inputs VIH 2.2 VCC+0.3 V
Logic 0 Voltage All Inputs VIL -0.3 0.8 V
DC ELECTRICAL CHARACTERISTICS (0°C ≤ tA ≤ 70°C; VCC=5.0V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Average VCC Power Supply Current ICC1 85 mA 2, 3
TTL Standby Current ( CE =VIH)ICC2 3 6 mA 2, 3
CMOS Standby Current
(CE =VCC-0.2V) ICC3 2 4.0 mA 2, 3
Input Leakage Current (any input) IIL -1 +1 µA
Output Leakage Current IOL -1 +1 µA
Output Logic 1 Voltage
(IOUT = -1.0 mA) VOH 2.4 V
Output Logic 0 Voltage
(IOUT = +2.1 mA) VOL 0.4 V
Write Protection Voltage VPF 4.0 4.25 4.5 V
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AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ± 10%)
DS1251Y-120 DS1251Y-150
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time tRC 120 150 ns
Address Access Time tAA 120 150 ns
CE Access Time tCEA 120 150 ns
CE Data Off Time tCEZ 40 50 ns
Output Enable Access Time tOEA 100 120 ns
Output Enable Data Off Time tOEZ 40 50 ns
Output Enable to DQ Low-Z tOEL 5 5 ns
CE to DQ Low-Z tCEL 5 5 ns
Output Hold from Address tOH 5 5 ns
Write Cycle Time tWC 120 150 ns
Address Setup Time tAS 0 0 ns
CE Pulse Width tCEW 100 120 ns
Address Hold from End of Write tAH1
tAH2
5
30 5
30 ns
ns 5
6
Write Pulse Width tWEW 75 90 ns
WE Data Off Time tWEZ 40 50 ns
WE or CE Inactive Time tWR 10 10 ns
Data Setup Time tDS 85 110 ns
Data Hold Time High tDH1
tDH2
0
25 0
25 ns
ns 5
6
AC TEST CONDITIONS
Input Levels: 0V to 3V
Transition Times: 5 ns
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Capacitance on all pins (except DQ) CI7pF
Capacitance on DQ pins CDQ 10 pF
AC ELECTRICAL CHARACTERISTICS
(POWER-UP/DOWN TIMING) (0°C to 70 °C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE or WE at VIH before Power-Down tPD 0µs
VPF (Max) to VPF (Min) VCC Fall Time tF300 µs
VPF (Min) to VSO VCC Fall Time tFB 10 µs
VSO to VPF (Min) VCC Rise Time tRB 1µs
VPF (Min) to VPF (Max) VCC Rise Time tR0µs
Power-Up tREC 15 25 35 ms
Expected Data Retention Time
(Oscillator On) tDR 10 years 4
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DS1646 READ CYCLE TIMING
DS1646 WRITE CYCLE TIMING
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POWER-DOWN/POWER-UP TIMING
NOTES:
1. All voltages are referenced to ground.
2. Typical values are at 25°C and nominal
supplies.
3. Outputs are open.
4. Data retention time is at 25°C and is
calculated from the date code on the device
package. The date code XXYY is the year
followed by the week of the year in which
the device was manufactured. For example,
9225 would mean the 25th week of 1992.
OUTPUT LOAD
5. tAH1, tDH1 are measured from WE going high.
6. tAH2, tDH2 are measured from CE going high.
7. Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperatures as long as temperature exposure to the lithium energy source
contained within does not exceed +85°C. Post-solder cleaning with water washing techniques is
acceptable, provided that ultrasonic vibration is not used.
In addition, for the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live-bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3
seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the
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part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove
solder.
DS1646 32-PIN PACKAGE
PKG 28-PIN
DIM MIN MAX
A IN.
MM 1.670
38.42 1.690
38.93
B IN.
MM 0.715
18.16 0.740
18.80
C IN.
MM 0.335
8.51 0.365
9.27
D IN.
MM 0.075
1.91 0.105
2.67
E IN.
MM 0.015
0.38 0.030
0.76
F IN.
MM 0.140
3.56 0.180
4.57
G IN.
MM 0.090
2.29 0.110
2.79
H IN.
MM 0.590
14.99 0.630
16.00
J IN.
MM 0.010
0.25 0.018
0.45
K IN.
MM 0.015
0.38 0.025
0.64
DS1646P
PKG INCHES
DIM MIN NOM MAX
A0.920 0.925 0.930
B0.980 0.985 0.990
C- - 0.080
D0.052 0.055 0.058
E0.048 0.050 0.052
F0.015 0.020 0.025
G0.025 0.027 0.030
NOTE: For the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live - bug”).
b. Hand Soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3
seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the
part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove
solder.
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DS1646P WITH DS9034PCX ATTACHED
PKG INCHES
DIM MIN NOM MAX
A0.920 0.925 0.930
B0.955 0.960 0.965
C0.240 0.245 0.250
D0.052 0.055 0.058
E0.048 0.050 0.052
F0.015 0.020 0.025
G0.020 0.025 0.030
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG INCHES
DIM MIN NOM MAX
A-1.050 -
B-0.826 -
C-0.050 -
D-0.030 -
E-0.112 -
