LTC1983-3/LTC1983-5
1
1983fa
The LTC
®
1983-3 and LTC1983-5 are inverting charge
pump DC/DC converters that produce negative regulated
outputs. The parts require only three tiny external capaci-
tors and can provide up to 100mA of output current. The
devices can operate in open loop mode (creating a –V
IN
supply) or regulated output mode depending on the input
supply voltage and the output current.
The LTC1983-3/LTC1983-5 have many useful features for
portable applications including very low quiescent current
(25µA typical) and a zero current shutdown mode pro-
grammed through the SHDN pin.
The LTC1983-3/LTC1983-5 are over-temperature and
short-circuit protected. The parts are available in a 6-pin
low profile (1mm) ThinSOT package.
■
–3V Generation in Single-Supply Systems
■
Portable Equipment
■
LCD Bias Supplies
■
GaAs FET Bias Supplies
■
Fixed Output Voltages: –3V, –5V or Low Noise V
IN
to –V
IN
Inverted Output
■
±4% Output Voltage Accuracy
■
Low Quiesient Current: 25µA
■
100mA Output Current Capability
■
2.3V to 5.5V Operating Voltage Range
■
Internal 900kHz Oscillator
■
“Zero Current” Shutdown
■
Short-Circuit and Over-Temperature Protected
■
Low Profile (1mm) ThinSOT
TM
Package
100mA Regulated
Charge-Pump Inverters
in ThinSOT
VIN
SHDN
C+
VOUT
GND
C–
LTC1983-3
VIN
3V TO 5.5V
VOUT = –3V
IOUT = UP TO 100mA
COUT
10µF
CIN
10µF
CFLY
1µF
OFF ON
CFLY: TAIYO YUDEN LMK212BJ105
CIN, COUT: TAIYO YUDEN JMK316BJ106ML
1983-3 TA01
VOUT vs IOUT
IOUT (mA)
0
VOUT (V)
–3.3
–3.2
–3.1
–3.0
–2.9
–2.8
–2.7 20 40 60 80
1983 TA02
100
VIN = 5V
VIN = 3.3V
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
–3V at 100mA DC/DC Converter
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC1983-3/LTC1983-5
2
1983fa
V
IN
to GND................................................... –0.3V to 6V
SHDN Voltage .............................................. –0.3V to 6V
V
OUT
to GND (LTC1983-3) .................. 0.2V to V
OUT
Max
V
OUT
to GND (LTC1983-5) .................. 0.2V to V
OUT
Max
I
OUT
Max ............................................................. 125mA
Output Short-Circuit Duration .......................... Indefinite
Operating Temperature Range (Note 2) ...–40°C to 85°C
Storage Temperature Range ................. – 65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
S6 PART
MARKING
T
JMAX
= 125°C, θ
JA
= 256°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTPC
LTYB
LTC1983ES6-3
LTC1983ES6-5
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
ELECTRICAL CHARACTERISTICS
Burst Mode is a registered trademark of Linear Technology Corporation.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, CFLY = 1µF, COUT = 10µF unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Operating Voltage (Regulated Output Mode) (LTC1983-3) ●3.0 5.5 V
(LTC1983-5) 5.0 5.5 V
V
IN
Minimum Startup Voltage 2.3 V
V
OUT
(LTC1983-3) V
IN
≥ 3.3V, I
OUT
≤ 25mA ●–2.88 –3 –3.12 V
V
IN
≥ 5V, I
OUT
≤ 100mA ●–2.88 –3 –3.12 V
V
OUT
(LTC1983-5) V
IN
≥ 5V, V
IN
–5V ≥ I
OUT
• R
OUT
●– 4.8 –5 –5.2 V
V
IN
Operating Current V
IN
≤ 5.5V, I
OUT
= 0µA, SHDN = V
IN
●25 60 µA
V
IN
Operating Current (Open-Loop Mode) (LTC1983-5) V
IN
= 3.3V 2.5 mA
V
IN
= 4.75V 4 mA
V
IN
Shutdown Current SHDN = 0V, V
IN
≤ 5.5V ●0.1 1 µA
Output Ripple 3.3 ≤ V
IN
≤ 5.5 60 mV
P-P
Open-Loop Output Impedance (LTC1983-3): R
OUT
V
IN
= 3.3V, V
OUT
= –3V 11 Ω
Open-Loop Output Impedance (LTC1983-5): R
OUT
V
IN
= 3.3V, I
OUT
≈ 50mA 11 Ω
V
IN
= 5V, I
OUT
≈ 60mA 8.5 Ω
Oscillator Frequency (Non Burst Mode® Operation) 900 kHz
SHDN Input High ●1.1 V
SHDN Input Low ●0.3 V
SHDN Input Current V
SHDN
= 5.5V ●2.2 4 µA
VCC 1
VOUT 2
C+ 3
6 SHDN
5 GND
4 C–
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC SOT-23
Note 2: The LTC1983E-3/LTC1983E-5 are guaranteed to meet
performance specifications from 0°C to 70°C. Specifications over the
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls.
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC1983-3/LTC1983-5
3
1983fa
Output Impedance vs
Input Voltage
Output Impedance
vs IOUT (LTC1983-5)
Efficiency vs IOUT (LTC1983-5)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Efficiency vs IOUT
IOUT (mA)
0
EFFICIENCY (%)
40 80 100
90
80
70
60
50
40
30
20
10
0
1983 G01
20 60
VIN = 2.3V VIN = 3.3V
VIN = 5V
TA = 25°C
VIN (V)
2.35
ROUT (Ω)
4.35
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
1983 TA02
3.35 5.35
ROUT
IOUT = 25mA
TA = 25°C
IOUT (mA)
0
ROUT (Ω)
40 80 100
30
25
20
15
10
5
1983 G03
20 60
VIN = 2.3V
VIN = 3.3V
VIN = 5V
TA = 25°C
IOUT (mA)
0.01
100
75
50
25
010
1983 GO4
0.1 1 100
EFFICIENCY (%)
VIN = 5V
VIN = 3.3V
VOUT = –3V
TA = 25°C
OUTPUT CURRENT (mA)
0
–2.1
–2.3
–2.5
–2.7
–2.9
–3.1
–3.3
–3.5 60 100
1983 G05
20 40 80 120
VOUT (V)
120°C
–40°C, 0°C, 40°C
80°C
OUTPUT CURRENT (mA)
0
2.7
VOUT (–V)
2.8
2.9
3.0
3.1
3.3
20 40 60 80
1983 G06
100 120
3.2
–40°C0°C
40°C
80°C
VIN = 5V
–3VOUT vs IOUT Over Temperature
–3VOUT vs IOUT Over Temperature
(VIN = 5V)
Open-Loop Current
vs Temperature (LTC1983-5)
TEMPERATURE (°C)
–40
4.9
4.7
4.5
4.3
4.1
3.9
3.7
3.5
1983 G07
10 60 110
IIN (mA)
VIN = 5V
Burst Mode Current
vs Temperature (LTC1983-3)
TEMPERATURE (°C)
–40
IIN (µA)
25
30
35
1983 G08
20
15
10 10 60
40
45
50
110
VIN = 5V
Open-Loop Input Current
vs VIN (LTC1983-5)
VIN (V)
2.3
1.5
IIN (mA)
2.0
2.5
3.0
3.5
4.5
2.8 3.3 3.3 4.3
1983 G09
4.8
4.0
TA = 25°C
LTC1983-3/LTC1983-5
4
1983fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Burst Mode Input Current
vs VIN (LTC1983-3)
VIN (V)
3.1
26.5
INPUT CURRENT (µA)
27.0
28.0
28.5
29.0
4.1 5.1 5.5
31.0
1983 G10
27.5
3.6 4.6
29.5
30.0
30.5
TA = 25°C
TEMPERATURE (°C)
–50
ROUT (Ω)
10
12
14
150
1983 G11
8
6
0050 100
4
2
18
16
VIN = 5V
VIN = 3V
IOUT = 10mA
TEMPERATURE (°C)
–50
0
VTHRESHOLD (V)
0.1
0.3
0.4
0.5
1.0
0.7
050
1983 G12
0.2
0.8
0.9
0.6
100 150
ROUT vs Temperature
(IOUT = 10mA)
SHDN Pin Threshold Voltage
vs Temperature
SHDN Pin Input Current
vs Temperature ROUT vs CFLY (VIN = 5V)
TEMPERATURE (°C)
–50
2.0
2.5
3.5
100
1983 G13
1.5
1.0
0 50 150
0.5
0
3.0
I
SHDN
(µA)
CFLY (µF)
0.01
1400 VIN = 5V
TA = 25°C
1200
1000
800
600
400
200
1983 G14
0.1 1
0
ROUT (Ω)
VOUT Start-Up into 100mA
Resistive Load
VOUT Ripple at 100mA Load VOUT Ripple at 30mA Load
VOUT Load Step Reponse from
IOUT = 0 to IOUT = 100mA
V
OUT
1V
V
IN
5V
V
OUT
20mV
50µs/DIV 1983 G15
1µs/DIV 1983 G16
V
OUT
20mV
2.5µs/DIV 1983 G17
V
OUT
20mV
100µs/DIV 1983 G18
I
OUT
100mA
LTC1983-3/LTC1983-5
5
1983fa
UU
U
PI FU CTIO S
V
IN
(Pin 1): Charge Pump Input Voltage. May be between
2.3V and 5.5V. V
IN
should be bypassed with a ≥4.7µF low
ESR capacitor as close as possible to the pin for best
performance.
V
OUT
(Pin 2): Regulated Output Voltage for the IC. V
OUT
should be bypassed with a ≥4.7µF low ESR capacitor as
close as possible to the pin for best performance.
C
+
(Pin 3): Charge Pump Flying Capacitor Positive Termi-
nal. This node is switched between V
IN
and GND (It is
connected to V
CC
during shutdown).
C
–
(Pin 4): Charge Pump Flying Capacitor Negative Termi-
nal. This node is switched between GND and V
OUT
(It is
connected to GND during shutdown).
GND (Pin 5): Signal and Power Ground for the 6-Pin
SOT-23 package. This pin should be tied to a ground plane
for best performance.
SHDN (Pin 6): Shutdown. Grounding this pin shuts down
the IC. Tie to V
IN
to enable. This pin should not be pulled
above the V
IN
voltage or below GND.
BLOCK DIAGRA
W
CONTROL
LOGIC
CLOCK2
CLOCK1
S1A
S2A
S1B
S2B
–
+
VREF
CHARGE PUMP
SHDN
VIN
CIN
10µF
CFLY
1µF
COUT
10µF
LTC1983-X
C+
C–
VOUT
COMP1
1µA
1983 BD
LTC1983-3/LTC1983-5
6
1983fa
OPERATIO
U
The LTC1983-3/LTC1983-5 use a switched capacitor
charge pump to invert a positive input voltage to a regu-
lated –3V ±4% (LTC1983-3) or –5 ±4% (LTC1983-5)
output voltage. Regulation is achieved by sensing the
output voltage through an internal resistor divider and
enabling the charge pump when the output voltage droops
above the upper trip point of COMP1. When the charge
pump is enabled, a 2-phase, nonoverlapping clock con-
trols the charge pump switches. Clock 1 closes the S1
switches which enables the flying capacitor to charge up
to the V
IN
voltage. Clock 2 closes the S2 switches that
invert the V
IN
voltage and connect the bottom plate of C
FLY
to the output capacitor at V
OUT
. This sequence of charging
and discharging continues at a free-running frequency of
900kHz (typ) until the output voltage has been pumped
down to the lower trip point of COMP1 and the charge
pump is disabled. When the charge pump is disabled, the
LTC1983 draws only 25µA (typ) from V
IN
which provides
high efficiency at low load conditions.
In shutdown mode, all circuitry is turned off and the part
draws less than 1µA from the V
IN
supply. V
OUT
is also
disconnected from V
IN
and C
FLY
. The SHDN pin has a
threshold of approximately 0.7V. The part enters shut-
down when a low is applied to the SHDN pin. The SHDN pin
should not be floated; it must be driven with a logic high
or low.
Open-Loop Operation
The LTC1983-3/LTC1983-5 inverting charge pumps regu-
late at –3V/–5V respectively, unless the input voltage is too
low or the output current is too high. The equations for
output voltage regulation are as follows:
V
IN
–5.06V > I
OUT
• R
OUT
(LTC1983-5)
V
IN
–3.06V > I
OUT
• R
OUT
(LTC1983-3)
If this condition is not met, then the part will run in open
loop mode and act as a low output impedance inverter for
which the output voltage will be:
V
OUT
= –[V
IN
–(I
OUT
• R
OUT
)]
For all R
OUT
values, check the corresponding curves in
the Typical Performance Characteristics section (Note:
C
FLY
= 1µF for all R
OUT
curves). The R
OUT
value will be
different for different flying caps, as shown in the follow-
ing equation:
Short-Circuit/Thermal Protection
During short-circuit conditions, the LTC1983 will draw
several hundred milliamps from V
IN
causing a rise in the
junction temperature. On-chip thermal shutdown cir-
cuitry disables the charge pump once the junction tem-
perature exceeds ≈155°C, and reenables the charge pump
once the junction temperature falls back to ≈145°C. The
LTC1983 will cycle in and out of thermal shutdown
indefinitely without latchup or damage until the V
OUT
short is removed.
Capacitor Selection
For best performance, it is recommended that low ESR
capacitors be used for both C
IN
and C
OUT
to reduce noise
and ripple. The C
IN
and C
OUT
capacitors should be either
ceramic or tantalum and should be 4.7µF or greater.
Aluminum electrolytic are not recommended because of
their high equivalent series resistance (ESR). If the source
impedance is very low, C
IN
may not be needed. Increasing
the size of C
OUT
to 10µF or greater will reduce output
voltage ripple. The flying capacitor and C
OUT
should also
have low equivalent series inductance (ESL). The board
layout is critical as well for inductance for the same reason
(the suggested board layout should be used).
A ceramic capacitor is recommended for the flying capaci-
tor with a value in the range of 0.1µF to 4.7µF. Note that
a large value flying cap (>1µF) will increase output ripple
unless C
OUT
is also increased. For very low load applica-
tions, C1 may be reduced to 0.01µF to 0.047µF. This will
reduce output ripple at the expense of efficiency and
maximum output current.
(Refer to Block Diagram)
LTC1983-3/LTC1983-5
7
1983fa
There are many aspects of the capacitors that must be
taken into account. First, the temperature stability of the
dielectric is a main concern. For ceramic capacitors, a
three character code specifies the temperature stability
(e.g. X7R, Y5V, etc.). The first two characters represent
the temperature range that the capacitor is specified and
the third represents the absolute tolerance that the ca-
pacitor is specified to over that temperature range. The
ceramic capacitor used for the flying and output capaci-
tors should be X5R or better. Second, the voltage coef-
ficient of capacitance for the capacitor must be checked
and the actual value usually needs to be derated for the
operating voltage (the actual value has to be larger than
the value needed to take into account the loss of capaci-
tance due to voltage bias across the capacitor). Third, the
frequency characteristics need to be taken into account
because capacitance goes down as the frequency of
oscillation goes up. Typically, the manufacturers have
capacitance vs frequency curves for their products. This
curve must be referenced to be sure the capacitance will
not be too small for the application. Finally, the capacitor
ESR and ESL must be low for reasons mentioned in the
following section.
Output Ripple
Normal LTC1983 operation produces voltage ripple on the
V
OUT
pin. Output voltage ripple is required for the LTC1983
to regulate. Low frequency ripple exists due to the hyster-
esis in the sense comparator and propagation delays in the
charge pump enable/disable circuits. High frequency ripple
is also present mainly due to ESR of the output capacitor.
Typical output ripple under maximum load is 60mV
P-P
with a low ESR 10µF output capacitor. The magnitude of
the ripple voltage depends on several factors. High input
voltage to negative output voltage differentials [(V
IN
+
V
OUT
) >1V] increase the output ripple since more charge
is delivered to C
OUT
per clock cycle. A large flying capacitor
(>1µF) also increases ripple for the same reason. Large
output current load and/or a small output capacitor (<10µF)
results in higher ripple due to higher output voltage dV/dt.
High ESR capacitors (ESR > 0.1Ω) on the output pin cause
high frequency voltage spikes on V
OUT
with every clock
cycle.
There are several ways to reduce the output voltage ripple.
A larger C
OUT
capacitor (22µF or greater) will reduce both
the low and high frequency ripple due to the lower C
OUT
charging and discharging dV/dt and the lower ESR typi-
cally found with higher value (larger case size) capacitors.
A low ESR ceramic output capacitor will minimize the high
frequency ripple, but will not reduce the low frequency
ripple unless a high capacitance value is chosen. A reason-
able compromise is to use a 10µF to 22µF tantalum
capacitor in parallel with a 1µF to 4.7µF ceramic capacitor
on V
OUT
to reduce both the low and high frequency ripple.
However, the best solution is to use 10µF to 22µF, X5R
ceramic capacitors which are available in 1206 package
sizes. An RC filter may also be used to reduce high
frequency voltage spikes (see Figure 1).
In low load or high V
IN
applications, smaller values for
C
FLY
may be used to reduce output ripple. A smaller flying
capacitor (0.01µF to 0.047µF) delivers less charge per
clock cycle to the output capacitor resulting in lower
output ripple. However, the smaller value flying caps also
reduce the maximum I
OUT
capability as well as efficiency.
Figure 1. Output Ripple Reduction Techniques
VOUT VOUT
LTC1983-X
10µF
TANTALUM
10µF
TANTALUM
VOUT VOUT
LTC1983-X
15µF
TANTALUM
1µF
CERAMIC
3.9Ω
1983 F01
OPERATIO
U
(Refer to Block Diagram)
LTC1983-3/LTC1983-5
8
1983fa
Inrush Currents
During normal operation, V
IN
will experience current tran-
sients in the several hundred milliamp range whenever the
charge pump is enabled. During start-up, these inrush
currents may approach 1 to 2 amps. For this reason, it is
important to minimize the source resistance between the
input supply and the V
IN
pin. Too much source resistance
may result in regulation problems or even prevent start-
up. One way that this can be avoided (especially when the
source impedance can’t be lowered due to system con-
straints) is to use a large V
IN
capacitor with low ESR right
at the V
IN
pin. If ceramic capacitors are used, you may
need to add 1µF to 10µF tantalum capacitor in parallel to
limit input voltage transients. Input voltage transients will
occur if V
IN
is applied via a switch or a plug. One example
of this situation is in USB applications.
Ultralow Quiescent Current Regulated Supply
The LTC1983 contains an internal resistor divider (refer to
the Block Diagram) that draws only 1µA (typ for the 3V
version) from V
OUT
during normal operation. During shut-
down, the resistor divider is disconnected from the output
and the part draws only leakage current from the output.
During no-load conditions, applying a 1Hz to 100Hz, 2%
to 5% duty cycle signal to the SHDN pin ensures that the
circuit of Figure 2 comes out of shutdown frequently
enough to maintain regulation even under low-load condi-
tions. Since the part spends nearly all of its time in
shutdown, the no-load quiescent current is essentially
zero. However, the part will still be in operation during the
time the SHDN pin is high, so the current will not be zero
and can be calculated using the following equations to
determine the approximate maximum current: I
IN(MAX)
=
[(Time out of shutdown) • (Burst Mode operation quies-
cent current) + (Normal operating I
IN
) • (Time output is
being charged before the LTC1983 enters Burst Mode
operation)]/(Period of SHDN signal). This number will be
highly dependent on the amount of board leakage current
and how many devices are connected to V
OUT
(each will
draw some leakage current) and must be calculated and
verified for each different board design.
The LTC1983 must be out of shutdown for a minimum
duration of 200µs to allow enough time to sense the output
and keep it in regulation. A 1Hz, 2% duty cycle signal will
keep V
OUT
in regulation under no-load conditions. Even
though the term no-load is used, there will always be board
leakage current and leakage current drawn by anything
connected to V
OUT
. This is why it is necessary to wake the
part up every once in a while to verify regulation. As the
V
OUT
load current increases, the frequency with which the
part is taken out of shutdown must also be increased to
prevent V
OUT
from drooping below the – 2.88V (for the 3V
version) during the OFF phase (see Figure 3). A 100Hz, 2%
duty cycle signal on the SHDN pin ensures proper regula-
tion with load currents as high as 100µA. When load
current greater than 100µA is needed, the SHDN pin must
be forced high as in normal operation.
Each time the LTC1983 comes out of shutdown, the part
delivers a minimum of one clock cycle worth of charge to
the output. Under high V
IN
(>4V) and/or low I
OUT
(<10µA)
conditions, this behavior may cause a net excess of charge
to be delivered to the output capacitor if a high frequency
signal is used on the SHDN pin (e.g., 50Hz to 100Hz).
Under such conditions, V
OUT
will slowly drift positive and
may even go out of regulation. To avoid this potential
Figure 2. Ultralow Quiescent Current Regulated Supply
VIN
GND
C+
SHDN
VOUT
C–
LTC1983-3
CFLY
1µF
CERAMIC
FROM MPU
SHDN
VIN
CIN
10µF
TANTALUM COUT
10µF
CERAMIC
SHDN PIN WAVEFORMS:
LOW IQ MODE
(IOUT ≤ 100µA)
VOUT LOAD ENABLE MODE
(IOUT = 100µA TO 100mA)
(1Hz TO 100Hz, 2% TO 5% DUTY CYCLE)
–3V ± 4%
1983 F02
3.3V TO 5.5V
OPERATIO
U
(Refer to Block Diagram)
LTC1983-3/LTC1983-5
9
1983fa
problem in the low I
Q
mode, it is necessary to switch the
part in and out of shutdown at the minimum allowable
frequency (refer to Figure 3) for a given output load.
General Layout Considerations
Due to the high switching frequency and high transient
currents produced by the LTC1983, careful board layout is
a must. A clean board layout using a ground plane and
short connections to all capacitors will improve perfor-
mance and ensure proper regulation under all conditions
(refer to Figures 4a and 4b). You will not get advertised
performance with careless layout. Figure 3
OUTPUT CURRENT (µA)
1
10
100
1000
MAXIMUM SHDN OFF TIME (ms)
1000
1983 F03b
1 10 100
SHDN ON PULSE WIDTH = 200µs
COUT = 10µF
Figure 4a. Recommended Component
Placement for a Single Layer Board
Figure 4b. Recommended Component
Placement for a Double Layer Board
1 VIN
2 VOUT
3 C+
SHDN 6
GND 5
C– 4
COUT
CFLY
VIN: 2.3V TO 5.5V
VOUT
1983 F04a
CIN
1 VIN
2 VOUT
3 C+
SHDN 6
GND 5
C– 4
CIN
COUT
CFLY
VOUT
1983 F04b
BOTTOM LAYER TOP LAYER
OPERATIO
U
(Refer to Block Diagram)
LTC1983-3/LTC1983-5
10
1983fa
TYPICAL APPLICATIO S
U
VIN
SHDN
C+
VOUT
GND
C–
LTC1983-5
VIN
2.5V TO 5.5V
VOUT
–VIN
10µF
10µF
CERAMIC
1µF
CERAMIC
OFF ON
1983 TA04
VIN
SHDN
C+
VOUT
GND
C–
LTC1983-5
VIN
2.5V
VOUT
–2.5V
1µF
CERAMIC
4.7µF
CERAMIC
0.47µF
CERAMIC
OFF ON
1983 TA03
2.5V to –2.5V DC/DC Converter
100mA Inverting DC/DC Converter
LTC1983-3/LTC1983-5
11
1983fa
PACKAGE DESCRIPTIO
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S6 Package
6-Lead Plastic SOT-23
(Reference LTC DWG # 05-08-1636)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302 REV B
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
LTC1983-3/LTC1983-5
12
1983fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002
LT/LWI 0606 REV A • PRINTED IN USA
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= 10mA (V
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OUT
= 80mA, Output Noise = 60µV
RMS
LTC1751/-3.3/-5 Doubler Charge Pumps V
OUT
=5V at 100mA; V
OUT
=3.3V at 80mA; ADJ; MSOP Packages
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Q
= 13µA; I
OUT
= 50mA
LTC1928-5 Doubler Charge Pump with Low Noise LDO ThinSOT Output Noise = 60µV
RMS
; V
OUT
= 5V; V
IN
= 2.7V to 4V
LTC3200 Constant Frequency Doubler Charge Pump Low Noise, 5V Output or Adjustable
Combined Unregulated Doubler
and Regulated Inverter
U
TYPICAL APPLICATIO
C+C–
LTC1983-3/
LTC1983-5
CFLY
1µF
CERAMIC
CBOOST
1µF
OFF ON
COUT2
10µF
CERAMIC
COUT1
10µF
CERAMIC
CIN
10µF
CERAMIC
1983 TA05
VIN
VIN VOUT VOUT
SHDN GND
D1
D2
VBOOST
VBOOST = 2VIN –2(VD)
