PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA,
AUDIO DIGITAL-TO-ANALOG CONVERTER
FEATURES
D24-Bit Resolution
DAnalog Performance (VCC = 5 V):
− Dynamic Range: 106 dB
− SNR: 106 dB, Typical
− THD+N: 0.002%, Typical
− Full-Scale Output: 4 VPP
, Typical
D4×/8× Oversampling Digital Filter:
− Stop-Band Attenuation: –50 dB
− Pass-Band Ripple: ±0.04 dB
DSampling Frequency: 5 kHz to 200 kHz
DSystem Clock: 128 fS, 192 fS, 256 fS, 384 fS,
512 fS, 768 fS, 1152 fS with Auto Detect
DSoftware Control (PCM1753, PCM1755):
− Accepts 16-, 18-, 20-, and 24-Bit Audio
Formats: Standard, I2S, and Left-Justified
− Digital Attenuation: 0 dB to –63 dB,
0.5 dB/Step
− Digital De-Emphasis
− Digital Filter Rolloff: Sharp or Slow
− Soft Mute
− Zero Flags for Each Output
− Open-Drain Output Zero Flag (PCM1755)
DHardware Control (PCM1754):
− I2S and 16-Bit Word, Right-Justified
− 44.1 kHz Digital De-Emphasis
− Soft Mute
− Zero Flag for L-, R-Channel Common
Output
DPower Supply: 5-V Single Supply
DSmall 16-Lead SSOP Package, Lead-Free
APPLICATIONS
DA/V Receivers
DDVD Movie Players
DDVD Add-On Cards for High-End PCs
DDVD Audio Players
DHDTV Receivers
DCar Audio Systems
DOther Applications Requiring 24-Bit Audio
DESCRIPTION
The PCM1753/54/55 is a CMOS, monolithic, integrated
circuit, which includes stereo digital-to-analog converters
and support circuitry in a small 16-lead SSOP package.
The data converters use TI’s enhanced multilevel
delta-sigma architecture, which employs 4th-order noise
shaping and 8-level amplitude quantization to achieve
excellent dynamic performance and improved tolerance to
clock jitter. The PCM1753/54/55 accepts industry-
standard audio data formats with 16- to 24-bit data,
providing easy interfacing to audio DSP and decoder
chips. Sampling rates up to 200 kHz are supported. A full
set of user-programmable functions is accessible through
a three-wire serial control port, which supports register
write functions.
The PCM1753/55 is pin-compatible with the PCM1748,
PCM1742, and PCM1741, except for pin 5.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Burr-Brown Audio
Copyright © 2003−2009, Texas Instruments Incorporated
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
2
PACKAGE/ORDERING INFORMATION(1)
PRODUCT PACKAGE PACKAGE
CODE
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER TRANSPORT MEDIA
PCM1753DBQ
16 pin SSOP
16DBQ
25°C to 85°C
PCM1753
PCM1753DBQ Tube
PCM1753DBQ 16-pin SSOP 16DBQ –25°C to 85°C PCM1753 PCM1753DBQR Tape and reel
PCM1754DBQ
16 pin SSOP
16DBQ
40°C to 85°C
PCM1754
PCM1754DBQ Tube
PCM1754DBQ 16-pin SSOP 16DBQ –40°C to 85°C PCM1754 PCM1754DBQR Tape and reel
PCM1755DBQ
16 pin SSOP
16DBQ
25°C to 85°C
PCM1755
PCM1755DBQ Tube
PCM1755DBQ 16-pin SSOP 16DBQ –25°C to 85°C PCM1755 PCM1755DBQR Tape and reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this ducoument, or see the TI website
at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range unless otherwise noted.
UNIT
Supply voltage: VCC –0.3 V to 6.5 V
Ground voltage differences: AGND, DGND ±0.1 V
Input voltage –0.3 V to 6.5 V
Input current (any pins except supplies) ±10 mA
Ambient temperature under bias –40°C to 125°C
Storage temperature –55°C to 150°C
Junction temperature 150°C
Lead temperature (soldering) 260°C, 5 s
Package temperature (IR reflow, peak) 260°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted.
PARAMETER TEST CONDITIONS
PCM1753DBQ, PCM1754DBQ,
PCM1755DBQ UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
Resolution 24 Bits
DATA FORMAT
Audio-data interface format
PCM1753
PCM1755 Standard, I2S, left-justified
Audio data interface format
PCM1754 I2S, standard
Audio-data bit len
g
th
PCM1753
PCM1755 16-, 18-, 20-, 24-bit, selectable
Audio data bit length
PCM1754 16–24-bit (I2S), 16-bit (standard)
Audio data format MSB first, 2s complement
fSSampling frequency 5 200 kHz
System clock frequency 128 fS, 192 fS, 256 fS, 384 fS,
512 fS, 768 fS, 1152 fS
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
3
ELECTRICAL CHARACTERISTICS (CONTINUED)
All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted.
PARAMETER TEST CONDITIONS
PCM1753DBQ, PCM1754DBQ,
PCM1755DBQ UNIT
PARAMETER
MIN TYP MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic family TTL compatible
VIH
Input logic level
2
VDC
VIL
Input logic level 0.8 VDC
IIH(1) VIN = VCC 10
IIL(1)
Input logic current
VIN = 0 V –10
μA
IIH(2) Input logic current VIN = VCC 65 100 μA
IIL(2) VIN = 0 V –10
VOH(3)
Output logic level
IOH = –1 mA 2.4
VDC
VOL(4) Output logic level IOL = 1 mA 0.4 VDC
DYNAMIC PERFORMANCE (5) (6)
fS = 44.1 kHz 0.002% 0.006%
THD+N at VOUT = 0 dB fS = 96 kHz 0.003%
THD+N at VOUT 0 dB
fS = 192 kHz 0.004%
fS = 44.1 kHz 0.65%
THD+N at VOUT = –60 dB fS = 96 kHz 0.8%
THD+N at VOUT 60 dB
fS = 192 kHz 0.95%
EIAJ, A-weighted, fS = 44.1 kHz 100 106
Dynamic range A-weighted, fS = 96 kHz 104 dB
Dynamic range
A-weighted, fS = 192 kHz 102
dB
EIAJ, A-weighted, fS = 44.1 kHz 100 106
Signal-to-noise ratio A-weighted, fS = 96 kHz 104 dB
Signal to noise ratio
A-weighted, fS = 192 kHz 102
dB
fS = 44.1 kHz 97 103
Channel separation fS = 96 kHz 101 dB
Channel separation
fS = 192 kHz 100
dB
Level linearity error VOUT = –90 dB ±0.5 dB
DC ACCURACY
Gain error ±1±6% of FSR
Gain mismatch, channel-to-channel ±1±3% of FSR
Bipolar zero error VOUT = 0.5 VCC at BPZ ±30 ±60 mV
ANALOG OUTPUT
Output voltage Full scale (0 dB) 80% of VCC VPP
Center voltage 50% of VCC VDC
Load impedance AC-coupled load 5 kΩ
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS (SHARP ROLLOFF)
Pass band ±0.04 dB 0.454
fS
Stop band 0.546 fs
Pass-band ripple ±0.04 dB
Stop-band attenuation Stop band = 0.546 fS–50 dB
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
4
ELECTRICAL CHARACTERISTICS (CONTINUED)
All specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS and 24-bit data, unless otherwise noted.
PARAMETER TEST CONDITIONS
PCM1753DBQ, PCM1754DBQ,
PCM1755DBQ UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
FILTER CHARACTERISTICS (SLOW ROLLOFF, PCM1753/PCM1755)
Pass band ±0.5 dB 0.198 fs
Stop band 0.884 fs
Pass-band ripple ±0.5 dB
Stop-band attenuation Stop band = 0.884 fS–35 dB
Delay time 18/fss
De-emphasis error ±0.1 dB
ANALOG FILTER PERFORMANCE
Frequency response
At 20 kHz –0.03 dB
Frequency response At 44 kHz –0.20 dB
POWER SUPPLY REQUIREMENTS (6)
VCC Voltage range 4.5 5 5.5 VDC
fS = 44.1 kHz 16 21
ICC Supply current fS = 96 kHz 25 mA
ICC
Supply current
fS = 192 kHz 30
mA
fS = 44.1 kHz 80 105
Power dissipation fS = 96 kHz 125 mW
Power dissipation
fS = 192 kHz 150
mW
TEMPERATURE RANGE
Operation temperature
PCM1753
PCM1755 –25 85 °C
Operation temperature
PCM1754 –40 85 °C
θJA Thermal resistance 16-pin SSOP 115 °C/W
(1) Pins 16, 1, 2, 3: SCK, BCK, DATA, LRCK.
(2) Pins 13–15: MD, MC, ML (PCM1753/PCM1755). Pins 12–15: TEST, DEMP, MUTE, FMT (PCM1754).
(3) Pins 11, 12: ZEROR, ZEROL (PCM1753). Pin 11: ZEROA (PCM1754).
(4) Pins 11, 12: ZEROR, ZEROL (PCM1753/PCM1755). Pin 11: ZEROA (PCM1754).
(5) Analog performance specifications are measured using the System Twot Cascade audio measurement system by Audio Precisiont in the
averaging mode.
(6) Conditions in 192-kHz operation are system clock = 128 fS and oversampling rate = 64 fS of register 18.
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
5
PIN ASSIGNMENTS
SCK
ML
MC
MD
ZEROL/NA
ZEROR/ZEROA
VCOM
AGND
16
15
14
13
12
11
10
9
BCK
DATA
LRCK
DGND
NC
VCC
VOUTL
VOUTR
PCM1753/PCM1755
(TOP VIEW)
1
2
3
4
5
6
7
8
SCK
FMT
MUTE
DEMP
TEST
ZEROA
VCOM
AGND
16
15
14
13
12
11
10
9
BCK
DATA
LRCK
DGND
NC
VCC
VOUTL
VOUTR
PCM1754
(TOP VIEW)
1
2
3
4
5
6
7
8
FUNCTIONAL BLOCK DIAGRAM
Power Supply
DGND
Enhanced
Multilevel
Delta-Sigma
Modulator
VOUTL
4y/8y
Oversampling
Digital
Filter
and
Function
Control
Audio
Serial
Port
BCK
LRCK
DATA
Serial
Control
Port
Zero Detect
(TEST)
SCK System
Clock
Manager
(MUTE) MC
(FMT) ML
Output Amp
and
Low-Pass Filter
(DEMP) MD
DAC
VCOM
System Clock
AGND
VCC
ZEROR/ZEROA(1)
(ZEROA)
ZEROL/NA(1)
Output Amp
and
Low-Pass Filter
DAC
VOUTR
(1) Open-Drain Output for the PCM1755
NOTE: Pin names in (parentheses) are valid for the PCM1754 only.
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
6
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
PCM1753/PCM1755
AGND 9 – Analog ground
BCK 1 I Audio data bit clock input
DATA 2 I Audio data digital input
DGND 4 – Digital ground
LRCK 3 I L-channel and R-channel audio data latch enable input
MC 14 I Mode control clock input(1)
MD 13 I Mode control data input (1)
ML 15 I Mode control latch input (1)
NC 5 –
SCK 16 I System clock input
VCC 6 – Analog power supply, 5 V
VCOM 10 – Common voltage decoupling
VOUTL 7 O Analog output for L-channel
VOUTR 8 O Analog output for R-channel
ZEROR/ZEROA 11 OZero flag output for R-channel/Zero flag output for L-/R-channels (2)
ZEROL/NA 12 O Zero flag output for L-channel/Not assigned (2)
PCM1754
AGND 9 – Analog ground
BCK 1 I Audio-data bit-clock input
DATA 2 I Audio-data digital input
DEMP 13 I De-emphasis control (1)
DGND 4 – Digital ground
FMT 15 I Data format select (1)
LRCK 3 I L-channel and R-channel audio data latch enable input
MUTE 14 I Analog mixing control (1)
NC 5 –
SCK 16 I System clock input
TEST 12 I Test pin. Ground or open (1)
VCC 6 – Analog power supply, 5 V
VCOM 10 – Common voltage decoupling
VOUTL 7 O Analog output for L-channel
VOUTR 8 O Analog output for R-channel
ZEROA 11 OZero flag output for L/R channels
(1) Schmitt-trigger input with internal pulldown.
(2) Open-drain output (PCM1755).
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
7
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER (DE-EMPHASIS OFF)
Figure 1. Frequency Response, Sharp Rolloff
Frequency [× fS]
−140
−120
−100
−80
−60
−40
−20
0
01234
Amplitude – dB
AMPLITUDE
vs
FREQUENCY
Figure 2. Pass-Band Ripple, Sharp Rolloff
Frequency [× fS]
−0.05
−0.04
−0.03
−0.02
−0.01
0.00
0.01
0.02
0.03
0.04
0.05
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude – dB
AMPLITUDE
vs
FREQUENCY
Figure 3. Frequency Response, Slow Rolloff
Frequency [× fS]
−140
−120
−100
−80
−60
−40
−20
0
01234
Amplitude – dB
AMPLITUDE
vs
FREQUENCY
Frequency [× fS]
−5
−4
−3
−2
−1
0
1
2
3
4
5
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude – dB
AMPLITUDE
vs
FREQUENCY
Figure 4. Transition Characteristics,
Slow Rolloff
All specifications at TA = 25_C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, unless otherwise noted
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
8
DE-EMPHASIS CURVES
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
02468101214
Figure 5
f – Frequency – kHz
De-emphasis Level – dB
DE-EMPHASIS LEVEL
vs
FREQUENCY
fS = 32 kHz
f – Frequency – kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14
DE-EMPHASIS ERROR
vs
FREQUENCY
De-emphasis Error – dB
fS = 32 kHz
Figure 6
f – Frequency – kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
02468101214161820
De-emphasis Level – dB
DE-EMPHASIS LEVEL
vs
FREQUENCY
fS = 44.1 kHz
Figure 7
f – Frequency – kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 101214161820
DE-EMPHASIS ERROR
vs
FREQUENCY
De-emphasis Error – dB
fS = 44.1 kHz
Figure 8
All specifications at TA = 25_C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, unless otherwise noted
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
9
DE-EMPHASIS CURVES (CONTINUED)
f – Frequency – kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10121416182022
De-emphasis Level – dB
DE-EMPHASIS LEVEL
vs
FREQUENCY
fS = 48 kHz
Figure 9
f – Frequency – kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10121416182022
DE-EMPHASIS ERROR
vs
FREQUENCY
De-emphasis Error – dB
fS = 48 kHz
Figure 10
All specifications at TA = 25_C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, unless otherwise noted
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
10
ANALOG DYNAMIC PERFORMANCE (SUPPLY VOLTAGE CHARACTERISTICS)
4.0 4.5 5.0 5.5 6.0
VCC – Supply Voltage – V
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
10
0.1
0.01
0.001
0.0001
THD+N – Total Harmonic Distortion + Noise – %
1
Figure 11
44.1 kHz, 384 fS
–60 dB
0 dB
96 kHz, 384 fS
192 kHz, 128 fS
96 kHz, 384 fS
44.1 kHz, 384 fS
192 kHz, 128 fS
VCC – Supply Voltage – V
96
98
100
102
104
106
108
110
4.0 4.5 5.0 5.5 6.0
Dynamic Range – dB
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
44.1 kHz, 384 fS
192 kHz, 128 fS
96 kHz, 384 fS
Figure 12
VCC – Supply Voltage – V
96
98
100
102
104
106
108
110
4.0 4.5 5.0 5.5 6.0
SNR – Signal-to-Noise Ratio – dB
SIGNAL-to-NOISE RATIO
vs
SUPPLY VOLTAGE
44.1 kHz, 384 fS
192 kHz, 128 fS
96 kHz, 384 fS
Figure 13
VCC – Supply Voltage – V
96
98
100
102
104
106
108
110
4.0 4.5 5.0 5.5 6.0
Channel Separation – dB
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
44.1 kHz, 384 fS
192 kHz, 128 fS
96 kHz, 384 fS
Figure 14
All specifications at TA = 25_C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, unless otherwise noted
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
11
ANALOG DYNAMIC PERFORMANCE (TEMPERATURE CHARACTERISTICS)
−50 −25 0 25 50 75 100
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
10
0.1
0.01
0.001
0.0001
THD+N – Total Harmonic Distortion + Noise – %
1
–60 dB
0 dB
Figure 15
TA – Free-Air Temperature – °C
192 kHz, 128 fS
96 kHz, 384 fS
192 kHz, 128 fS
96 kHz, 384 fS
44.1 kHz, 384 fS
44.1 kHz, 384 fS
TA – Free-Air Temperature – °C
96
98
100
102
104
106
108
110
−50 −25 0 25 50 75 100
Dynamic Range – dB
DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
44.1 kHz, 384 fS
192 kHz, 128 fS
96 kHz, 384 fS
Figure 16
TA – Free-Air Temperature – °C
96
98
100
102
104
106
108
110
−50 −25 0 25 50 75 100
SNR – Signal-to-Noise Ratio – dB
SIGNAL-to-NOISE RATIO
vs
FREE-AIR TEMPERATURE
44.1 kHz, 384 fS
192 kHz, 128 fS
96 kHz, 384 fS
Figure 17
TA – Free-Air Temperature – °C
96
98
100
102
104
106
108
110
−50 −25 0 25 50 75 100
Channel Separation – dB
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
44.1 kHz, 384 fS
192 kHz, 128 fS
Figure 18
96 kHz, 384 fS
All specifications at TA = 25_C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data, unless otherwise noted
–25°C to 85°C for the PCM1753/55, –40°C to 85°C for the PCM1754
.
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
12
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The PCM1753/54/55 requires a system clock for operating the digital interpolation filters and multilevel
delta-sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 shows examples of
system clock frequencies for common audio sampling rates.
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important
to use a clock source with low phase-jitter and noise. TI’s PLL170x family of multiclock generators is an excellent
choice for providing the PCM1753/54/55 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
SAMPLING FREQUENCY 128 fS192 fS256 fS384 fS512 fS768 fS1152 fS
8 kHz 1.0240 1.5360 2.0480 3.0720 4.0960 6.1440 9.2160
16 kHz 2.0480 3.0720 4.0960 6.1440 8.1920 12.2880 18.4320
32 kHz 4.0960 6.1440 8.1920 12.2880 16.3840 24.5760 36.8640
44.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 (1)
48 kHz 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 (1)
88.2 kHz 11.2896 16.9344 22.5792 33.8688 45.1584 (1) (1)
96 kHz 12.2880 18.4320 24.5760 36.8640 49.1520 (1) (1)
192 kHz 24.5760 36.8640 (1) (1) (1) (1) (1)
(1) This system clock rate is not supported for the given sampling frequency.
t(SCKH)
t(SCY)
System Clock (SCK)
t(SCKL)
2.0 V
0.8 V
H
L
PARAMETERS SYMBOL MIN TYP MAX UNITS
System clock pulse duration, high t(SCKH) 7 ns
System clock pulse duration, low t(SCKL) 7 ns
System clock pulse cycle time t(SCY) (1) ns
(1) 1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS
Figure 19. System Clock Input Timing
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
13
Power-On Reset Functions
The PCM1753/54/55 includes a power-on reset function. Figure 20 shows the operation of this function. With
the system clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The
initialization sequence requires 1024 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V). After the
initialization period, the PCM1753/55 is set to its reset default state, as described in the Mode Control Registers
section of this data sheet.
During the reset period (1024 system clocks), the analog output is forced to the bipolar zero level, or VCC/2.
After the reset period, an internal register is initialized in the next 1/fS period and if SCK, BCK, and LRCK are
provided continuously, the PCM1753/54/55 provides proper analog output with unit group delay against the
input data.
Reset Reset Removal
1024 System Clocks
VCC
3.7 V (Max)
3.0 V (Typ)
2.2 V (Min)
Internal Reset
System Clock
Don’t Care
Figure 20. Power-On Reset Timing
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
14
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1753/54/55 consists of a 3-wire synchronous serial port. It includes LRCK
(pin 3), BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit clock, and it is used to clock the serial data
present on DATA into the serial shift register of the audio interface. Serial data is clocked into the
PCM1753/54/55 on the rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial
data into the internal registers of the serial audio interface.
Both LRCK and BCK should be synchronous to the system clock. Ideally, it is recommended that LRCK and
BCK be derived from the system clock input, SCK. LRCK is operated at the sampling frequency, fS. BCK can
be operated at 32, 48, or 64 times the sampling frequency for standard (right-justified) format, and 32 times the
sampling frequency of BCK is limited to 16-bit right-justified format only. BCK can be operated at 48 or 64 times
the sampling frequency for the I2S and left-justified formats. 48 times the sampling frequency of BCK is limited
to 192/384/768 fS SCKI.
Internal operation of the PCM1753/54/55 is synchronized with LRCK. Accordingly, internal operation is held
when the sampling rate clock of LRCK is changed or when SCK and/or BCK is interrupted for a 3-bit clock cycle
or longer. If SCK, BCK, and LRCK are provided continuously after this held condition, the internal operation is
re-synchronized automatically in a period of less than 3/fS. External resetting is not required.
Audio Data Formats and Timing
The PCM1753/55 supports industry-standard audio data formats, including right-justified, I2S, and left-justified.
The PCM1754 supports I2S and 16-bit-word right-justified. The data formats are shown in Figure 22. Data
formats are selected using the format bits, FMT[2:0], located in control register 20 of the PCM1753/55, and
are selected using the FMT pin on the PCM1754. The default data format is 24-bit left-justified. All formats
require binary 2s-complement, MSB-first audio data. Figure 21 shows a detailed timing diagram for the serial
audio interface.
DATA
t(BCH)
1.4 V
BCK
LRCK
t(BCL) t(LB)
t(BCY)
t(DS) t(DH)
1.4 V
1.4 V
t(BL)
PARAMETERS SYMBOL MIN MAX UNITS
BCK pulse cycle time t(BCY) 1/(32 fS), 1/(48 fS),
1/(64 fS) (1)
BCK high-level time t(BCH) 35 ns
BCK low-level time t(BCL) 35 ns
BCK rising edge to LRCK edge t(BL) 10 ns
LRCK falling edge to BCK rising edge t(LB) 10 ns
DATA setup time t(DS) 10 ns
DATA hold time t(DH) 10 ns
(1) fS is the sampling frequency (e.g., 44.1 kHZ, 48 kHz, 96 kHz, etc.).
Figure 21. Audio Interface Timing
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LRCK
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
MSB LSB
1/fS
(= 32 fS, 48 fS, or 64 fS)
18-Bit Right-Justified, BCK = 48 fS or 64 fS
1/fS
(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW
(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
MSB LSB
20-Bit Right-Justified, BCK = 48 fS or 64 fS
MSB LSB
24-Bit Right-Justified, BCK = 48 fS or 64 fS
1/fS
(= 48 fS or 64 fS)
(= 48 fS, or 64 fS)
MSB LSB
16-Bit Right-Justified, BCK = 32 fS
16-Bit Right-Justified, BCK = 48 fS or 64 fS
MSB LSB
L-Channel R-Channel
BCK
DATA 14 15 16 123 14 15 16
14 15 16 123 14 15 16
16 17 18
DATA
DATA
DATA
DATA
123 16 17 18
18 19 20 123 18 19 20
22 23 24 123
MSB LSB
MSB LSB
MSB LSB
MSB LSB
123 14 15 16
123 14 15 16
123 16 17 18
123 18 19 20
22 23 24
MSB LSB
123 22 23 24
L-Channel R-ChannelLRCK
BCK
DATA 123 12
MSB
N–2 N
N–1
LSB
123
MSB
N–2 N
N–1
LSB
L-Channel R-Channel
LRCK
BCK
DATA 123 N–2 N
N–1 123 N–2 N
N–1 12
MSB LSB LSBMSB
Figure 22. Audio Data Input Formats
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ZERO FLAGS (PCM1753/55)
Zero-Detect Condition
Zero detection for either output channel is independent from the other channel. If the data for a given channel
remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that
channel.
Zero Flag Outputs
If a zero-detect condition exists for one or more channels, the zero flag pins for those channels are set to a logic
1 state. There are zero flag pins for each channel, ZEROL (pin 12) and ZEROR (pin 11). These pins can be
used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor,
or other digitally controlled function.
The active polarity of zero flag outputs can be inverted by setting the ZREV bit of control register 22 to 1. The
reset default is active-high output, or ZREV = 0.
The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register
22 to 1. The reset default is independent zero flags for L-channel and R-channel, or AZRO = 0.
In the case of the PCM1755, ZEROL and ZEROR are open-drain outputs.
ZERO FLAG (PCM1754)
The PCM1754 has a ZERO flag pin, ZEROA (pin 11). ZEROA is the L-channel and R-channel common zero
flag pin. If the data for L-channel and R-channel remains at a 0 level for 1024 sampling periods (or LRCK clock
periods), ZEROA is set to a logic 1 state.
HARDWARE CONTROL (PCM1754)
The digital functions of the PCM1754 are capable of hardware control. Table 2 shows selectable formats,
Table 3 shows de-emphasis control, and Table 4 shows mute control.
Table 2. Data Format Select
FMT (PIN 15) DATA FORMAT
LOW 16- to 24-bit, I2S format
HIGH 16-bit right-justified
Table 3. De-Emphasis Control
DEMP (PIN 13) DE-EMPHASIS FUNCTION
LOW 44.1 kHz de-emphasis OFF
HIGH 44.1 kHz de-emphasis ON
Table 4. Mute Control
MUTE (PIN 14) MUTE
LOW Mute OFF
HIGH Mute ON
OVERSAMPLING RATE CONTROL (PCM1754)
The PCM1754 automatically controls the oversampling rate of the delta-sigma D/A converters with the system
clock rate. The oversampling rate is set to 64× oversampling with every system clock and sampling frequency.
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SOFTWARE CONTROL (PCM1753/55)
The PCM1753/55 has many programmable functions which can be controlled in the software control mode. The
functions are controlled by programming the internal registers using ML, MC, and MD.
The serial control interface is a 3-wire serial port, which operates asynchronously to the audio serial interface.
The serial control interface is used to program the on-chip mode registers. The control interface includes MD
(pin 13), MC (pin 14), and ML (pin 15). MD is the serial data input, used to program the mode registers. MC
is the serial bit clock, used to shift data into the control port. ML is the control port latch clock.
Register Write Operation
All write operations for the serial control port use 16-bit data words. Figure 23 shows the control data word
format. The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index
(or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the
register specified by IDX[6:0].
Figure 24 shows the functional timing diagram for writing to the serial control port. ML is held at a logic 1 state
until a register needs to be written. To start the register write cycle, ML is set to logic 0. Sixteen clocks are then
provided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle
has completed, ML is set to logic 1 to latch the data into the indexed mode control register.
MSB LSB
Register Index (or Address) Register Data
0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D4D5 D3 D2 D1 D0
Figure 23. Control Data Word Format for MD
IDX0 D7 D6 D4D5 D3 D2 D1 D00
ML
MC
MD X 0 IDX6
X
IDX1IDX2IDX3IDX4IDX5IDX6
X
Figure 24. Register Write Operation
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Control Interface Timing Requirements
Figure 25 shows a detailed timing diagram for the serial control interface. These timing parameters are critical
for proper control port operation.
t(MCH)
ML
t(MLS)
LSB
t(MCL)
t(MHH)
t(MLH)
t(MCY)
t(MDH)
t(MDS)
MC
MD
PARAMETERS SYMBOL MIN TYP MAX UNITS
MC pulse cycle time t(MCY) 100 ns
MC low-level time t(MCL) 50 ns
MC high-level time t(MCH) 50 ns
ML high-level time t(MHH) (2) ns
ML falling edge to MC rising edge t(MLS) 20 ns
ML hold time (1) t(MLH) 20 ns
MD hold time t(MDH) 15 ns
MD setup time t(MDS) 20 ns
(1) MC rising edge for LSB to ML rising edge.
(2) 3
256 fS
sec (min); fS: sampling rate
Figure 25. Control Interface Timing
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MODE CONTROL REGISTERS (PCM1753/55)
User-Programmable Mode Controls
The PCM1753/55 includes a number of user programmable functions, which are accessed via control registers.
The registers are programmed using the serial control interface, which was previously discussed in this data
sheet. Table 5 lists the available mode control functions, along with their reset default conditions and associated
register index.
Register Map
The mode control register map is shown in Table 6. Each register includes an index (or address) indicated by
the IDX[6:0] bits.
Table 5. User-Programmable Mode Controls
FUNCTION RESET DEFAULT REGISTER BIT(s)
Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps 0 dB, no attenuation 16 and 17 AT1[7:0], AT2[7:0]
Soft mute control Mute disabled 18 MUT[2:0]
Oversampling rate control (64 fS or 128 fS)64 fS oversampling 18 OVER
Soft reset control Reset disabled 18 SRST
DAC operation control DAC1 and DAC2 enabled 19 DAC[2:1]
De-emphasis function control De-emphasis disabled 19 DM12
De-emphasis sample rate selection 44.1 kHz 19 DMF[1:0]
Audio data format control 24-bit left-justified 20 FMT[2:0]
Digital filter rolloff control Sharp rolloff 20 FLT
Zero flag function select L-, R-channel independent 22 AZRO
Output phase select Normal phase 22 DREV
Zero flag polarity select High 22 ZREV
Table 6. Mode Control Register Map
IDX
(B8–B14) REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
10h Register 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
11h Register 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
12h Register 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST OVER RSV RSV RSV RSV MUT2 MUT1
13h Register 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1
14h Register 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0
16h Register 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV AZRO ZREV DREV
NOTE:RSV: Reserved for test operation. It should be set to 0 for regular operation.
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Register Definitions
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
ATx[7:0]: Digital Attenuation Level Setting
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
Default value: 1111 1111b
Each DAC channel (VOUTL and VOUTR) includes a digital attenuation function. The attenuation level can be
set from 0 dB to –63 dB in 0.5-dB steps. Changes in attenuator levels are made by incrementing or
decrementing one step (0.5 dB) for every 8/fS time internal until the programmed attenuator setting is reached.
Alternatively, the attenuation level can be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. The attenuation level is set using the following
formula:
Attenuation level (dB) = 0.5 × (ATx[7:0]DEC – 255)
where ATx[7:0]DEC = 0 through 255.
For ATx[7:0]DEC = 0 through 128, attenuation is set to infinite attenuation.
The following table shows the attenuation levels for various settings:
ATx[7:0] DECIMAL VALUE ATTENUATION LEVEL SETTING
1111 1111b 255 0 dB, No Attenuation. (default)
1111 1110b 254 –0.5 dB
1111 1101b 253 –1.0 dB
LLL
1000 0011b 131 –62.0 dB
1000 0010b 130 –62.5 dB
1000 0001b 129 –63.0 dB
1000 0000b 128 Mute
LLL
0000 0000B0 Mute
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST OVER RSV RSV RSV RSV MUT2 MUT1
MUTx: Soft Mute Control
where x = 1 or 2, corresponding to the DAC outputs VOUT L (x = 1) and VOUTR (x = 2).
Default value: 0
MUTx = 0 Mute disabled (default)
MUTx = 1 Mute enabled
The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding
DAC outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute
is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1,
the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation,
one attenuator step (0.5 dB) for every 8/fS seconds. This provides pop-free muting of the DAC output.
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By setting MUTx = 0, the attenuator is increased one step for every 8/fS seconds to the previously programmed
attenuation level.
OVER: Oversampling Rate Control
Default value: 0
System clock rate = 256 fS, 384 fS, 512 fS, 768 fS, or 1152 fS:
OVER = 0 64× oversampling (default)
OVER = 1 128× oversampling
System clock rate = 128 fS or 192 fS:
OVER = 0 32× oversampling (default)
OVER = 1 64× oversampling
The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters. The OVER = 1 setting
is recommended when the sampling rate is 192 kHz (system clock rate is 128 fS or 192 fS).
SRST: Reset
Default value: 0
SRST = 0 Reset disabled (default)
SRST = 1 Reset enabled
The SRST bit is used to enable or disable the soft reset function. The operation is the same as power-on reset.
All registers are initialized.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1
DACx: DAC Operation Control
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2).
Default value: 0
DACx = 0 DAC operation enabled (default)
DACx = 1 DAC operation disabled
The DAC operation controls are used to enable and disable the DAC outputs, VOUTL and VOUTR. When
DACx = 0, the corresponding output generates the audio waveform dictated by the data present on the DATA
pin. When DACx = 1, the corresponding output is set to the bipolar zero level, or 0.5 VCC.
DM12: Digital De-Emphasis Function Control
Default value: 0
DM12 = 0 De-emphasis disabled (default)
DM12 = 1 De-emphasis enabled
The DM12 bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical
Performance Curves section of this data sheet.
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DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
Default value: 00
The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when
it is enabled.
DMF[1:0] De-Emphasis Sample Rate Selection
00 44.1 kHz (default)
01 48 kHz
10 32 kHz
11 Reserved
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0
FMT[2:0]: Audio Interface Data Format
Default value: 101
The FMT[2:0] bits are used to select the data format for the serial audio interface. The following table shows
the available format options.
FMT[2:0] Audio Data Format Selection
000 24-bit standard format, right-justified data
001 20-bit standard format, right-justified data
010 18-bit standard format, right-justified data
011 16-bit standard format, right-justified data
100 16- to 24-bit I2S format
101 16- to 24-bit left-justified format (default)
110 Reserved
111 Reserved
FLT: Digital Filter Rolloff Control
Default value: 0
FLT = 0 Sharp rolloff (default)
FLT = 1 Slow rolloff
The FLT bit allows the user to select the digital filter rolloff that is best suited to the application. Two filter rolloff
selections are available, sharp and slow. The filter responses for these selections are shown in the Typical
Performance Curves section of this data sheet.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV AZRO ZREV DREV
DREV: Output Phase Select
Default value: 0
DREV = 0 Normal output (default)
DREV = 1 Inverted output
The DREV bit is the output analog signal phase control.
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ZREV: Zero Flag Polarity Select
Default value: 01h
ZREV = 0 High on zero flag pins indicates a zero detect (default)
ZREV = 1 Low on zero flag pins indicates a zero detect
The ZREV bit allows the user to select the polarity of zero flag pins.
AZRO: Zero Flag Function Select
Default value: 0
AZRO = 0 L-/R-channel independent zero flags (default)
AZRO = 1 L-/R-channel common zero flag
The AZRO bit allows the user to select the function of zero flag pins.
AZRO = 0: Pin 11: ZEROR, zero flag output for R-channel
Pin 12: ZEROL, zero flag output for L-channel
AZRO = 1: Pin 11: ZEROA, zero flag output for L-/R-channels
Pin 12: NA, not assigned
ANALOG OUTPUTS
The PCM1753/54/55 includes two independent output channels, VOUTL and VOUTR. These are unbalanced
outputs, each capable of driving 4 VPP typical into a 5-kΩ ac-coupled load. The internal output amplifiers for
VOUTL and VOUTR are biased to the dc common-mode (or bipolar zero) voltage, equal to 0.5 VCC.
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise shaping characteristics of the PCM1753/54/55 delta-sigma D/A
converters. The frequency response of this filter is shown in Figure 26. By itself, this filter is not enough to
attenuate the out-of-band noise to an acceptable level for many applications. An external low-pass filter is
required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is
provided in the Applications Information section of this data sheet.
−60
−50
−40
−30
−20
−10
0
10
f – Frequency – kHz
Level – dB
LEVEL
vs
FREQUENCY
0.1 100 1k 10k1 10
Figure 26. Output Filter Frequency Response
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VCOM Output
One unbuffered common-mode voltage output pin, VCOM (pin 10) is brought out for decoupling purposes. This
pin is nominally biased to a dc voltage level equal to 0.5 VCC. This pin can be used to bias external circuits.
Figure 27 shows an example of using the VCOM pin for external biasing applications.
–
–
VCOM
OPA337
+
10 μF
+
PCM1753/54/55
Buffered VCOM
VCC
VOUTX(1) 10 μF
+
PCM1753/54/55
AV+*1, where AV+*R2
R1
VCOM
(1) X = L or R
1/2
OPA2353
+
Filtered
Output
VCC
2
3
1
C1
R3
R2
C2
R1
10 μF
+
(a) Using VCOM to Bias a Single-Supply Filter Stage
(b) Using a Voltage Follower to Buffer VCOM When Biasing Multiple Nodes
Figure 27. Biasing External Circuits Using the VCOM Pin
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APPLICATION INFORMATION
CONNECTION DIAGRAMS
A basic connection diagram is shown in Figure 28, with the necessary power supply bypassing and decoupling
components. TI recommends using the component values shown in Figure 28 for all designs.
The use of series resistors (22 Ω to 100 Ω) is recommended for the SCK, LRCK, BCK, and DATA inputs. The
series resistor combines with the stray PCB and device input capacitance to form a low-pass filter, which
reduces high-frequency noise emissions and helps to dampen glitches and ringing present on clock and data
lines.
BCK 16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DATA
LRCK
DGND
NC
VCC
VOUTL
VOUTR
SCK
AGND
ML
MC
MD
ZEROL/NA
VCOM
ZEROR/ZEROA
10 μF
Register Control
Post LPF
10 μF
PCM1753
PCM1755
+5 V
+
L-Ch Out
PCM Audio Data
+
Post LPF
R-Ch Out
System Clock
Zero Mute Control
BCK 16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DATA
LRCK
DGND
NC
VCC
VOUTL
VOUTR
SCK
AGND
FMT
MUTE
DEMP
TEST
VCOM
ZEROA
10 μF
Post LPF
10 μF
PCM1754
+5 V
+
L-Ch Out
PCM Audio Data
+
Post LPF
R-Ch Out
System Clock
Zero Mute Control
Format
MUTE On/Off
DEMP On/Off
+ +
10 mF
10 mF
+ +
10 mF
10 mF
Figure 28. Basic Connection Diagram
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POWER SUPPLIES AND GROUNDING
The PCM1753/54/55 requires 5 V for VCC.
Proper power supply bypassing is shown in Figure 28. The 10-μF capacitors should be tantalum or aluminum
electrolytic.
D/A OUTPUT FILTER CIRCUITS
Delta-sigma D/A converters use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR)
performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2.
The out-of-band noise must be low-pass filtered in order to provide the optimal converter performance. This
is accomplished by a combination of on-chip and external low-pass filtering.
Figure 27(a) and Figure 29 show the recommended external low-pass active filter circuits for single- and
dual-supply applications. These circuits are 2nd-order Butterworth filters using the multiple feedback (MFB)
circuit arrangement, which reduces sensitivity to passive component variations over frequency and
temperature. For more information regarding MFB active filter design, see Burr-Brown applications bulletin
(SBAA055), available from the TI Web site at http://www.ti.com.
Because the overall system performance is defined by the quality of the D/A converters and their associated
analog output circuitry, high-quality audio operational amplifiers are recommended for the active filters. TI’s
OPA2353 and OPA2134 dual operational amplifiers are shown in Figure 27(a) and Figure 29, and are
recommended for use with the PCM1753/54/55.
–
2
3
1
OPA2134
+
VOUT
R4
C2
C1
R3
R2
R1
VIN
AV[*R2
R1
Figure 29. Dual-Supply Filter Circuit
PCB LAYOUT GUIDELINES
A typical PCB floor plan for the PCM1753/54/55 is shown in Figure 30. A ground plane is recommended, with
the analog and digital sections being isolated from one another using a split or cut in the circuit board. The
PCM1753/54/55 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short,
direct connections to the digital audio interface and control signals originating from the digital section of the
board.
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Digital Logic
and
Audio
Processor
Digital Power
+VDDGND
Digital Section Analog Section
Return Path for Digital Signals
Analog Power
+VS
AGND –VS
+5VA
Digital
Ground
Analog
Ground
Output
Circuits
PCM1753/54/55
AGND
VCC
DGND
Figure 30. Recommended PCB Layout
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the PCM1753/54/55. In cases where a common 5-V supply must be used for the
analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and
digital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 31
shows the recommended approach for single-supply applications.
VDD
Digital Section Analog Section
RF Choke or Ferrite Bead
Power Supplies
Common
Ground
Output
Circuits
AGND
VCC
+VS
+5V –VS
AGND
DGND
PCM1753/54/55
Figure 31. Single-Supply PCB Layout
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THEORY OF OPERATION
The delta-sigma section of the PCM1753/54/55 is based on an 8-level amplitude quantizer and a 4th-order
noise shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram
of the 8-level delta-sigma modulator is shown in Figure 32. This 8-level delta-sigma modulator has the
advantage of stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the interpolation filter is 64 fS.
The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 33 and
Figure 34. The enhanced multilevel delta-sigma architecture also has advantages for input clock jitter sensitivity
due to the multilevel quantizer, with the simulated jitter sensitivity shown in Figure 35.
KEY PERFORMANCE PARAMETERS AND MEASUREMENT
This section provides information on how to measure key dynamic performance parameters for the
PCM1753/54/55. In all cases, an Audio Precision System Two Cascade audio measurement system or
equivalent is used to perform the testing.
Total Harmonic Distortion + Noise
Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio D/A converters because it
takes into account both harmonic distortion and all noise sources within a specified measurement bandwidth.
The average value of the distortion and noise is referred to as THD+N.
For the PCM1753/54/55, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at
the input of the DAC. The digital generator is set to 24-bit audio word length and a sampling frequency of
44.1 kHz or 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the
measurement system. The S/PDIF data is transmitted via a coaxial cable to the digital audio receiver on the
DEM-DAI1753 demonstration board. The receiver is then configured to output 24-bit data in either I2S or
left-justified data format. The DAC audio interface format is programmed to match the receiver output format.
The analog output is then taken from the DAC post filter and connected to the analog analyzer input of the
measurement system. The analog input is band limited using filters resident in the analyzer. The resulting
THD+N is measured by the analyzer and displayed by the measurement system.
+
+
−
Z–1
+
++
+
+
+
8-Level Quantizer
−Z–1
IN
8 fS
OUT
64 fS
+
+Z–1
+
+Z–1
+
Figure 32. Eight-Level Delta-Sigma Modulator
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
29
Frequency [ fS]
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
012345678
AMPLITUDE
vs
FREQUENCY
Amplitude – dB
Figure 33. Quantization Noise Spectrum
( 64 Oversampling)
Frequency [ fS]
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
012345678
AMPLITUDE
vs
FREQUENCY
Amplitude – dB
Figure 34. Quantization Noise Spectrum
( 128 Oversampling)
Jitter - ps p-p
90
95
100
105
110
115
120
125
0 100 200 300 400 500 600
DYNAMIC RANGE
vs
JITTER
Dynamic Range – dB
Figure 35. Jitter Dependence
( 64 Oversampling)
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
30
Dynamic Range
Dynamic range is specified as A-weighted THD+N measured with a –60-dB full-scale, 1-kHz digital sine wave
stimulus at the input of the D/A converter. This measurement is designed to give a good indicator of how the
DAC performs given a low-level input signal.
The measurement setup for the dynamic range measurement is shown in Figure 37, and is similar to the
THD+N test setup discussed previously. The differences include the band limit filter selection, the additional
A-weighting filter, and the –60-dB full-scale input level.
S/PDIF
Receiver
Evaluation Board
DEM-DAI1753
PCM1753/54/55
2nd-Order
Low-Pass
Filter
AES17 Filter
Band Limit
Analyzer
and
Display
Digital
Generator
S/PDIF
Output 0 dB FS
(100% Full-Scale),
24-Bit,
1-kHz Sine Wave
Averaging
Mode
HPF = 400 Hz
LPF = 30 kHz
f–3 dB = 20.9 kHz
f–3 dB = 54 kHz or 108 kHz
Audio Precision System Two
Figure 36. Test Setup for THD+N Measurement
Idle Channel Signal-to-Noise Ratio
The SNR test provides a measure of the noise floor of the D/A converter. The input to the D/A is all-0s data,
and the dither function of the digital generator must be disabled to ensure an all-0s data stream at the input of
the D/A converter.
The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input
signal level.
(See the note provided in Figure 37).
PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
31
S/PDIF
Receiver
Evaluation Board
DEM-DAI1753
PCM1753/54/55
2nd-Order
Low-Pass
Filter
AES17 Filter
Band Limit
A-Weighting
Filter(1)
Analyzer
and
Display
Digital
Generator
S/PDIF
Output
0% Full-Scale,
Dither Off (SNR)
or –60 dB FS,
1 kHz Sine Wave
(Dynamic Range)
Averaging
Mode
HPF = 400 Hz
LPF = 30 kHz
f–3 dB = 20.9 kHz
f–3 dB = 54 kHz or 108 kHz
(1) Results without A-Weighting are approximately 3 dB worse.
Audio Precision System Two
Figure 37. Test Setup for Dynamic Range and SNR Measurement
Revision History
DATE REV PAGE SECTION DESCRIPTION
2/09 C
12 System Clock and Reset
Functions Changed value of 192 kHz at 256 fS from “49.1520” to note “(1)” in Table 1.
2/09
C
14 Audio Serial Interface Changed text.
NOTE:Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCM1753DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1753DBQG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1753DBQR ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1753DBQRG4 ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1754DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1754DBQG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1754DBQR ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1754DBQRG4 ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1755DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1755DBQG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1755DBQR ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM1755DBQRG4 ACTIVE SSOP DBQ 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF PCM1753, PCM1754 :
•Automotive: PCM1753-Q1, PCM1754-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1753DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PCM1754DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PCM1755DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1753DBQR SSOP DBQ 16 2000 367.0 367.0 35.0
PCM1754DBQR SSOP DBQ 16 2000 367.0 367.0 35.0
PCM1755DBQR SSOP DBQ 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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