Z9305/Z9309 Zero Delay Clock Buffer Preliminary Product Features * * * * Product Description Zero input-output propagation delay Output-output skew less than 250 ps Device-device skew less than 700 ps One input drives nine outputs, grouped as 4/4/1 (Z9309) 10 MHz to 150 MHz operating range, compatible with CPU and PCI bus frequencies Less than 200 ps cycle-cycle jitter, compatible with Pentium and Pentium Pro -based systems Test Mode to bypass PLL (Z9309) Available in space-saving 16 pin 150-mil SOIC and TSSOP package (Z9309), and 8 pin 150 Mil SOIC package (Z9305) * * * * Block Diagram (Z9305) REF PLL CLKOUT CLK1 CLK2 CLK3 CLK4 Block Diagram (Z9309) REF The Z9309 is a low cost 3.3V zero delay buffer designed to distribute high speed clocks in PC system devices and SDRAM modules and is available in a 16pin SOIC or TSSOP package. The Z9305 is an 8-pin version of the Z9309 and it accepts one reference input and drives out five low skew clocks. The devices have an on-chip PLL which locks to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The Z9309 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Table 1. If all output clocks are not required, Bank B can be tri-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The Z9305 and Z9309 PLLs enter a Power Down mode when there are no rising edges on the REF input. In this state, the outputs are tri-stated and the PLL is turned off, resulting in less than 50 uA of current draw. The Z9309 PLL shuts down in one additional case as shown in Table 1. Multiple Z9305 and Z9309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. CLKOUT All outputs have less than 200 ps of cycle-cycle jitter. The input to output propagation delay is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. CLKA1 CONNECTION DIAGRAM PLL CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 Rev.1.0 REF CLK2 CLK1 GND 1 2 3 4 Z9305 S1 Select Input Decoding Z9309 S2 8 7 6 5 11/4/1999 Page 1 of 9 CLKOUT CLK4 VDD CLK3 Z9305/Z9309 Zero Delay Clock Buffer Preliminary Pin Description (Z9305) PIN No. 1 2 3 4 5 6 7 8 Pin Name (1) REF (1) CLK2 (1) CLK1( GND (1) CLK3 VDD (1) CLK4 (1) CLKOUT I/O I O O I O O O Description Input reference frequency, 5.0 V tolerant input. Buffered Clock Output Buffered Clock Output Ground Buffered Clock Output 3.3V supply Buffered Clock Output Buffered clock output, internal feedback on this pin. Pin Description (Z9309) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name (1) REF (1) CLKA1 (1) CLKA2 VDD GND (1) CLKB1 (1) CLKB2 (2) S2 (2) S1 (1) CLKB3 (1) CLKB4 GND VDD (1) CLKA3 (1) CLKA4 (1) CLKOUT I/O I O O I I O O I I O O O O O Description Input reference frequency, 5.0 V tolerant input. Clock Output, Bank A. Clock Output, Bank A. 3.3 V Supply Ground Clock Output, Bank B. Clock Output, Bank B. Select Input pin, bit 2. Select Input pin, bit 1 Clock Output, Bank B. Clock Output, Bank B. Ground 3.3V supply Clock Output, Bank A. Clock Output, Bank A. Buffered output, internal feedback on this pin. Note 1: Includes weak pull down. Note 2: Includes weak pull up. Z9309 Select Input Functionality S2 0 S1 0 CLKA1-A4 Tri-State CLKB1-B4 Tri-State 0 1 Driven Tri-State 1 0 Driven 1 1 Driven CLK-OUT Driven [1] Output Source PLL PLL Shut-down N Driven PLL N Driven Driven REF Y Driven Driven PLL N Note 1: This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.s. Table 1 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.0 11/4/1999 Page 2 of 9 Z9305/Z9309 Zero Delay Clock Buffer Preliminary REF, Input T0 CLKA/CLKB Delay vs. Loading Difference Between CLKOUT & CLKA/CLKB Pins Ref - Input to CLKA/CLKB Delay (ps) 1500 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: CLKOUT Load - CLKA/CLKB Load (PF) Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs including CLKOUT must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs. If input to output delay adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs. For zero output-output skew, be sure to load all outputs equally. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev. 1.0 11/4/1999 Page 3 of 9 Z9305/Z9309 Zero Delay Clock Buffer Preliminary Maximum Ratings Voltage Relative to VSS: -0.3V Voltage Relative to VDD: 0.3V Storage Temperature: This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). 0C to + 125C Operating Temperature: 0C to +85C Maximum Power Supply: 7V DC Electrical Characteristics (Z9305/Z9309) (VDD = 3.0 to 3.6 V, TA = 0C to 85C) Characteristic (1) Input Low Voltage (1) Input High Voltage Symbol Min Typ VIL - - VIH 2.0 - Max 0.8 Units Conditions Vdc Vdc - Input Low Current IIL 50.0 A VIN = 0V Input High Current IIH 100 A VIN = VDD VOL 0.4 V IOL = 8 mA V IOH = - 8mA (2) Output Low Voltage (2) VOH 2.4 Tri-State leakage Current Ioz - - 10 A S1 = S2 = GND Power Down Supply Current Idd - - 50 A Ref = 0 MHz Dynamic Supply Current Idd - - 40 mA Unload outputs, 66.66 MHz, Select inputs at VDD or GND. Output High Voltage Notes: 1. REF and FBK inputs have a threshold voltage of VDD/2. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.0 11/4/1999 Page 4 of 9 Z9305/Z9309 Zero Delay Clock Buffer Preliminary Switching Characteristics (Z9305/Z9309) (VDD = 3.0 to 3.6 V, TA = 0C to 85C) Characteristic Symbol Output Period Input Period Duty Cycle (T2/T1) Rise Time (1) (1) Min (1) Units Conditions 150 MHz 30 pF load t1 10 150 MHz 30 pF load - 45 50 55 % Measured @ 1.4V - 1.5 nSec Measured between 0.8V & 2.0V, 15 pF Load 1.5 nSec Measured between 0.8V & 2.0V, 15 pF Load t4 Fall Time Max 10 t3 (1) Typ t1 t5 - - 250 pSec All output equally loaded t6 - 0 + 350 pSec Measured at VDD/2 Device to Device Skew t7 - 0 700 pSec Measured at VDD/2 on FBK pins of devices (1) tj - - 200 pSec Measured at 66.67 MHz, loaded outputs, input Trise/Fall < 1 nS 1.0 ms Stable power supply, valid clocks presented on REF pin. Output to Output Skew Delay, REF Rising Edge to (1) CLKOUT Rising Edge (1) Cycle to Cycle Jitter (1) Maximum PLL Lock Time tLOCK Notes: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev. 1.0 11/4/1999 Page 5 of 9 Z9305/Z9309 Zero Delay Clock Buffer Preliminary Test Circuit Diagrams VDD 0.1 uF Outputs CLK out C LOAD VDD 0.1 uF GND GND Test Circuit Package Drawing and Dimensions 8 Pin SOIC Narrow Outline Dimensions C INCHES L E SYMBOL H a D NOM MAX MIN NOM MAX A 0.061 0.064 0.068 1.55 1.63 1.73 A1 0.004 0.006 0.0098 0.127 0.150 0.250 A2 0.055 0.058 0.061 1.40 1.47 1.55 B 0.0138 0.016 0.0192 0.35 0.41 0.49 C 0.0075 0.008 0.0098 0.19 0.20 0.25 D 0.189 0.194 0.196 4.80 4.93 4.98 E 0.150 0.155 0.157 3.81 3.94 3.99 A2 A A1 e MILLIMETERS MIN B e 1.270 BSC H .230 .236 .244 5.84 5.99 6.20 h 0.010 0.013 0.016 0.25 0.33 0.41 0 5 8 0.41 0.64 0.89 a L INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 0.050 BSC 0 0.016 5 0.025 8 0.035 Rev.1.0 11/4/1999 Page 6 of 9 Z9305/Z9309 Zero Delay Clock Buffer Preliminary Package Drawing and Dimensions (16 Pin 150 Mil SOIC) 16 Pin 150 Mil SOIC Outline Dimensions INCHES SYMBOL C L H E MIN A2 A A1 B MAX MIN NOM MAX A 0.097 0.101 0.104 2.46 2.56 2.64 A1 0.0050 0.009 0.0115 0.127 0.22 0.29 A2 0.090 0.092 0.094 2.29 2.34 2.39 B 0.014 0.016 0.019 0.35 0.41 0.48 C 0.0091 0.010 0.0125 0.23 0.25 0.32 D 0.402 0.407 0.412 10.21 10.34 10.46 E 0.150 - 0.157 3.81 - 3.988 e a D NOM MILLIMETERS 0.050 BSC 1.27 BSC H 0.400 0.406 0.410 10.16 10.31 10.41 L 0.024 0.032 0.040 0.61 0.81 1.02 a 0 5 10 0 5 10 e INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev. 1.0 11/4/1999 Page 7 of 9 Z9305/Z9309 Zero Delay Clock Buffer Preliminary Package Drawing and Dimensions (Cont.) D R0.1 16 Pin TSSOP Dimensions INCHES SYMBOL E1 MIN MILLIMETERS NOM MAX MIN NOM MAX A - - 0.0433 - - 1.10 A1 0.0019 0.0039 0.0059 0.05 0.10 0.15 A2 0.0346 0.0354 0.0374 0.85 0.90 0.95 L 0.0196 0.0236 0.0275 0.50 0.60 0.75 L1 0.0354 0.0393 0.0433 0.90 1.00 1.10 R 0.0035 - - 0.09 - - b 0.0076 - 0.0108 0.195 - 0.275 b1 0.0076 0.0086 0.0096 0.195 0.22 0.245 c 0.0041 - 0.0068 0.105 - 0.175 c1 0.0041 0.0049 0.0057 0.105 0.125 0.145 0 - 8 0 - 8 BO 1.20 -B1.50 SURFACES ROUGHNESS: 6+ 27n(RZ) 4 [10 TYP R0.15 -C- 0.07 C B e e R0.15 14 TYP 1.0 0.05 MAX. 1.0 0.05 MAX. 0.026 BSC 0.65 BSC D 0.1948 0.1968 0.1988 4.95 5.0 5.05 E 0.2480 0.2519 0.2559 6.3 6.4 6.5 E1 0.1712 0.1732 0.1752 4.35 4.4 4.45 S 0.0078 - - 0.20 - - A E b .08 8 A C B A R A2 c c1 0.25 S L b1 A1 L1 DETAIL A DETAIL B INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.0 11/4/1999 Page 8 of 9 Z9305/Z9309 Zero Delay Clock Buffer Preliminary Ordering Information Part Number Package Type Production Flow Z9305BX 8 Pin SOIC Commercial, 0C to +85C Z9309BX 16 Pin SOIC Commercial, 0C to +85C Z9309BT 16 Pin TSSOP Commercial, 0C to +85C Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI Z9305BX Date Code, Lot # Z9305/Z9309BXB Flow Commercial, 0C to +85C Package X = SOIC, 150 Mil. T = TSSOP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev. 1.0 11/4/1999 Page 9 of 9