Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.0 11/4/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 1 of 9
Product Features
• Zero input-output propagation delay
• Output-output skew less than 250 ps
• Device-device skew less than 700 ps
• One input drives nine outputs, grouped as 4/4/1
(Z9309)
• 10 MHz to 150 MHz operating range, compatible
with CPU and PCI bus frequencies
• Less than 200 ps cycle-cycle jitter, compatible with
Pentium and Pentium Pro –based systems
• Test Mode to bypass PLL (Z9309)
• Available in space-saving 16 pin 150-mil SOIC and
TSSOP package (Z9309), and 8 pin 150 Mil SOIC
package (Z9305)
Block Diagram (Z9305)
PLL
REF
CLK1
CLK2
CLK3
CLK4
CLKOUT
Block Diagram (Z9309)
PLL
REF
CLKA1
Select Input
Decoding
S2
S1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
Product Description
The Z9309 is a low cost 3.3V zero delay buffer
designed to distribute high speed clocks in PC system
devices and SDRAM modules and is available in a 16-
pin SOIC or TSSOP package. The Z9305 is an 8-pin
version of the Z9309 and it accepts one reference input
and drives out five low skew clocks. The devices have
an on-chip PLL which locks to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
The Z9309 has two banks of four outputs each, which
can be controlled by the Select inputs as shown in the
Table 1. If all output clocks are not required, Bank B can
be tri-stated. The selec t inputs als o allow the input c lock
to be directly applied to the output for chip and system
testing purposes.
The Z9305 and Z9309 PLLs enter a Power Down m ode
when there are no rising edges on the REF input. In this
state, the outputs are tri-stated and the PLL is turned
off, resulting in less than 50 uA of current draw. The
Z9309 PLL shuts down in one additional case as shown
in Table 1.
Multiple Z9305 and Z9309 devices can acc ept the same
input clock and distribute it. In this case, the skew
between the outputs of two devices is guaranteed to be
less than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter.
The input to output propagation delay is guaranteed to
be less than 350 ps, and the output to output skew is
guaranteed to be less than 250 ps.
CONNECTION DIAGRAM
CLKOUT
CLK4
VDD
CLK3
1
2
3
4
8
7
6
5
REF
CLK2
CLK1
GND
Z9305
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
Z9309
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.0 11/4/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 2 of 9
Pin Description (Z9305)
PIN No. Pin Name I/O Description
1REF(1) I Input reference frequency, 5.0 V tolerant input.
2CLK2(1) O Buffered Clock Output
3CLK1((1) O Buffered Clock Output
4GND I Ground
5CLK3(1) O Buffered Clock Output
6VDD 3.3V supply
7CLK4(1) O Buffered Clock Output
8CLKOUT(1) O Buffered clock output, internal feedback on this pin.
Pin Description (Z9309)
PIN No. Pin Name I/O Description
1REF(1) I Input reference frequency, 5.0 V tolerant input.
2CLKA1(1) O Clock Output, Bank A.
3CLKA2(1) O Clock Output, Bank A.
4VDD I 3.3 V Supply
5GND I Ground
6CLKB1(1) O Clock Output, Bank B.
7CLKB2(1) O Clock Output, Bank B.
8S2(2) I Select Input pin, bit 2.
9S1(2) I Select Input pin, bit 1
10 CLKB3(1) O Clock Output, Bank B.
11 CLKB4(1) O Clock Output, Bank B.
12 GND Ground
13 VDD 3.3V supply
14 CLKA3(1) O Clock Output, Bank A.
15 CLKA4(1) O Clock Output, Bank A.
16 CLKOUT(1) O Buffered output, internal feedback on this pin.
Note 1: I ncludes weak pull down.
Note 2: I ncludes weak pull up.
Z9309 Select Input Functionality
S2 S1 CLKA1-A4 CLKB1-B4 CLK-OUT[1] Output Source PLL Shut-down
0 0 Tri-State Tri-State Driven PLL N
0 1 Driven Tri-State Driven PLL N
1 0 Driven Driven Driven REF Y
1 1 Driven Driven Driven PLL N
Note 1: This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and output.s. Table 1
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/4/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 3 of 9
REF, Input T0 CLKA/CLKB Delay vs. Loading Difference Between CLKOUT & CLKA/CLKB
Pins
0-5-10-15-20-25-30 5 1015202530
1500
1000
500
0
-500
-1000
-1500
Ref - Input to CLKA/CLKB Delay (ps)
Output Load Difference: CLKOUT Load - CLKA/CLKB Load (PF)
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs including CLKOUT must be equally loaded. Even if
CLKOUT is not used, it must have a capacitive load equal to that on other outputs. If input to output delay adjustments
are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs.
For zero output-output skew, be sure to load all outputs equally.
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.0 11/4/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 4 of 9
Maximum Ratings
Voltage Relative to VSS: -0.3V
Voltage Relative to VDD: 0.3V
Storage Temperature: 0°C to + 125°C
Operating Temperature: 0°C to +85°C
Maximum Power Supply: 7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Electrical Characteristics (Z9305/Z9309) (VDD = 3.0 to 3.6 V, TA = 0°C to 85°C)
Characteristic Symbol Min Typ Max Units Conditions
Input Low Voltage(1) VIL - - 0.8 Vdc
Input High Voltage(1) VIH 2.0 - Vdc -
Input Low Current IIL 50.0 µA VIN = 0V
Input High Current IIH ±100 µA VIN = VDD
Output Low Voltage(2) VOL 0.4 V IOL = 8 mA
Output High Voltage(2) VOH 2.4 V IOH = - 8mA
Tri-State leakage Current Ioz - - 10 µA S1 = S2 = GND
Power Down Supply Current Idd - - 50 µA Ref = 0 MHz
Dynamic Supply Current Idd - - 40 mA Unload outputs, 66.66 MHz, Select inputs
at VDD or GND.
Notes:
1. REF and FBK inputs have a threshold voltage of VDD/2.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified
with loaded outputs.
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/4/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 5 of 9
Switching Characteristics (Z9305/Z9309) (VDD = 3.0 to 3.6 V, TA = 0°C to 85°C)
Characteristic Symbol Min Typ Max Units Conditions
Output Period t110 150 MHz 30 pF load
Input Period t110 150 MHz 30 pF load
Duty Cycle (T2/T1) (1) - 45 50 55 % Measured @ 1.4V
Rise Time(1) t3- 1.5 nSec Measured between 0.8V & 2.0V, 15 pF
Load
Fall Time(1) t41.5 nSec Measured between 0.8V & 2.0V, 15 pF
Load
Output to Output Skew(1) t5- - 250 pSec All output equally loaded
Delay, REF Rising Edge to
CLKOUT Rising Edge(1) t6- 0 + 350 pSec Measured at VDD/2
Device to Device Skew(1) t7- 0 700 pSec Measured at VDD/2 on FBK pins of
devices
Cycle to Cycle Jitter(1) tj - - 200 pSec Measured at 66.67 MHz, loaded
outputs, input Trise/Fall < 1 nS
Maximum PLL Lock Time(1) tLOCK 1.0 ms Stable power supply, valid clocks
presented on REF pin.
Notes:
1. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified
with loaded outputs.
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.0 11/4/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 6 of 9
Test Circuit Diagrams
VDD
VDD
GND GND
Outputs
0.1 uF
0.1 uF
CLK out
C
LOAD
Test Circuit
Package Drawing and Dimensions
8 Pin SOIC Narrow Outline Dimensions
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A0.061 0.064 0.068 1.55 1.63 1.73
A10.004 0.006 0.0098 0.127 0.150 0.250
A20.055 0.058 0.061 1.40 1.47 1.55
B0.0138 0.016 0.0192 0.35 0.41 0.49
C0.0075 0.008 0.0098 0.19 0.20 0.25
D0.189 0.194 0.196 4.80 4.93 4.98
E0.150 0.155 0.157 3.81 3.94 3.99
e0.050 BSC 1.270 BSC
H .230 .236 .244 5.84 5.99 6.20
h 0.010 0.013 0.016 0.25 0.33 0.41
a0°5°8°0°5°8°
L 0.016 0.025 0.035 0.41 0.64 0.89
DA
A2
A1
B
e
EH
a
L
C
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/4/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 7 of 9
Package Drawing and Dimensions
(16 Pin 150 Mil SOIC) 16 Pin 150 Mil SOIC Outline Dimensions
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A 0.097 0.101 0.104 2.46 2.56 2.64
A10.0050 0.009 0.0115 0.127 0.22 0.29
A2 0.090 0.092 0.094 2.29 2.34 2.39
B 0.014 0.016 0.019 0.35 0.41 0.48
C 0.0091 0.010 0.0125 0.23 0.25 0.32
D 0.402 0.407 0.412 10.21 10.34 10.46
E 0.150 - 0.157 3.81 - 3.988
e 0.050 BSC 1.27 BSC
H 0.400 0.406 0.410 10.16 10.31 10.41
L 0.024 0.032 0.040 0.61 0.81 1.02
a 0º 5º 10º 0º 5º 10º
a
Be
A
A1
A2
D
EH
L
C
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.0 11/4/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 8 of 9
Package Drawing and Dimensions (Cont.)
BO
SURFACES ROUGHNESS: 6+ 27n(RZ)
D
-B-
1.50
E1
1.20
R0.1
B
e
-C- C0.07
R0.15
4
[10° TYP
0.05 MAX.
0.05 MAX.
1.0
1.0
E
R0.15
A
A1
0.25
A2
R
L1
L
A
8°
b
cc1
b1
DETAIL B
.08 CB A
DETAIL A
14° TYP
S
16 Pin TSSOP Dimensions
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A - - 0.0433 - - 1.10
A1 0.0019 0.0039 0.0059 0.05 0.10 0.15
A2 0.0346 0.0354 0.0374 0.85 0.90 0.95
L 0.0196 0.0236 0.0275 0.50 0.60 0.75
L1 0.0354 0.0393 0.0433 0.90 1.00 1.10
R 0.0035 - - 0.09 - -
b 0.0076 - 0.0108 0.195 - 0.275
b1 0.0076 0.0086 0.0096 0.195 0.22 0.245
c 0.0041 - 0.0068 0.105 - 0.175
c1 0.0041 0.0049 0.0057 0.105 0.125 0.145
θ0°-8°0°-8°
e 0.026 BSC 0.65 BSC
D 0.1948 0.1968 0.1988 4.95 5.0 5.05
E 0.2480 0.2519 0.2559 6.3 6.4 6.5
E1 0.1712 0.1732 0.1752 4.35 4.4 4.45
S 0.0078 - - 0.20 - -
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/4/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 9 of 9
Ordering Information
Part Number Package Type Production Flow
Z9305BX 8 Pin SOIC Commercial, 0°C to +85°C
Z9309BX 16 Pin SOIC Commercial, 0°C to +85°C
Z9309BT 16 Pin TSSOP Commercial, 0°C to +85°C
Note: The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI
Z9305BX
Date Code, Lot #
Z9305/Z9309BXB Flow
Commercial, 0°C to +85°C
Package
X = SOIC, 150 Mil.
T = TSSOP
Revision
IMI Device Number
