uPD69142-CSP500 - NEC Electronics

NEC Electronics Inc.

EA-C10

2.5-Volt, 0.25-Micron (drawn)

CMOS Embedded Array

March 1997Preliminary

A12503EU1V0DS00

EA-C10 Series Features EA-C10 Series Benefits

•0.25 µm drawn (0.18 µm L-effective) CMOS process ⇒Ultra-high density cell structure with high performance

•Advanced embedded array architecture ⇒Fast TAT and high integration of embedded megafunctions

•Available gate counts from 206K to 7 million gates ⇒Support for a wide range of high-complexity systems

•Optimized 2.5V architecture (operates down to 1.8V) ⇒Highest speed at ultra-low power consumption

•Significant low power dissipation of 0.14 µW/MHz/gate ⇒New application possibilities and new system solutions

•Ultra-high pin count using 40 µm pad pitch ⇒Increased I/O density to achieve smaller die sizes

•Special power rail structure, multi-oxide process ⇒Mixed 2.5V / true 3.3V I/O for full system compatibility

•Cell-based I/O structure including LVDS, HSTL, GTL+, PCI ⇒Flexible adaptation to system requirements

•Embedding of analog macros including DACs, ADCs ⇒Mixed-signal design options

•Advanced packages such as TapeBGA, Flip Chip+BGA ⇒Cost-effective and state-of-the-art packaging

•NEC’s OpenCAD® design environment ⇒Flexible design flow for short design times

Applications

The EA-C10 family is ideal for applications where high

density is mandatory and a short time-to-market path is

required. For example, RAM-dominated designs can be

realized with reduced die size and a reasonable turnaround

time. EA-C10 is well-suited for designs that may require

rework, because the logic function portion of the design

uses gate array primitives created just by the final metal

masks. Typical applications include engineering

workstations, telecommunications systems, advanced

graphics and low power applications where very high

performance is required.

Figure 1. Embedded Array Core Integration

Table 1. EA-C10 Series Features and Benefits

Description

The high-speed 0.25 µm drawn (0.18 µm L-effective)

EA-C10 embedded array family offers both support for

embedded high-density macros as well as the short

turnaround time of a gate array resulting in a time-to-

market advantage. In this product, NEC combines high-

performance CMOS gate array primitives with diffused,

embedded megafunctions such as RAM, ROM, CPU,

DSP and analog cores.

EA-C10 also uses a cell-based I/O structure that allows a

flexible adaptation to the system requirements. State-of-

the-art interface macros for high-speed or special signaling

systems are also supported, such as PCI, HSTL, GTL+,

LVDS, p-ECL, and IEEE1394. Analog functions like DACs,

ADCs and PLLs also can be incorporated within the I/O

area.

Process

EA-C10 ASICs are manufactured with NEC’s advanced

titanium-silicide (Ti-Si) process. The chip layout may use

between three and five metal layers (Al). As the EA-C10

ASIC family follows basically a gate array approach, it

offers short turnaround times for silicon processing and

lower development costs compared to cell-based ASICs.

The turnaround time is kept short by fixing the embedded

core locations and beginning prototype fabrication in

parallel with place and route design steps.

High Density

Memory

Analog

Macro

Logic

Function

Cell-Based

I/O Cells

High Density

Cell-Based

Compiled Memory

Gate Array

Primitives

(Sea-of-Gate)

Advanced Core

and

Analog Functions

Gate Array

Base Master

Core

Megafunction

OpenCAD is a registered trademark of NEC Electronics Inc.

All non-NEC trademarks are the property of their respective owners.

EA-C10

Interface Macro Support

The EA-C10 interface area uses the cell-based (CB-C10)

I/O structures that provide a variety of interface options,

including both 2.5-volt and 3.3-volt full-swing interface

buffers.

For special applications, several high-speed I/O buffer

types are available. These include 3.3-volt PCI cells, AGP

for 66 MHz and 133 MHz applications, GTL (Gunning

Transceiver Logic), HSTL (class 1,2,3,4) and pseudo-

ECL (pECL) buffers. These high-speed buffers are

available for special applications. Table 3 summarizes

the available interface options.

2.5-Volt / 3.3-Volt Mixed I/O Interfacing. Although

EA-C10 is a 2.5-volt optimized technology with thin gate

oxide, NEC offers 3.3-volt-compatible I/O interfacing.

The full-swing 3.3-volt interfacing is achieved through a

multi-oxide process in the I/O area. The buffers for 2.5-

volt / 3.3-volt interface levels can be mixed. This is

supported by the special power rail structure shown in

Figure 2.

Table 2. Product Outline

Master (µPD69..) 3 layer ..101 ..102 ..103 ..104 ..105 ..107 ..109 ..111 ..112 ..113 ..114 ..115

Master (µPD69..) 4 layer ..121 ..122 ..123 ..124 ..125 ..127 ..129 ..131 ..132 ..133 ..134 ..135

Master (µPD69..) 5 layer* ..141 ..142 ..143 ..144 ..145 ..147 ..149 ..151 ..152 ..153 ..154 ..155

Gate count (available) 206k 338k 497k 690k 1041k 1611k 2127k 2509k 3137k 3597k 4089k 6937k

Number of pads (40 µm pitch) 348 444 540 636 780 972 1116 1212 1356 1452 1548 2016

Utilization 80% for 3-layer metal; 85% for 4-layer metal

Toggle frequency (typ.) 1.1 GHz

Internal 59 ps (F/O = 1, L = 0 mm); 147.5 ps (F/O = 2, L = typ. average length) (F322 )

Delay time Input 79.9 ps (F/O = 2, L = 0 mm) (FI01)

Output 1.363 ns (CL = 50 pF) (FO02)

Consumed Internal 0.14 µW/MHz/gate (2.5V); 0.07 µW/MHz/gate (1.8V)

power Input 1.66 µW/MHz (F/O = 2, L = 0 mm)

Output 167 µW/MHz (CL = 15 pF)

Power supply voltage 2.5 V ± 0.2V (operation down to 1.8V possible)

Operating temperature -40 to +85°C

Interface level 2.5V / 3.3V CMOS level, LVTTL level, GTL+,HSTL, PCI, pECL

Technology Sea-of-gates 0.25 µm (drawn) silicon gate CMOS (0.18 L-effective), diffused embedded macros, 3, 4 or 5*

metal layers

Note: *5th metal layer used for flip-chip packaging

Figure 2. Power Rail Structure

Drawing not to scale

Internal Core

for internal power supply

VDD (2.5V, 3.3V)

VDDQ (ex. HSTL)

GND

increased internal

cell area

I/O area for 2.5V only

mixed voltage I/O area

2.5V I/O area 3.3V I/O area

VDDQ I/O area

HSTL / PCI Interfacing. A third power rail (VDDQ) is

available for interface types that require a reference

voltage (such as HSTL, GTL+, and AGP). These buffers

may also be located anywhere in the I/O area.

EA-C10

Table 3. EA-C10 I/O Buffer Types

Buffer Type Options and Possible Combinations

Standard I/O Pull-up 50 kΩ, 5 kΩ / Pull-down 50 k Ω

Interface Schmitt Trigger input

Buffers Fail safe

LVCMOS / LVTTL level

Output buffers:

Open drain

Tri-state

Low noise (slew-rate controlled)

Driveability:

2.5V interface: 3, 6, 9, 12, 18, 24 mA/slot

3.3V interface: 3, 6, 9, 12, 24 mA/slot

High-Speed PCI (3.3V, up to 64 bit / 66 MHz)

I/O Buffers GTL / GTL+

pECL

HSTL

SSTL

LVDS*

AGP (66 MHz and 133 MHz)

IEEE1394*

USB*

Note: *Under development. Please check the availability of the

advanced interfaces with your nearest NEC design center.

Macro Library Support

The embedded array approach allows the combination of

high-density cores with a prototype turnaround time equal

to gate arrays. Megafunctions and memory blocks such

as RAM and ROM can be embedded into the sea-of-gates

area within the EA-C10 base master. The area used for

the megafunctions is defined by pre-diffusion. The logical

function is created by the final metalization masks. This

enables the usage of a gate array master and the whole

set of macros available in the cell-based technology CB-

C10. Cores from the BiCMOS family (QB-10) may also be

embedded.

Memory Macros. Various kinds of memory macros are

available for EA-C10. Designers can select either gate

array memory compilers using gate array cells or cell-

based compilers which offer higher density and faster

access times.

Cell-based type memory blocks are generated based on

advanced memory compiler tools and thus ensure highest

flexibility for design requirements. The available memory

types are described in Table 4.

Table 4. CMOS-10 / EA-C10 Memory Compilers

Family Type Mode Ports Maximum Size

CMOS-10/ High-speed Async. 18 Kbit

EA-C10 Aysnc. 28 Kbit

High-speed Sync. 216 Kbit

Sync. 316 Kbit

Sync. 58 Kbit

EA-C10 High-density Sync. 12K word x 32 bit

Sync. 22K word x 64 bit

High-speed Sync. 12K word x 64 bit

Sync. 24K word x 64 bit

Super high-speed Sync. 14K word x 64 bit

Block Library Support

EA-C10's functional blocks are designed to be backward-

compatible with previous families. Thus, an easy migration

from previous designs is possible. The library is fully

compatible with CMOS-10, the 0.25 µm (drawn) gate

array familiy.

The EA-C10 family offers a wide variety of advanced

blocks, including combinational gates, shift registers,

adders and counters. In addition, memory blocks such as

RAM and ROM are provided. The EA-C10 primitive

macros are available in up to four performance/power

options per primitive. With a range of options available,

popular design synthesis tools are able to make the

optimal size/performance/power choice for each path. All memory macros can be combined with a built-in-self-

test (BIST) macro for easy and high-performance

production testing.

EA-C10

resolutions of 7 to 12 bits and a frequency of 100 kHz to

220 MHz for high-speed conversion.

Mega Macros. NEC offers a large set of megamacros

and cores to cope with today’s system requirements.

Table 5 shows a subset of the macro portfolio.

Type Description Type Description

Table 5. EA-C10 Mega Macro Library (subset listing)

CPU V30MZ™: 16-bit microprocessor

CPU V8xx™: 32-bit RISC microcontroller

(several derivates)

CPU ARM

CPU VR4xxx™: 64-bit RISC microcontroller

(several derivates)

Datapath High-speed multiplier/accumulator

DSP OAK: digital signal processor

DSP PINE: digital signal processor

DSP SPRX: digital signal processor

I/F peripheral 16550: UART with FIFO and 16450 mode

I/F peripheral 4993: 8-bit parallel I/O real-time clock

I/F peripheral 71037: DMA Controller

I/F peripheral 71051: USART, 300k bit/s, full-duplex

I/F peripheral 71054: programmable timer/counter

I/F peripheral 71055: programmable parallel interface (3x 8-bit)

I/F peripheral 71059: interrupt controller unit

I/F peripheral ATM (25 MHz, 155 MHz)

I/F peripheral CODEC (modem, voice)

I/F peripheral Ethernet 10/100 base

I/F peripheral IEEE 1284: bidirectional centronics

I/F peripheral IEEE1394: high speed serial bus

I/F peripheral MPEG2

I/F peripheral PCI controller

I/F peripheral RAC: RAMBUS ASIC Cell

I/F peripheral USB: Universal Serial Bus interface

DPLL Digital PLL (up to 250 MHz)

APLL Analog PLL (up to 500 MHz)

Plastic BGAs with up to 672 balls can help to cope with

high-complexity system requirements by providing excel-

lent electrical and thermal characteristics. Tape BGA

packages support up to 1088 balls.

NEC expands the package offering continuously with new

advanced packages. For high-performance applications

with high pin counts, the 2-layer tape BGA with enhanced

electrical characteristics is available. Applications that

require ultra-dense packages can be realized with the flip-

chip package. This technique can also be used for Multi-

Chip Module (MCM) structures, where die mounting was

previously necessary.

Packaging

The advanced pad pitch of 40 µm allows high-pin-count

applications and gives a significant benefit for pad-limited

designs. EA-C10, the new high-performance embedded

array family, is supported by a variety of advanced pack-

ages. For lower pin counts (up to 376 pins), the standard

QFP is available, including the heat-spreader package

type to improve thermal characteristics.

Package Type Maximum Pin/Ball Count

Plastic BGA 672

Tape BGA 1088

QFP 376 (0.4 mm pitch)

Flip-Chip 2016

Chip Scale 500

Analog Macros. A variety of A/D and D/A converters will

be available for analog applications. Analog-to-digital

converters (ADCs) are under development with a bit

resolution of 7 to 12 bits and a frequency of 100 kHz (for

general-purpose applications) up to 30 MHz. Digital-to-

analog converters (DACs) will also be developed with

V30MZ, V8xx, and Vr4xxx are trademarks of NEC Corporation.

EA-C10

CAD Support

NEC takes up the challenges of the new ultra-high-

density 0.25 µm technology by having close relationships

with leading EDA vendors to fulfill the design require-

ments during the whole design flow.

Fully supported by NEC’s sophisticated OpenCAD design

framework, EA-C10 maximizes design quality and flex-

ibility while minimizing ASIC design time.

NEC’s OpenCAD system allows designers to combine

the EDA industry’s most popular third-party design tools

with proprietary NEC tools, including those for advanced

floorplanner, clock tree synthesis, automatic test pattern

generation (ATPG), full-timing simulation, accelerated

fault grading and advanced place and route algorithms.

The latest OpenCAD system is open for sign-off using

standard EDA tools. NEC offers RTL- and STA-(Static

Timing Analysis) sign-off procedures to shorten the ASIC

design cycle of high-complexity designs.

Support of High-Speed Systems. High-speed systems

require tight control of clock skew on the chip and between

devices on a printed circuit board. CB-C10 provides two

features to control clock skew: the Digital PLL (DPLL)

working at frequencies up to 250 MHz for chip-to-chip

skew minimization and Clock Tree Synthesis (CTS).

CTS — supported by an NEC proprietary design tool — is

used for clock skew management through the automatic

insertion of a balanced buffer tree. The clock tree insertion

method minimizes large-capacitive trunks and is especially

useful with the hierarchical, synthesized design style

being used for high-integration devices. RC values for

actual net lengths of the clock tree are used for back

annotation after place and route operations. A skew as

low as ±60 ps can be achieved.

Accurate Design Verification. Nonlinear timing

calculation is a very important requirement of the high-

density, deep sub-micron ASIC designs. NEC makes use

of the increased accuracy delivered by the nonlinear table

look-up delay calculation methodology and offers

consistent wire load models to ensure a high accuracy of

the design verification.

Design Rule Check. A comprehensive design rule

check (DRC) program reports design rule violations as

well as chip utilization statistics for the design netlist. The

generated report contains such information as net counts,

total pin and gate counts, and utilization figures.

Layout. During design synthesis, wire load models are

used to get delay estimations in a very early state of the

design flow. In general, there’s no need for customers to

perform the floorplanning to meet the required timing.

During layout, enhanced in-place optimization (IPO)

features of the layout tools and engineering change order

(ECO) capabilities of the synthesis tools are used to

optimize critical timing paths defined by the given timing

constraints. This feature can reduce the total design time.

Test Support

The EA-C10 family supports automatic test generation

through a scan test methodology. It includes internal

scan, boundary scan (JTAG) and built-in-self-test (BIST)

architecture for easy and high-performance production

RAM testing. This allows higher fault coverage, easier

testing and faster development time.

Test of embedded megamacros is supported from NEC’s

test bus concept, which allows the use of predefined test

pattern sets for integrated core macros.

Supplemental Publications

This data sheet contains preliminary specifications and

operational data for the EA-C10 embedded array family.

Additional information is available in NEC’s EA-C10 Design

Manual, Block Library and other related documents.

Please refer also to the CMOS-10 and CB-C10 data

sheets to get more information about 0.25 µm gate array

and cell-based ASIC products.

Please contact your local NEC design center for additional

information; see the back of this data sheet for locations

and telephone numbers.

EA-C10

Absolute Maximum Ratings

Power supply voltage, VDD 3.6 V

Input voltage, VI

2.5V input buffer 3.6 V

3.3V input buffer 4.6 V

Output voltage, VO

2.5V buffer 3.6 V

3.3V buffer 4.6 V

Latch-up current, ILATCH 1 A

Operating temperature, TOPT -40 to +85°C

Storage temperature, TSTG -65 to +150°C

Input / Output Capacitance

VDD=VI=0 V; f=1 MHz

Terminal Symbol Typ Max Unit

Input CIN 4 6 pF

Output COUT 46pF

I/O CI/O 4 6 pF

Note: Values do not include package pin capacitance.

Power Consumption

Description Limits Unit

Internal cell (@ 2.5V supply voltage, loaded) 0.14 µW/MHz

Input block (FI01, F/O=2, L=0) 1.66 µW/MHz

Output block (F002 @ 15 pF) 167 µW/MHz

Recommended Operating Conditions

2.5V Buffer 3.3V Buffer 3.3V PCI

Parameter Symbol Min Max Min Max Min Max Unit

Power supply voltage VDD 2.3 2.7 3.0 3.6 3.0 3.6 V

Junction temperature TJ-40 +125 -40 +125 -40 +125 °C

Low-level input voltage VIL 00.7 -0.5 0.3 VDD -0.5 0.3 VDD V

High-level input voltage VIH 1.7 VDD 0.5 VDD VDD+ 0.5 0.5 VDD VDD+ 0.5 V

Input rise or fall time tR, tF0200 0200 0200 ns

Input rise or fall time, Schmitt tR, tF010 010 010 ms

AC Characteristics

VDD = 2.5 V ± 0.2 V; Tj = 0 to +125°C

Parameter Symbol Best Typ Worst Unit Conditions

Toggle frequency fTOG 2.8 2.0 1.1 GHz D-F/F; F/O = 1

Delay time

2-input power - NAND (F322) tPD 30.5 41.1 67.7 ps F/O = 2; L = 0 mm

tPD 43.6 59.0 96.4 ps F/O = 1; L = 0.5 mm

Flip-flop (F611) tPD 200 278 465 ps F/O = 1; L = 0 mm

tPD 242 336 558 ps F/O = 2; L = 0.5 mm

tSETUP 170 220 340 ps —

tHOLD 60 50 50 ps —

Input buffer (FI01) tPD 77.8 103 188 ps F/O = 1; L = 0.5 mm

tPD 63.0 79.7 144 ps F/O = 2; L = 0 mm

Input buffer (3.3V) * tPD 190 286 510 ps F/O = 1; L = 0.5 mm

tPD 173 255 451 ps F/O = 2; L = 0 mm

Output buffer (12 mA) 2.5V tPD 287 439 779 ps CL = 0 pF

Output buffer (12 mA) 2.5V tPD 932 1363 2312 ps CL = 50 pF

Output buffer (12 mA) 3.3V * tPD 457 659 1192 ps CL = 0 pF

Output buffer (12 mA) 3.3V * tPD 1386 2115 3554 ps CL = 50 pF

Output rise time (12 mA) tR0.73 1.03 1.83 ns CL = 15 pF; 10-90%

Output fall time (12 mA) tF0.75 0.93 1.55 ns CL = 15 pF; 10-90%

Note: *including delay of level shifter circuit

EA-C10

DC Characteristics

VDD = 2.5 V ± 0.2 V; Tj = 0 to +125° C

Parameter Symbol Min Typ Max Unit Conditions

Quiescent current

<= 2000K gates IDDS 40 800 µA VI = VDD or GND

> 2000K gates IDDS 70 1400 µA VI = VDD or GND

Off-state output leakage current

2.5V output IOZ ±10 µA VO = VDD or GND

3.3V output IOZ ±10 µA VO = VDD or GND

Output sink current with pull-up (VO = 2.5V) IRµA VPU = 3.3 V, RPU =2kΩ

Output sink short circuit current IOS -250 mA VO = GND

Input leakage current

Regular II±10-4 ±10 µA VI = VDD or GND

50 kΩ pull-up IITBD µA VI = GND

5 kΩ pull-up IITBD mA VI = GND

50 kΩ pull-down IITBD µA VI = VDD

Pull-up resistor

50 kΩ pull-up RPU TBD kΩ

5 kΩ pull-up RPU TBD kΩ

50 kΩ pull-down RPD TBD kΩ

Low-level output current

2.5V buffers

3 mA IOL 11.0 8.8 5.2 mA VOL = 0.4V

6 mA IOL 22.3 17.6 11.5 mA VOL = 0.4V

9 mA IOL 33.5 26.5 15.8 mA VOL = 0.4V

12 mA IOL 44.5 35.3 21.2 mA VOL = 0.4V

18 mA IOL 66.7 52.9 31.7 mA VOL =0.4V

24 mA IOL 88.7 70.5 42.3 mA VOL = 0.4V

3.3V buffers (full-swing)

3 mA IOL 20.5 14.5 8.3 mA VOL = 0.4V

6 mA IOL 30.3 21.7 12.5 mA VOL = 0.4V

9 mA IOL 40.5 29.0 16.7 mA VOL = 0.4V

12 mA IOL 46.8 36.0 20.8 mA VOL = 0.4V

Low-level output voltage

2.5V buffers VOL 0.1 VIOL = 0 mA

3.3V buffers VOL 0.1 VIOL = 0 mA

High-level output voltage

2.5V buffers VOH VDD - 0.1 VIOH = 0 mA

3.3V buffers VOH VDD - 0.1 VIOH = 0 mA

EA-C10

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THIRD-PARTY DESIGN CENTERS

SOUTH CENTRAL/SOUTHEAST

•Koos Technical Services, Inc.

385 Commerce Way, Suite 101

Longwood, FL 32750

TEL407-260-8727

FAX407-260-6227

•Integrated Silicon Systems Inc.

2222 Chapel Hill Nelson Highway

Durham, NC 27713

TEL919-361-5814

FAX919-361-2019

•Applied Systems, Inc.

1761 W. Hillsboro Blvd., Suite 328

Deerfield Beach, FL 33442

TEL305-428-0534

FAX305-428-5906

NEC Electronics Inc.

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