30 V, Low Noise, Rail-to-Rail Input/Output,
Low Power Operational Amplifiers
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
Rev. I Document Feedback
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FEATURES
Rail-to-rail input/output
Low power: 0.625 mA typical per amplifier at ±15 V
Gain bandwidth product: 15.9 MHz at AV = 100 typical
Unity-gain crossover: 9.9 MHz typical
−3 dB closed-loop bandwidth: 13.9 MHz typical at ±15 V
Low offset voltage: 100 µV maximum (SOIC)
Unity-gain stable
High slew rate: 4.6 V/µs typical
Low noise: 3.9 nV/√Hz typical at 1 kHz
Long-term offset voltage drift (10,000 hours): 3 µV typical
Temperature hysteresis: 4 µV typical
APPLICATIONS
Battery-powered instrumentation
High-side and low-side sensing
Power supply control and protection
Telecommunications
Digital-to-analog converter (DAC) output amplifiers
Analog-to-digital converter (ADC) input buffers
PIN CONNECTION DIAGRAM
08237-001
NOTES
1. F OR T HE LF CS P P ACKAGE,
THE EXPOSED PAD MUST BE
CONNECTED TO V –.
3+IN A
4V–
1OUT A
2–I N A
6–IN B
5+IN B
8 V+
7OUT B
ADA4084-2
Figure 1. ADA4084-2, 8-Lead LFCSP (CP); for Additional Packages and
Models, See the Pin Configurations and Function Descriptions Section
GENERAL DESCRIPTION
The ADA4084-1 (single), ADA4084-2 (dual), and ADA4084-4
(quad) are single-supply, 10 MHz bandwidth amplifiers featuring
rail-to-rail inputs and outputs. They are guaranteed to operate
from +3 V to +30 V (or ±1.5 V to ±15 V).
These amplifiers are well suited for single-supply applications
requiring both ac and precision dc performance. The combination
of wide bandwidth, low noise, and precision makes the
ADA4084-1/ADA4084-2/ADA4084-4 useful in a wide variety of
applications, including filters and instrumentation.
Other applications for these amplifiers include portable telecom-
munications equipment, power supply control and protection, and
use as amplifiers or buffers for transducers with wide output
ranges. Sensors requiring a rail-to-rail input amplifier include
Hall effect, piezoelectric, and resistive transducers.
The ability to swing rail to rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
The ADA4084-1/ADA4084-2/ADA4084-4 are specified over
the industrial temperature range of −40°C to +125°C.
The single ADA4084-1 is available in the 5-lead SOT-23 and
8-lead SOIC; the dual ADA4084-2 is available in the 8-lead
SOIC, 8-lead MSOP, and 8-lead LFCSP surface-mount
packages; and the ADA4084-4 is offered in the 14-lead TSSOP
and 16-lead LFCSP.
The ADA4084-1/ADA4084-2/ADA4084-4 are members of a
growing series of high voltage, low noise op amps offered by
Analog Devices, Inc. (see Table 1).
Table 1. Low Noise Op Amps
Single
Dual
Quad
Voltage Noise
AD8597 AD8599 1.1 nV/Hz
ADA4004-1 ADA4004-2 ADA4004-4 1.8 nV/Hz
AD8675 AD8676 2.8 nV/Hz rail-to-rail output
AD8671 AD8672 AD8674 2.8 nV/Hz
OP27, OP37 3.2 nV/Hz
ADA4084-1 ADA4084-2 ADA4084-4 3.9 nV/Hz rail-to-rail
input/output
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Connection Diagram ................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Electrical Characteristics ............................................................. 4
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 11
±1.5 V Characteristics ................................................................ 11
±5 V Characteristics ................................................................... 17
±15 V Characteristics ................................................................ 23
Applications Information .............................................................. 29
Functional Description .............................................................. 29
Start-Up Characteristics ............................................................ 30
Input Protection ......................................................................... 30
Output Phase Reversal ............................................................... 30
Designing Low Noise Circuits in Single-Supply Applications .. 31
Comparator Operation .............................................................. 31
Long-Term Drift ......................................................................... 32
Temperature Hysteresis ............................................................. 32
Outline Dimensions ....................................................................... 33
Ordering Guide .......................................................................... 36
REVISION HISTORY
5/2017—Rev. H to Rev. I
Changed CP-8-12 to CP-8-11 ...................................... Throughout
Changed CP-16-26 to CP-16-17 .................................. Throughout
Changes to Features Section............................................................ 1
Added Long-Term Drift Section, Temperature Hysteresis
Section, Figure 112, Figure 113, and Figure 114; Renumbered
Sequentially ..................................................................................... 32
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 36
8/2015—Rev. G to Rev. H
Added 5-Lead SOT-23 ....................................................... Universal
Changes to Pin Connection Diagram Section, Figure 1, and
General Description Section ........................................................... 1
Deleted Figure 3; Renumbered Sequentially ................................. 1
Changes to Large Signal Voltage Gain Parameter, Table 2 .......... 4
Changes to Large Signal Voltage Gain Parameter, Table 3 .......... 5
Changes to Large Signal Voltage Gain Parameter, Table 4 .......... 6
Changes to Table 6 ............................................................................ 7
Moved Figure 3 ................................................................................. 8
Added Pin Configurations and Function Descriptions Section,
Figure 4, Figure 5, Table 7, Table 8, and Table 9; Renumbered
Sequentially ....................................................................................... 8
Added Figure 6, Figure 7, Figure 8, Table 10, and Table 11 ........ 9
Moved Figure 9 ............................................................................... 10
Added Table 12 ............................................................................... 10
Added Figure 11 and Figure 15..................................................... 11
Added Figure 42 and Figure 46..................................................... 17
Added Figure 73 and Figure 77..................................................... 23
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 35
6/2015—Rev. F to Rev. G
Changes to Figure 96 and Figure 97............................................. 24
1/2015—Rev. E to Rev. F
Moved Revision History ................................................................... 3
Changes to Table 5 ............................................................................. 7
Changes to Ordering Guide .......................................................... 29
7/2014—Rev. D to Rev. E
Added ADA4084-1 ............................................................. Universal
Added Figure 1; Renumbered Sequentially ................................... 1
Changes to Output Voltage High Parameter, Table 2 ................... 3
Changes to Current Noise Density Parameter, Table 3 ................ 4
Changes to Current Noise Density Parameter, Table 4 ................ 5
Changes to Figure 8 Caption, and Figure 9 to Figure 11 ............. 7
Changes to Figure 13 ......................................................................... 8
Changes to Figure 21 ......................................................................... 9
Added Figure 31; Renumbered Sequentially .............................. 11
Changes to Figure 30 Caption, and Figure 32 to Figure 34 ...... 11
Changes to Figure 36 Caption to Figure 39 Caption ................. 12
Changes to Figure 50 ...................................................................... 14
Added Figure 60 ............................................................................. 16
Changes to Figure 59 Caption, Figure 62, and Figure 63 .......... 16
Changes to Figure 65 Caption to Figure 68 Caption ................. 17
Changes to Figure 79 ...................................................................... 19
Added Figure 89 ............................................................................. 21
Changes to Figure 88 Caption, Figure 91 Caption, and
Figure 92 Caption ........................................................................... 21
Changes to Ordering Guide .......................................................... 28
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 3 of 36
11/2013—Rev. C to Rev. D
Added 14-Lead TSSOP and 16-Lead LFCSP Packages ....... Universal
Added ADA4084-4 ..................................................................... Universal
Change to Features Section and Applications Section ................. 1
Added Figure 2 and Figure 3; Renumbered Sequentially ............ 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 ............................................................................ 5
Changes to Table 5 and Table 6 ....................................................... 6
Changes to Typical Performance Characteristics Section ........... 7
Updated Outline Dimensions ........................................................ 27
Changes to Ordering Guide ........................................................... 28
4/2013—Rev. B to Rev. C
Changes to Figure 48 Caption ....................................................... 15
Updated Outline Dimensions ........................................................ 25
6/2012—Rev. A to Rev. B
Added LFCSP Package....................................................... Universal
Changes to Figure 1 ........................................................................... 1
Changes to Output Voltage High Parameter, Table 4 ................... 5
Added Figure 5 and Figure 7, Renumbered Sequentially ............ 7
Added Figure 30 and Figure 32 ..................................................... 12
Added Figure 55 and Figure 57 ..................................................... 17
Added Startup Characteristics Section ........................................ 23
Moved Figure 78 .............................................................................. 23
Changes to Output Phase Reversal Section and Comparator
Operation Section ........................................................................... 24
Updated Outline Dimensions ........................................................ 25
Changes to Ordering Guide ........................................................... 26
2/2012—Rev. 0 to Rev. A
Changes to Data Sheet Title ............................................................. 1
Changes to Voltage Range in General Description ...................... 1
Changes to Supply Current/Amplifier Parameter, Table 2 .......... 3
Changes to Common-Mode Rejection Ratio Parameter, Table 3 .. 4
Changes to Common-Mode Rejection Ratio Parameter, Table 4 .. 5
Changes to Figure 2 .......................................................................... 6
Changes to Figure 24 ...................................................................... 10
Changes to Figure 32 ...................................................................... 12
Changes to Figure 47 ...................................................................... 14
Changes to Figure 55 ...................................................................... 16
Changes to Figure 62 ...................................................................... 17
Changes to Figure 73 ...................................................................... 20
10/2011—Revision 0: Initial Version
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 4 of 36
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY = 3 V, V CM = 1.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS SOIC package 20 100 µV
−40°C ≤ TA ≤ +125°C 200 µV
SOT-23, MSOP, TSSOP packages 50 130 µV
−40°C ≤ TA ≤ +125°C 250 µV
ADA4084-2 LFCSP package
80
200
µV
−40°C ≤ TA ≤ +125°C 300 µV
Offset Voltage Drift Δt/ΔT −40°C ≤ TA ≤ +125°C 0.5 1.75 µV/°C
Offset Voltage Matching TA = 25°C 150 µV
ADA4084-4 LFCSP package 200 µV
Input Bias Current IB 140 250 nA
−40°C ≤ TA ≤ +125°C 400 nA
Input Offset Current IOS 5 25 nA
−40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 3 V 64 88 dB
−40°C ≤ TA ≤ +125°C 60 dB
A
VO
R
L
= 2 kΩ, 0.5 V ≤ V
OUT
≤ 2.5 V
100
104
dB
−40°C ≤ T
A
≤ +125°C
97
dB
Input Impedance
Differential 100||1.1 kΩ||pF
Common Mode 80||2.9 MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 2.90 2.95 V
−40°C ≤ TA ≤ +125°C 2.80 V
RL = 2 kΩ to VCM 2.85 2.9 V
−40°C ≤ TA ≤ +125°C 2.70 V
Output Voltage Low VOL RL = 10 kΩ to VCM 10 20 mV
−40°C ≤ TA ≤ +125°C 40 mV
RL = 2 kΩ to VCM 20 30 mV
−40°C ≤ TA ≤ +125°C 50 mV
Short-Circuit Current ISC −17/+10 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±1.25 V to ±1.75 V 100 110 dB
−40°C ≤ TA ≤ +125°C 90 dB
Supply Current per Amplifier ISY IOUT = 0 mA 0.565 0.650 mA
−40°C ≤ TA ≤ +125°C 0.950 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 2.0 2.6 V/µs
GBP
V
IN
= 5 mV p-p, R
L
= 10 kΩ, A
V
= 100
15.4
MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 8.08 MHz
Phase Margin ΦM 86 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 12.3 MHz
Settling Time tS AV = 10, VIN = 2 V p-p, 0.1% 4 µs
Total Harmonic Distortion Plus Noise THD + N VIN = 300 mV rms, RL = 2 kΩ, f = 1 kHz 0.009 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.14 µV p-p
Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz
i
n
f = 1 kHz
0.55
pA/√Hz
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 5 of 36
VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS SOIC package 30 100 µV
−40°C ≤ TA ≤ +125°C 200 µV
SOT-23, MSOP, TSSOP packages 60 130 µV
−40°C ≤ TA ≤ +125°C 250 µV
ADA4084-2 LFCSP package
90
200
µV
−40°C ≤ TA ≤ +125°C 300 µV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.5 1.75 µV/°C
Offset Voltage Matching TA = 25°C 150 µV
ADA4084-4 LFCSP package 200 µV
Input Bias Current IB 140 250 nA
−40°C ≤ TA ≤ +125°C 400 nA
Input Offset Current IOS 5 25 nA
−40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range −5 +5 V
Common-Mode Rejection Ratio CMRR VCM = ±4 V, −40°C ≤ TA ≤ +125°C 106 124 dB
VCM = ±5 V 76 dB
V
CM
= ±5 V, −40°C ≤ T
A
≤ +125°C
70
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 kΩ, −4 V ≤ V
OUT
≤ 4 V
108
112
dB
−40°C ≤ TA ≤ +125°C 103 dB
Input Impedance
Differential 100||1.1 kΩ||pF
Common Mode 200||2.5 MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 4.9 4.95 V
−40°C ≤ TA ≤ +125°C 4.8 V
RL = 2 kΩ to VCM 4.8 4.85 V
−40°C ≤ T
A
≤ +125°C
4.7
V
Output Voltage Low VOL RL = 10 kΩ to VCM −4.95 −4.9 V
−40°C ≤ TA ≤ +125°C −4.8 V
RL = 2 kΩ to VCM −4.95 −4.8 V
−40°C ≤ TA ≤ +125°C −4.7 V
Short-Circuit Current ISC −24/+17 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±2 V to ±18 V 110 120 dB
−40°C ≤ TA ≤ +125°C 105 dB
Supply Current per Amplifier ISY IOUT = 0 mA 0.595 0.700 mA
−40°C ≤ TA ≤ +125°C 1.00 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ to VCM 2.4 3.7 V/µs
Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.9 MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 9.6 MHz
Phase Margin ΦM 85 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 13.9 MHz
Settling Time tS AV = 10, VIN = 8 V p-p, 0.1% 4 µs
Total Harmonic Distortion Plus Noise THD + N VIN = 2 V rms, RL = 2 kΩ, f = 1 kHz 0.003 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.14 µV p-p
Voltage Noise Density
e
n
f = 1 kHz
3.9
nV/√Hz
Current Noise Density in f = 1 kHz 0.55 pA/√Hz
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 6 of 36
VSY = ±15.0 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS SOIC package 40 100 µV
−40°C ≤ TA ≤ +125°C 200 µV
SOT-23, MSOP, TSSOP packages 70 130 µV
−40°C ≤ TA ≤ +125°C 250 µV
ADA4084-2 LFCSP package
100
200
µV
−40°C ≤ TA ≤ +125°C 300 µV
Offset Voltage Drift ΔVOS/ΔT 0.5 1.75 µV/°C
Offset Voltage Matching TA = 25°C 150 µV
ADA4084-4 LFCSP package 200 µV
Input Bias Current IB 140 250 nA
−40°C ≤ TA ≤ +125°C 400 nA
Input Offset Current IOS 5 25 nA
−40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range −15 +15 V
Common-Mode Rejection Ratio CMRR VCM = ±14 V, −40°C ≤ TA ≤ +125°C 106 124 dB
VCM = ±15 V 85 dB
V
CM
= ±15 V, −40°C ≤ T
A
≤ +125°C
80
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 kΩ, −13.5 V ≤ V
OUT
≤ +13.5 V
110
117
dB
−40°C ≤ TA ≤ +125°C 105 dB
Input Impedance
Differential 100||1.1 kΩ||pF
Common Mode 200||2.5 MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 14.85 14.9 V
−40°C ≤ TA ≤ +125°C 14.8 V
RL = 2 kΩ to VCM 14.5 14.6 V
−40°C ≤ T
A
≤ +125°C
14.0
V
Output Voltage Low VOL RL = 10 kΩ to VCM −14.95 −14.9 V
−40°C ≤ TA ≤ +125°C −14.8 V
RL = 2 kΩ to VCM −14.9 −14.8 V
−40°C ≤ TA ≤ +125°C −14.7 V
Short-Circuit Current ISC ±30 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = +1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±2 V to ±18 V 110 120 dB
−40°C ≤ TA ≤ +125°C 105 dB
Supply Current per Amplifier ISY IOUT = 0 mA 0.625 0.750 mA
−40°C ≤ TA ≤ +125°C 1.050 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 2.4 4.6 V/µs
Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.9 MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 9.9 MHz
Phase Margin ΦM 86 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 13.9 MHz
Settling Time tS AV = 10, VIN = 10 V p-p, 0.1% 4 µs
Total Harmonic Distortion Plus Noise THD + N VIN = 5 V rms, RL = 2 kΩ, f = 1 kHz 0.003 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.1 µV p-p
Voltage Noise Density
e
n
f = 1 kHz
3.9
nV/√Hz
Current Noise Density in f = 1 kHz 0.55 pA/√Hz
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 7 of 36
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage ±18 V
Input Voltage
V− ≤ V
IN
≤ V+
Differential Input Voltage1 ±0.6 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec)
300°C
ESD
Human Body Model2 4.5 kV
Machine Model3 200 V
Field-Induced Charged-Device Model
(FICDM)4
1.25 kV
1 For input differential voltages greater than 0.6 V, limit the input current to
less than 5 mA to prevent degradation or destruction of the input devices.
2 Applicable standard: MIL-STD-883, Method 3015.7.
3 Applicable standard: JESD22-A115-A (ESD machine model standard of
JEDEC).
4 Applicable standard: JESD22-C101-C (ESD FICDM standard of JEDEC).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device soldered on a 4-layer JEDEC
standard printed circuit board (PCB) with zero airflow.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
5-Lead SOT-23 (RJ-5) 219.4 155.6 °C/W
8-Lead SOIC_N (R-8) 121 43 °C/W
8-Lead MSOP (RM-8)
142
45
°C/W
8-Lead LFCSP (CP-8-11)1, 3 84 40 °C/W
14-Lead TSSOP (RU-14) 112 43 °C/W
16-Lead LFCSP (CP-16-17)2, 3
55 30 °C/W
1 Values are based on 4-layer (2S2P) JEDEC standard PCB, with four thermal
vias. Exposed pad soldered to PCB.
2 Values are based on 4-layer (2S2P) JEDEC standard PCB, with nine thermal
vias. Exposed pad soldered to PCB.
3 θJC measured on top of package.
ESD CAUTION
D2
D101
D100
D5 D4
D1
Q1
Q4 Q3
Q24
Q21 D20
Q13
Q18
Q19
Q23
Q2
FOLDED
CASCADE
V
EE
V
OUT
V
CC
V
BIAS
MIRROR
08237-002
R4
R5
R6
R7 C2
C1
R1 R2
R3
Figure 2. Simplified Schematic
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 8 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NIC
1
–IN
2
+IN
3
V–
4
NIC
8
V+
7
OUT
6
NIC
5
NOTES
1. NI C = NOT INT E RNALL Y CONNECT E D.
ADA4084-1
TOP VIEW
(No t t o Scal e)
08237-101
Figure 3. ADA4084-1, 8-Lead SOIC (R)
Table 7. 8-Lead SOIC, ADA4084-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 NIC Not Internally Connected
2 −IN Negative Input
3 +IN Positive Input
4 V− Negative Supply
5 NIC Not Internally Connected
6 OUT Output
7 V+ Positive Supply
8
NIC
Not Internally Connected
OUT
1
V–
2
+IN
3
V+
5
ADA4084-1
–IN
4
08237-301
Figure 4. ADA4084-1, 5-Lead SOT-23 (RJ)
Table 8. 5-Lead SOT-23, ADA4084-1 Pin Function Descriptions
Pin No. Mnemonic Description
1
OUT
Output
2 V− Negative Supply
3 +IN Positive Input
4 −IN Negative Input
5 V+ Positive Supply
08237-104
NOTES
1. FOR THE LF CS P P ACKAGE,
THE EXPOSED PAD MUST BE
CONNE CTED T O V–.
+IN A
V–
OUT A
–IN A
–IN B
+IN B
V+
OUT B
3
4
1
2
6
5
8
7
ADA4084-2
TOP VIEW
(Not to Scal e)
Figure 5. ADA4084-2, 8-Lead LFCSP (CP)
Table 9. 8-Lead LFCSP, ADA4084-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT A Output, Channel A
2 −IN A Negative Input, Channel A
3 +IN A Positive Input, Channel A
4 V− Negative Supply
5 +IN B Positive Input, Channel B
6 −IN B Negative Input, Channel B
7 OUT B Output, Channel B
8 V+ Positive Supply
EPAD Exposed Pad. For the LFCSP package, the exposed pad must be connected to V−.
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 9 of 36
08237-302
+IN A
V–
OUT A
–IN A
–IN B
+IN B
V+
OUT B
1
2
3
4
8
7
6
5
ADA4084-2
TOP VIEW
(Not to Scale)
Figure 6. ADA4084-2, 8-Lead MSOP (RM)
08237-303
OUT A 1
–IN A 2
+IN A 3
V– 4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4084-2
TOP VIEW
(Not to Scale)
Figure 7. ADA4084-2, 8-Lead SOIC (R)
Table 10. 8-Lead MSOP, 8-Lead SOIC, ADA4084-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT A Output, Channel A
2 −IN A Negative Input, Channel A
3 +IN A Positive Input, Channel A
4 V− Negative Supply
5 +IN B Positive Input, Channel B
6 −IN B Negative Input, Channel B
7 OUT B Output, Channel B
8 V+ Positive Supply B
OUT B
+IN B
–IN B
V+
–IN A
+IN A
OUT A
OUT C
+IN C
–IN C
V–
–IN D
+IN D
OUT D
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ADA4084-4
TOP VIEW
(Not to Scale)
0
8237-102
Figure 8. ADA4084-4, 14-Lead TSSOP (RU)
Table 11. 14-Lead TSSOP, ADA4804-4 Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT A Output, Channel A
2 −IN A Negative Input, Channel A
3 +IN A Positive Input, Channel A
4 V+ Positive Supply
5 +IN B Positive Input, Channel B
6 −IN B Negative Input, Channel B
7 OUT B Output, Channel B
8 OUT C Output, Channel C
9 −IN C Negative Input, Channel C
10 +IN C Positive Input, Channel C
11 V− Negative Supply
12 +IN D Positive Input, Channel D
13 −IN D Negative Input, Channel D
14 OUT D Output, Channel D
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 10 of 36
12
11
10
1
3
4
–IN D
+I N D
V–
9+I N C
–IN A
V+
2
+I N A
+I N B
6OUT B
5–IN B
7OUT C
8
–IN C
16 NIC
15 OUT A
14 OUT D
13 NIC
TOP
VIEW
ADA4084-4
NOTES
1. NIC = NOT INT E RNALL Y CONNECT E D.
2. FOR THE LF CSP PACKAGE, THE EXPOSED PAD
MUST BE CO NNE CTED TO V –.
08237-103
Figure 9. ADA4084-4, 16-Lead LFCSP (CP)
Table 12. 16-Lead LFCSP, ADA4084-4 Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN A Negative Input Channel A
2 +IN A Positive Input, Channel A
3 V+ Positive Supply
4 +IN B Positive Input, Channel B
5 −IN B Negative Input, Channel B
6 OUT B Output, Channel B
7 OUT C Output, Channel C
8 −IN C Negative Input, Channel C
9 +IN C Positive Input, Channel C
10
V−
Negative Supply
11 +IN D Positive Input, Channel D
12 −IN D Negative Input, Channel D
13 NIC Not Internally Connected
14 OUT D Output, Channel D
15 OUT A Output, Channel A
16
NIC
Not Internally Connected
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 11 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
±1.5 V CHARACTERISTICS
120
0
–100 –50 500100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
20
40
60
80
100
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
–25 25–75 75
08237-003
Figure 10. Input Offset Voltage (VOS) Distribution, SOIC
0
10
20
30
40
50
60
70
80
90
100
–100 –75 –50 –25 025 50 75 100
NUMBER O F AMPLIFIERS
V
OS
(µV)
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
08237-306
Figure 11. Input Offset Voltage (VOS) Distribution, SOT-23
50
0
–100 –50 –25 25–75 75500100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
5
10
15
20
25
30
35
40
45
08237-004
Figure 12. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
0
50
100
150
200
–200 –150 –100 –50 050 100
NUMBER OF AMPLIFIERS
V
OS
(µV)
08237-081
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
Figure 13. Input Offset Voltage (VOS) Distribution, LFCSP
60
002.0
NUMBER O F AMP LI FI E RS
TCV
OS
(µV/°C)
V
SY
= ±1. 5V
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
10
20
30
40
50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
08237-005
Figure 14. TCVOS Distribution, SOIC, MSOP, and TSSOP
0
2
4
6
8
10
12
14
16
18
20
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
NUMBER O F AMPLIFIERS
TCV
OS
(µV/°C)
V
SY
= ±1. 5V
R
L
= ∞
–40°C ≤T
A
≤+125°C
08237-309
Figure 15. TCVOS Distribution, SOT-23