HT83XXX Q-VoiceTM Preliminary Features * Operating voltage: 2.4V~5.0V * Watchdog Timer * Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz) * Low voltage reset * 4-level subroutine nesting system clock * System clock: 4MHz~8MHz (2.4V) * HALT function and wake-up feature reduce power * RC oscillator for system clock consumption * PWM circuit direct drive speaker or output by * Eight I/O pins transistor * 2K14-bit program ROM * 32-pin DIP package * 808-bit RAM * Two 8-bit programmable timer counter and one time base counter Applications * Intelligent educational leisure products * Sound effect generators * Alert and warning systems General Description The HT83XXX is excellent for versatile voice and sound effect product applications. The efficient MCU instructions allow users to program the powerful custom applications. The system frequency of HT83XXX can be up to 8MHz under 2.4V and include a HALT function to reduce power consumption. The HT83XXX series are 8-bit high performance microcontroller with voice synthesizer and tone generator. The HT83XXX is designed for applications on multiple I/Os with sound effects, such as voice and melody. It can provide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator. Low voltage detection is provided to reset under 2.2V or 3.3V. Selection Table Body Voice ROM size Voice length Rev. 0.00 HT83003 HT83006 HT83009 HT83018 HT83036 HT83048 HT83072 64K-bit 128K-bit 192K-bit 384K-bit 768K-bit 1024K-bit 1536K-bit 3 sec 6 sec 9 sec 18 sec 36 sec 48 sec 72 sec 1 February 19, 2003 Preliminary HT83XXX Block Diagram S T A C K 0 In te r r u p t C ir c u it S T A C K 1 P ro g ra m R O M S T A C K 2 P ro g ra m C o u n te r In s tr u c tio n R e g is te r M U X T M R 1 D A T A M e m o ry S Y S C L K /4 T M R 1 C 8 - b it T im e B a s e S h ifte r P A C P O R T A P A 0 ~ P A 7 P A O S R E V D V S S D S S Y S C L K /4 S Y S C L K /1 0 2 4 S T A T U S A L U T im in g G e n e r a tio n 8 - b it IN T C M U X In s tr u c tio n D e c o d e r S Y S C L K /4 T M R 0 C S T A C K 3 M P 0 T M R 0 C 1 A C C H A L T W D T S M W D T P r e s c a le r E N /D IS 2 5 6 U X W D T R C O S C S Y S C L K /4 L V D /L V R L a tc h C o u n te r In te rfa c e S Y S C L K P W M S Y S C L K Rev. 0.00 8 -s ta g e P r e s c a le r P W M 1 P W M 2 2 February 19, 2003 Preliminary HT83XXX Pin Assignment N C 1 3 2 N C N C 2 3 1 N C N C 3 3 0 N C N C 4 2 9 N C N C 5 2 8 N C N C 6 2 7 N C N C 7 2 6 P W M 2 N C 8 2 5 P W M 1 N C 9 2 4 V C C A 1 N C 1 0 2 3 V C C 2 2 G N D P A 0 1 1 P A 1 1 2 2 1 G N D A 1 P A 2 1 3 2 0 O S C 1 P A 3 1 4 1 9 R E S P A 4 1 5 1 8 P A 7 P A 5 1 6 1 7 P A 6 H T 8 3 0 0 3 /H T 8 3 0 0 6 /H T 8 3 0 0 9 /H T 8 3 0 1 8 H T 8 3 0 3 6 /H T 8 3 0 4 8 /H T 8 3 0 7 2 3 2 D IP -A Pad Assignment HT83003/HT83006/HT83009 (0 ,0 ) P A 1 P A 2 P A 3 P A 4 P A 5 8 9 1 0 P W M 1 V C C A 1 1 1 1 2 1 3 V C C P A 0 7 1 5 1 4 G N D 6 P W M 2 G N D A 1 5 O S C 1 4 R E S 3 P A 7 2 P A 6 1 1 6 Chip size: 2220 1355 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 0.00 3 February 19, 2003 Preliminary HT83XXX HT83018/HT83036 (0 ,0 ) 1 2 3 4 5 7 6 8 9 1 6 P W M 2 1 5 P W M 1 1 4 V C C A 1 1 1 1 2 1 3 1 0 V C C G N D G N D A 1 O S C 1 R E S P A 7 P A 6 P A 5 P A 4 P A 3 P A 2 P A 1 P A 0 Chip size: 2220 1660 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. HT83048/HT83072 (0 ,0 ) 1 2 3 4 5 6 7 8 1 6 P W M 2 1 5 1 4 P W M 1 V C C A 1 1 1 1 2 1 3 9 V C C G N D G N D A 1 O S C 1 R E S P A 7 P A 6 P A 5 P A 4 P A 3 P A 2 P A 1 P A 0 Chip size: 2220 2335 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 0.00 4 February 19, 2003 Preliminary HT83XXX Pad Coordinates HT83003/HT83006/HT83009 Pad No. X Y Pad No. X Y 1 -982.145 -508.050 9 -135.205 -508.050 2 -876.845 -508.050 10 3 -766.245 -508.050 11 -31.229 758.645 -490.400 4 -666.245 -508.050 12 858.645 -490.400 5 -555.645 -508.050 13 958.645 -490.400 6 -455.645 -508.050 14 841.895 -345.550 7 -345.045 -508.050 15 841.895 -224.050 8 -245.045 -508.050 16 841.895 -85.450 Pad No. X Y Pad No. X Y 1 -982.145 -660.550 9 -135.205 -660.550 2 -876.845 -660.550 10 -660.550 -642.900 -508.050 HT83018/HT83036 3 -766.245 -660.550 11 -31.229 758.645 4 -666.245 -660.550 12 858.645 -642.900 5 -555.645 -660.550 13 958.645 -642.900 6 -455.645 -660.550 14 841.895 -498.050 7 -345.045 -660.550 15 841.895 -376.550 8 -245.045 -660.550 16 841.895 -237.950 Pad No. X Y Pad No. X Y 1 -982.145 -998.050 9 -135.205 -998.050 2 -876.845 -998.050 10 -998.050 -980.400 HT83048/HT83072 3 -766.245 -998.050 11 -31.229 758.645 4 -666.245 -998.050 12 858.645 -980.400 5 -555.645 -998.050 13 958.645 -980.400 6 -455.645 -998.050 14 841.895 -835.550 7 -345.045 -998.050 15 841.895 -714.050 8 -245.045 -998.050 16 841.895 -575.450 Pin Description Pad Name I/O Mask Option Description PA0~PA7 I/O Wake-up, Pull-high or None Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input by mask option. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (mask option). GND 3/4 3/4 Negative power supply, ground VDD 3/4 3/4 Positive power supply GNDA1 3/4 3/4 PWM negative power supply, ground VDDA1 3/4 3/4 PWM positive power supply, ground I 3/4 Schmitt trigger reset input, active low OSC1 3/4 RC OSC1 is connected to an RC network for the internal system clock. PWM1, PWM2 O 3/4 PWM output for driving a external transistor or speaker RES Rev. 0.00 5 February 19, 2003 Preliminary HT83XXX Absolute Maximum Ratings Supply Voltage ..........................VSS+2.4V to VSS+5.2V Storage Temperature ...........................-50C to 125C Input Voltage .............................VSS-0.3V to VDD+0.3V Operating Temperature ..........................-20C to 70C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Test Conditions VDD Conditions 3/4 Min. Typ. Max. Unit 2.4 3/4 5.2 V mA VDD Operating Voltage 3/4 ISTB Standby Current 3V No load, system HALT 3/4 1 3/4 IDD Operating Current 3V No load, fSYS=4MHz 3/4 1.2 1.5 mA IOL I/O Port Sink Current 3V VOL=0.3V 17 3/4 3/4 mA IOH I/O Port Source Current 3V VOH=2.7V -12 3/4 3/4 mA IO PWM Source Current 3V VOL=0.3V 121 3/4 3/4 mA VOH=2.7V IO PWM Source Current 3V -81 3/4 3/4 mA VIL1 Input Low Voltage (RES) 3V 3/4 3/4 1.5 3/4 V VIH1 Input High Voltage (RES) 3V 3/4 3/4 2.2 3/4 V fSYS 4.0 4.5 3V ROSC=100kW 3.7 System Frequency ROSC=62kW 7.4 8.0 8.6 Min. Typ. Max. Unit MHz A.C. Characteristics Symbol Parameter Test Conditions VDD Conditions fSYS System Clock (RC OSC) 3V 3/4 4 3/4 8 MHz fTIMER Timer Input Frequency 3V 3/4 0 3/4 8 MHz tWDTOSC Watchdog Oscillator 3V 3/4 45 90 180 ms tWDT Watchdog Time-out Period (RC) 3V 12 23 45 ms tRES External Reset Low Pulse Width 3/4 3/4 1 3/4 3/4 ms tSST System Start-up Timer Period 3/4 Power-up or wake-up from HALT 3/4 1024 3/4 tSYS Rev. 0.00 Without WDT prescaler 6 February 19, 2003 Preliminary HT83XXX Functional Description incremented by one. The program counter then points to the memory word containing the next instruction code. Execution Flow The system clock for the HT83XXX series is derived from either a crystal or an RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter - PC The 13-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed. The lower byte of the program counter (PCL) is a read/write register (06H). Moving data into the PCL performs a short jump. The destination must be within 256 locations. After accessing a program memory word to fetch an instruction code, the contents of the program counter are When a control transfer takes place, an additional dummy cycle is required. S y s te m C lo c k T 1 T 2 T 3 T 4 T 1 T 2 P C P C T 3 T 4 T 1 T 2 P C + 1 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) T 3 T 4 P C + 2 F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution flow Mode Program Counter *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 Time Base Overflow 0 0 0 0 0 0 0 0 0 0 1 0 0 Timer Counter 0 Overflow 0 0 0 0 0 0 0 0 0 1 0 0 0 Timer Counter 1 Overflow 0 0 0 0 0 0 0 0 0 1 1 0 0 Skip PC+2 Loading PCL *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program counter Note: *12~*0: Program counter bits S12~S0: Stack register bits #12~#0: Instruction code bits Rev. 0.00 @7~@0: PCL bits 7 February 19, 2003 Preliminary HT83XXX Program Memory - ROM Table Location The program memory stores the program instructions that are to be executed. It also includes data, table and interrupt entries, addressed by the program counter along with the table pointer. The program memory size for HT83XXX is 204814 bits. Certain locations in the program memory are reserved for special usage: Any location in the ROM space can be used as look up tables. The instructions TABRDC [m] (used for any bank) and TABRDL [m] (only used for last page of program ROM) transfer the contents of the lower-order byte to the specified data memory [m], and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined. The higher-order bytes of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. * Location 000H This area is reserved for program initialization. The program always begins execution at location 000H each time the system is reset. The table pointer (TBLP) is a read/write register, which indicates the table location. * Location 004H This area is reserved for the time base interrupt service program. If the ETBI (intc.1) is activated, and the interrupt is enabled and the stack is not full, the program will jump to location 004H and begins execution. Stack Register - Stack The stack register is a special part of the memory used to save the contents of the program counter (PC). This stack is organized into four levels. It is neither part of the data nor part of the program space, and cannot be read or written to. Its activated level is indexed by a stack pointer (SP) and cannot be read or written to. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. * Location 008H This area is reserved for the 8-bit timer counter 0 interrupt service program. If a timer interrupt results from a timer counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 008H and begins execution. * Location 00CH The program counter is restored to its previous value from the stack at the end of subroutine or interrupt routine, which is signaled by return instruction (RET or RETI). After a chip resets, SP will point to the top of the stack. This area is reserved for the 8-bit timer counter 1 interrupt service program. If a timer interrupt results from a timer counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 00CH and begins execution. 0 0 0 0 H 0 0 0 4 H 0 0 0 8 H 0 0 0 C H The interrupt request flag will be recorded but the acknowledgment will be inhibited when the stack is full and a non-masked interrupt takes place. After the stack pointer is decremented (by RET or RETI), the interrupt request will be serviced. This feature prevents stack overflow and allows programmers to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry is lost. In itia l A d d r e s s T im e B a s e In te r r u p t S u b r o u tin e T im e r 0 In te r r u p t S u b r o u tin e P ro g ra m R O M T im e r 1 In te r r u p t S u b r o u tin e 0 0 1 5 H 0 7 F F H Program memory Instruction Table Location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] 0 0 0 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table location Note: *10~*0: Current program ROM table Rev. 0.00 @7~@0: Write @7~@0 to TBLP pointer register 8 February 19, 2003 Preliminary Data Memory - RAM The data memory is designed with 808 bits. The data memory is further divided into two functional groups, namely, special function registers (00H~2AH) and general purpose user data memory (30H~7FH). Although most of them can be read or be written to, some are read only. HT83XXX 0 0 H R 0 0 1 H M P 0 0 2 H 0 3 H 0 4 H 0 5 H A C C 0 6 H P C L 0 7 H T B L P 0 8 H The special function registers include an indirect addressing register (R0:00H), memory pointer register (MP0:01H), accumulator (ACC:05H), program counter lower-order byte register (PCL:06H), table pointer (TBLP:07H), table higher-order byte register (TBLH:08H), status register (STATUS:0AH), interrupt control register 0 (INTC:0BH), timer counter 0 (TMR0:0DH), timer counter 0 control register (TMR0C:0EH), timer counter 1 (TMR1L:10H), timer counter 1 control register (TMR1C:11H), I/O registers (PA:12H), I/O control registers (PAC:13H), voice ROM address latch0[21:0] (LATCH0H:18H, LATCH0M:19H, LATCH0L:1AH), time base control bit EBTI (INTC.1), PWM control register (PWMCR:26H), PWM output (PWMD:28H), voice ROM latch data register (LATCHD:2AH). T B L H 0 9 H W D T S 0 A H S T A T U S 0 B H IN T C 0 C H 0 D H T M R 0 T M R 0 C 0 E H 0 F H 1 0 H T M R 1 1 1 H T M R 1 C 1 2 H P A 1 3 H P A C 1 4 H 1 5 H 1 6 H 1 7 H The general purpose data memory, addressed from 30H~7FH, is used for data and control information under instruction commands. 1 8 H L A T C H 0 H 1 9 H L A T C H 0 M 1 A H L A T C H 0 L 1 B H S p e c ia l P u r p o s e D A T A M E M O R Y 1 C H 1 D H 1 E H The areas in the RAM can directly handle the arithmetic, logic, increment, decrement and rotate operations. Except some dedicated bits, each bit in the RAM can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the Memory Pointer register 0 (MP0:01H). 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H P W M C R 2 7 H 2 8 H P W M D 2 9 H 2 A H L A T C H D 2 B H : U n u s e d . R e a d a s "0 " 2 F H 3 0 H G e n e ra l P u rp o s e D a ta M e m o ry 7 F H RAM mapping Address RAM Mapping Read/Write Description 00H R0 R/W Indirect addressing register 0 01H MP0 R/W Memory pointer 0 05H ACC R/W Accumulator 06H PCL R/W Program counter lower-order byte address 07H TBLP R/W Table pointer lower-order byte register 08H TBLH R Table higher-order byte content register 09H WDTS R/W Watchdog Timer option setting register Rev. 0.00 9 February 19, 2003 Preliminary Address RAM Mapping Read/Write HT83XXX Description 0AH STATUS R/W Status register 0BH INTC R/W Interrupt control register 0 0DH TMR0 R/W Timer counter 0 register 0EH TMR0C R/W Timer counter 0 control register 10H TMR1 R/W Timer counter 1 register 11H TMR1C R/W Timer counter 1 control register 12H PA R/W Port A I/O data register 13H PAC R/W Port A I/O control register 18H LATCH0H R/W Voice ROM address latch 0 [A21~A16] 19H LATCH0M R/W Voice ROM address latch 0 [A15~A8] 1AH LATCH0L R/W Voice ROM address latch 0 [A7~A0] 26H PWMCR R/W PWM control register 28H PWMD R/W PWM output data D7~D0 2AH LATCHD R Voice ROM data register 2BH~2FH Unused 30H~7FH User data RAM Note: R/W User data RAM R: Read only W: Write only R/W: Read/Write Indirect Addressing Register Status Register - STATUS (0AH) Location 00H is indirect addressing registers that are not physically implemented. Any read/write operation of [00H] accesses the RAM pointed to by MP0 (01H) respectively. Reading location 00H indirectly returns the result 00H. While, writing it indirectly leads to no operation. This 8-bit STATUS register (0AH) consists of a zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except the TO and PD flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PD flags. Operations related to the status register, however, may yield different results from those intended. The TO and PD flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. Accumulator - ACC (05H) The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions: On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. * Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc) Rev. 0.00 10 February 19, 2003 Preliminary Labels HT83XXX Bits Function C 0 C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC 1 AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z 2 Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV 3 OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD 4 PD is cleared by system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO 5 TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. 3/4 6, 7 Unused bit, read as 0 Status register T1F bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. Interrupts The HT83XXX provides two 8-bit programmable timer interrupts, and a time base interrupt. The Interrupt Control registers (INTC:0BH) contain the interrupt control bits to set to enable/disable and the interrupt request flags. Time Base Interrupt is triggered by set INTC.1 (ETBI) which sets the related interrupt request flag (TBF:bit 4 of INTC). When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (TBF) and EMI bits will be cleared to disable other interrupts. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI bit and the corresponding INTC bit may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. During the execution of an interrupt subroutine, other interrupt acknowledgment are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at the specified location(s) in the program memory. Only the program counter is pushed onto the stack. The programmer must save the contents of the register or status register (STATUS) in advance if they are altered by an interrupt service program which corrupts the desired control sequence. The Internal Timer Counter 0 Interrupt is initialized by setting the timer counter 0 interrupt request flag (T0F:bit 5 of INTC), caused by a timer counter 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The timer counter 0/1 interrupt request flag (T0F/T1F) which enables timer counter 0/1 control bit (ET0I/ET1I), the time base interrupt request flag (TBF) which enables time base control bit (ETTBI) from the interrupt control register (INTC:0BH) EMI, ETBI, ET0I, ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt begin serviced. Once the interrupt request flags (T0F, T1F, TBF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. The Internal Timer Counter 1 Interrupt is initialized by setting the timer counter 1 interrupt request flag (T1F:bit 6 of INTC), caused by a timer counter 1 overflow. When the interrupt is enabled, and the stack is not full and the It is recommended that application programs do not use CALL subroutines within an interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only Rev. 0.00 11 February 19, 2003 Preliminary HT83XXX one stack is left and the interrupt enable is not well controlled, once a CALL subroutine if used in the interrupt subroutine will corrupt the original control sequence. Register INTC (0BH) Bit No. Label Function 0 EMI 1 ETBI Controls the time base interrupt (1= enabled; 0= disabled) 2 ET0I Controls the timer 0 interrupt (1= enabled; 0= disabled) 3 ET1I Controls the timer 1 interrupt (1= enabled; 0= disabled) 4 TBF Time base interrupt request flag (1= active; 0= inactive) 5 T0F Timer 0 request flag (1= active; 0= inactive) 6 T1F Timer 1 request flag (1= active; 0= inactive) 7 3/4 Controls the master (global) interrupt (1= enabled; 0= disabled) Unused bit, read as 0 INTC0 register Interrupt Source Priority Vector Time Base Interrupt 1 04H Timer Counter 0 Overflow 2 08H Timer Counter 1 Overflow 3 0CH Oscillator Configuration Watchdog Timer - WDT The HT83XXX provides RC oscillator circuit for the system clock. The signal is used for the system clock. The HALT mode stops the system oscillator to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 62kW to 100kW. The system clock, divided by 4. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore not suitable for timing sensitive operations where accurate oscillator frequency is desired. The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with period 78ms normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out period can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of WDTS(09H)) can give different time-out period. O S C 1 R C If WS2, WS1, WS0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. O s c illa to r System oscillator Rev. 0.00 If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. 12 February 19, 2003 Preliminary S y s te m HT83XXX C lo c k /4 M a s k O p tio n S e le c t W D T O S C W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r 8 -to -1 M U X W S 0 ~ W S 2 W D T T im e - o u t Watchdog Timer The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm re set only the PC and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler), three methods are adopted; external reset (external reset (a low level to RES), software instructions, or a HALT instruction. The software instruction is CLR WDT and execution of the CLR WDT instruction will clear the WDT. WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 Division Ratio 3/4 3/4 3/4 3/4 3/4 0 0 0 1:1 3/4 3/4 3/4 3/4 3/4 0 0 1 1:2 3/4 3/4 3/4 3/4 3/4 0 1 0 1:4 3/4 3/4 3/4 3/4 3/4 0 1 1 1:8 3/4 3/4 3/4 3/4 3/4 1 0 0 1:16 3/4 3/4 3/4 3/4 3/4 1 0 1 1:32 3/4 3/4 3/4 3/4 3/4 1 1 0 1:64 3/4 3/4 3/4 3/4 3/4 1 1 1 1:128 WDTS register Power Down - HALT The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled by the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. The HALT mode is initialized by a HALT instruction and results in the following: * The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected). * The contents of the on chip RAM and registers remain unchanged. * WDT and WDT prescaler will be cleared and recount again. * All I/O ports maintain their original status. Once a wake-up event occurs, it takes 1024 system clock period to resume normal operation. In other words, a dummy cycle period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next instruction execution, this will be executed immediately after a dummy period is finished. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. * The PD flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. By examining the TO and PD flags, the reason for the chip reset can be determined. The PD flag is cleared when the system powers-up or executes the CLR WDT instruction, and is set when the HALT instruction is executed. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the PC and SP. The other maintain their original status. Rev. 0.00 13 February 19, 2003 Preliminary Reset HT83XXX H A L T There are 3 ways in which a reset can occur: R e s e t T im e - o u t R e s e t * RES reset during normal operation * RES reset during HALT W a rm W D T W D T R E S * WDT time-out reset during normal operation The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during any other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PD flag and TO flag, the program can distinguish between different chip resets. C o ld R e s e S S T 1 0 -s ta g e R ip p le C o u n te r O S C I P o w e r - o n D e te c tin g Reset configuration The functional unit chip reset status are shown below. RESET Conditions PC 000H Interrupt Disable Prescaler Clear TO PD 0 0 RES reset during power-up u u RES reset during normal operation 0 1 RES wake-up HALT WDT Clear. After master reset, WDT begins counting 1 u WDT time-out during normal operation Timer counter Off 1 1 WDT wake-up HALT Input/output ports Input mode SP Points to the top of the stack Note: u stands for unchanged To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses after a system power up or when awakening from a HALT state. Timer Counter 0/1 The TMR0/TMR1 is internal clock source only, i.e. (TM1, TM0)=(1,0). There is a 3-bit prescaler (TMRS2, TMRS1, TMRS0) which defines different division ratio of TMR0/TMR1s clock source. When a system power up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay. Label tS S T S S T T im e - o u t C h ip R e s e t Reset timing chart V Function Defines the operating clock source (TMRS2, TMRS1, TMRS0) 000: clock source/2 001: clock source/4 TMRS2, 010: clock source/8 TMRS1, 0~2 011: clock source/16 TMRS0 100: clock source/32 101: clock source/64 110: clock source/128 111: clock source/256 V D D R E S Bits D D TE 3 Defines the TMR0/TMR1 active edge of timer counter TON 4 Enable/disable timer counting (0=disabled; 1=enabled) 3/4 5 Unused bit, read as 0 TM0, TM1 6 7 Defines the operating mode (TM1, TM0) R E S TMR0C/TMR1C register Reset circuit Note: TMR0C/TMR1C bit 3 always write 0 TMR0C/TMR1C bit 5 always write 0 TMR0C/TMR1C bit 6 always write 1 TMR0C/TMR1C bit 7 always write 0 Rev. 0.00 14 February 19, 2003 Preliminary The TMR0/1 is internal clock source only. There is a 3-bit prescaler (TMRS2, TMRS1, TMRS0) which defines different division ratio of TMR0/1s clock source. The TMR0C is the timer counter 0 control register, which defines the timer counter 0 options. The timer counter 1 has the same options as the timer counter 0 and is defined by TMR1C. Time Base To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C/TMR1C) should be set to 1. The overflow of the timer counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service. The time base enables the counting operation by INTC.1 (ETBI) bit. The overflow to interrupt as set INTC.1. The time base is internal clock source only. Time base of 1ms to overflow as system clock is 4MHz. Time base of 0.5ms to overflow as system clock is 8MHz. (T M R S 2 , T M R S 1 , T M R S 0 ) S y s te m C lo c k HT83XXX D a ta B u s 8 -S ta g e P r e s c a le r T im e r C o u n te r 0 /1 P r e lo a d R e g is te r R e lo a d T O N O v e r flo w to In te rru p t T im e r C o u n te r 0 /1 Timer counter 0/1 S y s te m C lo c k /4 1 0 2 4 O v e r flo w to In te rru p t Time base The registers states are summarized in the following table. Register Reset (Power On) PC WDT Time-out RES Reset (Normal Operation) (Normal Operation) RES Reset (HALT) WDT Time-out (HALT) 0000H 0000H 0000H 0000H 0000H MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR0C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- TMR1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR1C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- LATCH0H ---- --xx ---- --uu ---- --uu ---- --uu ---- --uu LATCH0M xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu LATCH0L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PWMCR -00- 00-0 -uu- uu-u -uu- uu-u -uu- uu-u -uu- uu-u PWMD xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu LATCHD xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Note: u means unchanged; x means unknown; - means undefined Rev. 0.00 15 February 19, 2003 Preliminary Low Voltage Reset - LVR HT83XXX read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within 2.2V or 3.3V (by mask option), such as changing a battery, the LVR will automatically reset the device internally. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H) instructions. Input/Output Ports There are 8 bidirectional input/output lines in the microcontroller, labeled from PA, which are mapped to the data memory of [12H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A, [m] (m=12H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each I/O line has its own control register (PAC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will Each line of port A has the capability of waking-up the device. The wake-up capability of port A is determined by mask option. There is a pull-high option available for all I/O lines. Once the pull-high option is selected, all I/O lines have pull-high resistors. Otherwise, the pull-high resistors are absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. V D Q D a ta B u s C K W r ite C o n tr o l R e g is te r Q S V C h ip R e s e t D P A 0 ~ P A 7 P B 0 ~ P B 7 P C 0 ~ P C 7 Q C K S Q M R e a d I/O S y s te m W e a k P u ll- u p M a s k O p tio n R e a d C o n tr o l R e g is te r W r ite I/O D D D D U X W a k e - U p ( P A o n ly ) M a s k O p tio n Input/output ports Rev. 0.00 16 February 19, 2003 Preliminary HT83XXX Audio Output - PWMD (28H) The HT83XXX provides one 8-bit PWM interface for driving an external 8W speaker. The programmer must write the voice data to register PWMD (28H) Pulse Width Modulation Control Register - PWMCR (26H) Bit 7 Bit 6 (R/W) Bit 5 (R/W) Bit 4 Bit 3 (R/W) Bit 2 (R/W) Bit 1 Bit 0 (R/W) 3/4 P1 P0 3/4 Single_PWM VROMC 3/4 PWMC PWMC: Start bit of PWM output * PWM start counter: 0 to 1 PWM2 and the PWM1 will get a GND level voltage after setting start bit to 1. * PWM stop counter: 1 to 0 PWM output Initial low level , and stop in low level After waiting one cycle end , stop the PWM counter and keep in low signal If PWMC from low to high then start PWM output and 5kHz/6kHz/8kHz latch new data , if no update then keep the old value. VROMC: Enable voice ROM power circuit (1=enable; 0=disable) If PWMC from high to low, in duty end, stop PWM output and stop the counter. Single_PWM: Driving PWM signal only by PWM1 port. (1=enable; 0=disable) Voice ROM Data Address Latch Counter The HT83xxx provides an 8-bit (bit 7 is a sign bit, if Single_PWM = 0) PWM interface. The PWM provides two pad outputs: PWM1, PWM2 which can directly drive a piezo or a 8W speaker without adding any external element (green mode), or using only port PWM1 (Set Single_PWM = 1) to drive piezo or a 8W speaker with external element. When Setting Single_PWM = 1, choose voice data7~data1 as the output data (no sign bit on it). The voice ROM data address latch counter is the handshaking between the microcontroller and voice ROM, where the voice codes are stored. One 8-bit of voice ROM data will be addressed by setting 21-bit address latch counter LATCH0H/LATCH0M/LATCH0L. After the 8-bit voice ROM data is addressed, a few instruction cycles (4ms at least) will be generated to latch the voice ROM data, then the microcontroller can read the voice data from LATCHD (2AH). Setting data to P0 and P1 can generate various sampling rates (5kHz/6kHz/8kHz): Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0 P1 P0 Sampling Carrier Preload PWM Code Rate frequency Times Range set [26H].2 ; Enable voice ROM circuit mov A, 07H ; 0 0 5kHz 30kHz 6 0~127 mov LATCH0L, A ; Set LATCH0L to 07H 0 1 6kHz 30kHz 5 0~127 mov A, 00H 1 0 8kHz 32kHz 4 0~124 mov LATCH0M, A ; Set LATCH0M to 00H mov A, 00H mov LATCH0H, A ; Set LATCH0H to 00H call Delay Time ; Delay a short period of time mov A, LATCHD ; Get voice data at 000007H 3/4 3/4 X X X X If the sign bit is 0, then the signal is output to PWM1and the PWM2 will get a GND level voltage after setting start bit to 1. If the sign bit is 1, then the signal is output to ; ; D a ta B u s S y s te m c lo c k F 0 S ta r t b it 2 6 H .0 P W M I P W M D a ta B u ffe r (2 8 H ) P r e s c a le r D iv . F 2 F 1 C K P E B it7 ( s ig n b it) 7 B its C o u n te r ( B it6 ~ B it0 ) O v e r flo w V D D D Q C K Q R P W M D A C 1 fo r S P E A K E R P W M D A C 2 fo r S P E A K E R PWM Rev. 0.00 17 February 19, 2003 Preliminary HT83XXX Mask Option Mask Option Description PA Wake-up Enable or disable PA wake-up function Watchdog Timer (WDT) Enable or disable WDT function One or two CLR instruction WDT clock source is from WDTOSC or T1 Low Voltage Reset (LVR) Enable or disable low voltage reset Low voltage reset at 2.2V or 3.3V PA Pull-high Enable or disable PA pull-high fOSC - ROSC Table (VDD=5V) Rev. 0.00 fOSC ROSC 4MHz10% 6MHz10% 8MHz10% 100kW 75kW 62kW 18 February 19, 2003 Preliminary HT83XXX Application Circuits V D D V D D O S C 1 R (1 0 0 k W ~ 6 2 k W ) V D D V C C A 1 4 7 m F R E S 0 .1 m F C G N D A 1 P A 0 ~ P A 7 S p e a k e r P W M 1 P W M 2 G N D (8 /1 6 ) H T 8 3 X X X Single PWM Mode V D D V D D O S C 1 R V (1 0 0 k W ~ 6 2 k W ) D D V C C A 1 4 7 m F R E S 0 .1 m F C G N D A 1 V D D S p e a k e r (8 /1 6 ) P A 0 ~ P A 7 P W M 1 P W M 2 G N D Q 2 N P N B C E H T 8 3 X X X Note: * For normal application, a capacitor C is not necessary. However, if you want to extend the reset time , a 0.1mF capacitor can be placed on the RES pin. Rev. 0.00 19 February 19, 2003 Preliminary HT83XXX Package Information 32-pin DIP (600mil) Outline Dimensions A 1 7 3 2 B 1 6 1 H C D E Symbol Rev. 0.00 F a G I Dimensions in mil Min. Nom. Max. A 1635 3/4 1665 B 535 3/4 555 C 145 3/4 155 D 125 3/4 145 E 16 3/4 20 F 50 3/4 70 G 3/4 100 3/4 H 595 3/4 615 I 635 3/4 670 a 0 3/4 15 20 February 19, 2003 HT83XXX Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2003 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 0.00 21 February 19, 2003