HT83036 - Holtek Semiconductor

HT83XXX

Q-VoiceTM

Selection Table

Body HT83003 HT83006 HT83009 HT83018 HT83036 HT83048 HT83072

Voice ROM size 64K-bit 128K-bit 192K-bit 384K-bit 768K-bit 1024K-bit 1536K-bit

Voice length 3 sec 6 sec 9 sec 18 sec 36 sec 48 sec 72 sec

Rev. 0.00 1 February 19, 2003

Features

·Operating voltage: 2.4V~5.0V

·Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)

system clock

·System clock: 4MHz~8MHz (2.4V)

·RC oscillator for system clock

·Eight I/O pins

·2K´14-bit program ROM

·80´8-bit RAM

·Two 8-bit programmable timer counter and one time

base counter

·Watchdog Timer

·Low voltage reset

·4-level subroutine nesting

·HALT function and wake-up feature reduce power

consumption

·PWM circuit direct drive speaker or output by

transistor

·32-pin DIP package

Applications

·Intelligent educational leisure products

·Alert and warning systems

·Sound effect generators

General Description

The HT83XXX series are 8-bit high performance

microcontroller with voice synthesizer and tone genera-

tor. The HT83XXX is designed for applications on multi-

ple I/Os with sound effects, such as voice and melody. It

can provide various sampling rates and beats, tone lev-

els, tempos for speech synthesizer and melody genera-

tor. Low voltage detection is provided to reset under

2.2V or 3.3V.

The HT83XXX is excellent for versatile voice and sound

effect product applications. The efficient MCU instruc-

tions allow users to program the powerful custom appli-

cations. The system frequency of HT83XXX can be up

to 8MHz under 2.4V and include a HALT function to re-

duce power consumption.

Preliminary

Block Diagram

HT83XXX

Rev. 0.00 2 February 19, 2003

Preliminary

P r o g r a m

C o u n t e r

P r o g r a m

R O M

I n s t r u c t i o n

R e g i s t e r

I n s t r u c t i o n

D ecoder

T i m i n g

G e n e r a t i o n

O S C 1

R E S

V D D

V S S

I n t e r r u p t

C i r c u i t

I N T C

M P 0 MUX

M U X

D A T A

M e m o r y

A L U

S h i f t e r

S T A T U S

A C C

T M R 0

T M R 0 C

S Y S C L K / 4

8 - b i t

L V D / L V R

P A C

P A

P O R T A

PA0~PA7

L a t c h C o u n t e r

I n t e r f a c e

8 - s t a g e

P r e s c a l e r

S T A C K 2

S T A C K 3

S T A C K 0

S T A C K 1

S Y S C L K

S Y S C L K / 4

H A L T E N / D I S

T M R 1

T M R 1 C

S Y S C L K / 4

8 - b i t

T i m e B a s e S Y S C L K / 1 0 2 4

W D T S

W D T P r e s c a l e r

256

W D T R C

O S C

MUXS Y S C L K / 4

P W M

S Y S C L K

P W M 1

P W M 2

Pin Assignment

Pad Assignment

HT83003/HT83006/HT83009

Chip size: 2220 ´1355 (mm)2

* The IC substrate should be connected to VSS in the PCB layout artwork.

HT83XXX

Rev. 0.00 3 February 19, 2003

Preliminary

1 0

1 1

1 2

1 3

1 4

1 5

1 6

H T 8 3 0 0 3 / H T 8 3 0 0 6 / H T 8 3 0 0 9 / H T 8 3 0 1 8

H T 8 3 0 3 6 / H T 8 3 0 4 8 / H T 8 3 0 7 2

3 2 D I P - A

3 2

3 1

3 0

2 9

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

N C

P W M 2

P W M 1

V C C A 1

V C C

G N D A 1

G N D

O S C 1

R E S

P A 7

P A 6

N C

P A 0

P A 1

P A 2

P A 3

P A 4

P A 5

( 0 , 0 )

2345678 9 1 0 1 1 1 2 1 3

1 4

1 5

1 6

V C C

G N D

G N D A 1

O S C 1

R E S

P A 7

P A 6

P A 5

P A 4

P A 3

P A 2

P A 1

P A 0

P W M 2

P W M 1

V C C A 1

HT83018/HT83036

Chip size: 2220 ´1660 (mm)2

* The IC substrate should be connected to VSS in the PCB layout artwork.

HT83048/HT83072

Chip size: 2220 ´2335 (mm)2

* The IC substrate should be connected to VSS in the PCB layout artwork.

HT83XXX

Rev. 0.00 4 February 19, 2003

Preliminary

( 0 , 0 )

1 2 3 4 5 6 7 8 9 1 1 1 2 1 3

1 4

1 5

1 6 P W M 2

P W M 1

V C C A 1

V C C

G N D

G N D A 1

O S C 1

R E S

P A 7

P A 6

P A 5

P A 4

P A 3

P A 2

P A 1

P A 0

1 31 21 1

1 4

( 0 , 0 )

V C C

G N D

G N D A 1

O S C 1

R E S

P A 7

P A 6

P A 5

P A 4

P A 3

P A 2

P A 1

P A 0

1 2 3 4 5 6 7 8 9 1 0

1 5

1 6 P W M 2

P W M 1

V C C A 1

Pad Coordinates

HT83003/HT83006/HT83009

Pad No. X Y Pad No. X Y

1-982.145 -508.050 9-135.205 -508.050

2-876.845 -508.050 10 -31.229 -508.050

3-766.245 -508.050 11 758.645 -490.400

4-666.245 -508.050 12 858.645 -490.400

5-555.645 -508.050 13 958.645 -490.400

6-455.645 -508.050 14 841.895 -345.550

7-345.045 -508.050 15 841.895 -224.050

8-245.045 -508.050 16 841.895 -85.450

HT83018/HT83036

Pad No. X Y Pad No. X Y

1-982.145 -660.550 9-135.205 -660.550

2-876.845 -660.550 10 -31.229 -660.550

3-766.245 -660.550 11 758.645 -642.900

4-666.245 -660.550 12 858.645 -642.900

5-555.645 -660.550 13 958.645 -642.900

6-455.645 -660.550 14 841.895 -498.050

7-345.045 -660.550 15 841.895 -376.550

8-245.045 -660.550 16 841.895 -237.950

HT83048/HT83072

Pad No. X Y Pad No. X Y

1-982.145 -998.050 9-135.205 -998.050

2-876.845 -998.050 10 -31.229 -998.050

3-766.245 -998.050 11 758.645 -980.400

4-666.245 -998.050 12 858.645 -980.400

5-555.645 -998.050 13 958.645 -980.400

6-455.645 -998.050 14 841.895 -835.550

7-345.045 -998.050 15 841.895 -714.050

8-245.045 -998.050 16 841.895 -575.450

Pin Description

Pad Name I/O Mask Option Description

PA0~PA7 I/O

Wake-up,

Pull-high

or None

Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input

by mask option. Software instructions determine the CMOS output or

Schmitt trigger input with or without pull-high resistor (mask option).

GND ¾¾

Negative power supply, ground

VDD ¾¾

Positive power supply

GNDA1 ¾¾

PWM negative power supply, ground

VDDA1 ¾¾

PWM positive power supply, ground

RES I¾Schmitt trigger reset input, active low

OSC1 ¾RC OSC1 is connected to an RC network for the internal system clock.

PWM1, PWM2 O ¾PWM output for driving a external transistor or speaker

HT83XXX

Rev. 0.00 5 February 19, 2003

Preliminary

Absolute Maximum Ratings

Supply Voltage ..........................VSS+2.4V to VSS+5.2V Storage Temperature ...........................-50°Cto125°C

Input Voltage .............................VSS-0.3V to VDD+0.3V Operating Temperature ..........................-20°Cto70°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

D.C. Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD Conditions

VDD Operating Voltage ¾¾

2.4 ¾5.2 V

ISTB Standby Current 3V No load, system HALT ¾1¾mA

IDD Operating Current 3V No load, fSYS=4MHz ¾1.2 1.5 mA

IOL I/O Port Sink Current 3V VOL=0.3V 17 ¾¾

IOH I/O Port Source Current 3V VOH=2.7V -12 ¾¾

IOPWM Source Current 3V VOL=0.3V 121 ¾¾

IOPWM Source Current 3V VOH=2.7V -81 ¾¾

VIL1 Input Low Voltage (RES)3V ¾¾

1.5 ¾V

VIH1 Input High Voltage (RES)3V ¾¾

2.2 ¾V

fSYS System Frequency 3V ROSC=100kW3.7 4.0 4.5

MHz

ROSC=62kW7.4 8.0 8.6

A.C. Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD Conditions

fSYS System Clock (RC OSC) 3V ¾4¾8 MHz

fTIMER Timer Input Frequency 3V ¾0¾8 MHz

tWDTOSC Watchdog Oscillator 3V ¾45 90 180 ms

tWDT Watchdog Time-out Period (RC) 3V Without WDT prescaler 12 23 45 ms

tRES External Reset Low Pulse Width ¾¾ 1¾¾ms

tSST System Start-up Timer Period ¾Power-up or wake-up from

HALT ¾1024 ¾tSYS

HT83XXX

Rev. 0.00 6 February 19, 2003

Preliminary

HT83XXX

Rev. 0.00 7 February 19, 2003

Preliminary

Functional Description

Execution Flow

The system clock for the HT83XXX series is derived

from either a crystal or an RC oscillator. It is internally di-

vided into four non-overlapping clocks. One instruction

cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to effectively execute within one cycle. If an instruc-

tion changes the program counter, two cycles are

required to complete the instruction.

Program Counter -PC

The 13-bit program counter (PC) controls the sequence

in which the instructions stored in program ROM are ex-

ecuted.

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by one. The program counter then points

to the memory word containing the next instruction

code.

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call, initial re-

set, internal interrupt or return from subroutine, the PC

manipulates the program transfer by loading the ad-

dress corresponding to each instruction.

The conditional skip is activated by instruction. Once the

condition is met, the next instruction, fetched during the

current instruction execution, is discarded and a dummy

cycle takes its place while the correct instruction is ob-

tained.

The lower byte of the program counter (PCL) is a

read/write register (06H). Moving data into the PCL per-

forms a short jump. The destination must be within 256

locations.

When a control transfer takes place, an additional

dummy cycle is required.

Mode Program Counter

*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Initial Reset 0000000000000

Time Base Overflow 0000000000100

Timer Counter 0 Overflow 0000000001000

Timer Counter 1 Overflow 0000000001100

Skip PC+2

Loading PCL *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from Subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *12~*0: Program counter bits S12~S0: Stack register bits

#12~#0: Instruction code bits @7~@0: PCL bits

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C P C + 1 P C + 2

S y s t e m C l o c k

P C

Execution flow

HT83XXX

Rev. 0.00 8 February 19, 2003

Preliminary

Program Memory -ROM

The program memory stores the program instructions

that are to be executed. It also includes data, table and

interrupt entries, addressed by the program counter

along with the table pointer. The program memory size

for HT83XXX is 2048´14 bits. Certain locations in the

program memory are reserved for special usage:

·Location 000H

This area is reserved for program initialization. The

program always begins execution at location 000H

each time the system is reset.

·Location 004H

This area is reserved for the time base interrupt ser-

vice program. If the ETBI (intc.1) is activated, and the

interrupt is enabled and the stack is not full, the pro-

gram will jump to location 004H and begins execution.

·Location 008H

This area is reserved for the 8-bit timer counter 0 inter-

rupt service program. If a timer interrupt results from a

timer counter 0 overflow, and if the interrupt is enabled

and the stack is not full, the program will jump to loca-

tion 008H and begins execution.

·Location 00CH

This area is reserved for the 8-bit timer counter 1 inter-

rupt service program. If a timer interrupt results from a

timer counter 1 overflow, and if the interrupt is enabled

and the stack is not full, the program will jump to loca-

tion 00CH and begins execution.

Table Location

Any location in the ROM space can be used as look up

tables. The instructions TABRDC [m] (used for any

bank) and TABRDL [m] (only used for last page of pro-

gram ROM) transfer the contents of the lower-order byte

to the specified data memory [m], and the higher-order

byte to TBLH (08H). Only the destination of the

lower-order byte in the table is well-defined. The

higher-order bytes of the table word are transferred to

the TBLH. The table higher-order byte register (TBLH)

is read only.

The table pointer (TBLP) is a read/write register, which

indicates the table location.

Stack Register -Stack

The stack register is a special part of the memory used

to save the contents of the program counter (PC). This

stack is organized into four levels. It is neither part of the

data nor part of the program space, and cannot be read

or written to. Its activated level is indexed by a stack

pointer (SP) and cannot be read or written to. At a sub-

routine call or interrupt acknowledgment, the contents of

the program counter are pushed onto the stack.

The program counter is restored to its previous value

from the stack at the end of subroutine or interrupt rou-

tine, which is signaled by return instruction (RET or

RETI). After a chip resets, SP will point to the top of the

stack.

The interrupt request flag will be recorded but the ac-

knowledgment will be inhibited when the stack is full and

a non-masked interrupt takes place. After the stack

pointer is decremented (by RET or RETI), the interrupt

request will be serviced. This feature prevents stack

overflow and allows programmers to use the structure

more easily. In a similar case, if the stack is full and a

²CALL²is subsequently executed, stack overflow oc-

curs and the first entry is lost.

Instruction Table Location

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] 0 0 0 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *10~*0: Current program ROM table @7~@0: Write @7~@0 to TBLP pointer register

0000H

0004H

0008H

P r o g r a

R O M

000C H

I n i t i a l A d d r e s s

T i m e B a s e I n t e r r u p t S u b r o u t i n e

T i m e r 0 I n t e r r u p t S u b r o u t i n e

T i m e r 1 I n t e r r u p t S u b r o u t i n e

0 7 F F H

0015H

Program memory

HT83XXX

Rev. 0.00 9 February 19, 2003

Preliminary

Data Memory -RAM

The data memory is designed with 80´8 bits. The data

memory is further divided into two functional groups,

namely, special function registers (00H~2AH) and gen-

eral purpose user data memory (30H~7FH). Although

most of them can be read or be written to, some are read

only.

The special function registers include an indirect ad-

dressing register (R0:00H), memory pointer register

(MP0:01H), accumulator (ACC:05H), program counter

lower-order byte register (PCL:06H), table pointer

(TBLP:07H), table higher-order byte register

(TBLH:08H), status register (STATUS:0AH), interrupt

control register 0 (INTC:0BH), timer counter 0

(TMR0:0DH), timer counter 0 control register

(TMR0C:0EH), timer counter 1 (TMR1L:10H), timer

counter 1 control register (TMR1C:11H), I/O registers

(PA:12H), I/O control registers (PAC:13H), voice ROM

address latch0[21:0] (LATCH0H:18H, LATCH0M:19H,

LATCH0L:1AH), time base control bit EBTI (INTC.1),

PWM control register (PWMCR:26H), PWM output

(PWMD:28H), voice ROM latch data register

(LATCHD:2AH).

The general purpose data memory, addressed from

30H~7FH, is used for data and control information un-

der instruction commands.

The areas in the RAM can directly handle the arithmetic,

logic, increment, decrement and rotate operations. Ex-

cept some dedicated bits, each bit in the RAM can be

set and reset by ²SET [m].i²and ²CLR [m].i². They are

also indirectly accessible through the Memory Pointer

S p e c i a l P u r p o s e

D A T A M E M O R Y

14H

15H

16H

17H

18H

19H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

10H

11H

12H

13H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 5 H

30H

7 F H

2 6 H

2 7 H

2 8 H

2 9 H

2 A H

2 B H

2 F H

: U n u s e d .

R e a d a s " 0 "

M P 0

R 0

A C C

P C L

T B L P

T B L H

W D T S

S T A T U S

I N T C

T M R 0

T M R 0 C

T M R 1

T M R 1 C

P A

PAC

L A T C H 0 H

L A T C H 0 M

L A T C H 0 L

P W M D

L A T C H D

G e n e r a l P u r p o s e D a t a M e m o r y

P W M C R

RAM mapping

Address RAM Mapping Read/Write Description

00H R0 R/W Indirect addressing register 0

01H MP0 R/W Memory pointer 0

05H ACC R/W Accumulator

06H PCL R/W Program counter lower-order byte address

07H TBLP R/W Table pointer lower-order byte register

08H TBLH R Table higher-order byte content register

09H WDTS R/W Watchdog Timer option setting register

HT83XXX

Rev. 0.00 10 February 19, 2003

Preliminary

Address RAM Mapping Read/Write Description

0AH STATUS R/W Status register

0BH INTC R/W Interrupt control register 0

0DH TMR0 R/W Timer counter 0 register

0EH TMR0C R/W Timer counter 0 control register

10H TMR1 R/W Timer counter 1 register

11H TMR1C R/W Timer counter 1 control register

12H PA R/W Port A I/O data register

13H PAC R/W Port A I/O control register

18H LATCH0H R/W Voice ROM address latch 0 [A21~A16]

19H LATCH0M R/W Voice ROM address latch 0 [A15~A8]

1AH LATCH0L R/W Voice ROM address latch 0 [A7~A0]

26H PWMCR R/W PWM control register

28H PWMD R/W PWM output data D7~D0

2AH LATCHD R Voice ROM data register

2BH~2FH Unused

30H~7FH User data RAM R/W User data RAM

Note: R: Read only

W: Write only

R/W: Read/Write

Indirect Addressing Register

Location 00H is indirect addressing registers that are

not physically implemented. Any read/write operation of

[00H] accesses the RAM pointed to by MP0 (01H) re-

spectively. Reading location 00H indirectly returns the

result 00H. While, writing it indirectly leads to no opera-

tion.

Accumulator -ACC (05H)

The accumulator (ACC) is related to the ALU opera-

tions. It is also mapped to location 05H of the RAM and

is capable of operating with immediate data. The data

movement between two data memory locations must

pass through the ACC.

Arithmetic and Logic Unit -ALU

This circuit performs 8-bit arithmetic and logic opera-

tions and provides the following functions:

·Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

·Logic operations (AND, OR, XOR, CPL)

·Rotation (RL, RR, RLC, RRC)

·Increment and Decrement (INC, DEC)

·Branch decision (SZ, SNZ, SIZ, SDZ etc)

Status Register -STATUS (0AH)

This 8-bit STATUS register (0AH) consists of a zero flag

(Z), carry flag (C), auxiliary carry flag (AC), overflow flag

(OV), power down flag (PD), watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

Except the TO and PD flags, bits in the status register

can be altered by instructions similar to other registers.

Data written into the status register does not alter the TO

or PD flags. Operations related to the status register,

however, may yield different results from those in-

tended. The TO and PD flags can only be changed by a

Watchdog Timer overflow, chip power-up, or clearing

the Watchdog Timer and executing the ²HALT²instruc-

tion. The Z, OV, AC, and C flags reflect the status of the

latest operations.

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack. If the contents of the status

is important, and if the subroutine is likely to corrupt the

status register, the programmer should take precautions

and save it properly.

HT83XXX

Rev. 0.00 11 February 19, 2003

Preliminary

Labels Bits Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

AC 1AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z2 Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

OV 3OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PD 4PD is cleared by system power-up or executing the ²CLR WDT²instruction. PD is set by exe-

cuting the ²HALT²instruction.

TO 5TO is cleared by system power-up or executing the ²CLR WDT²or ²HALT²instruction. TO is

set by a WDT time-out.

¾6, 7 Unused bit, read as ²0²

Status register

Interrupts

The HT83XXX provides two 8-bit programmable timer

interrupts, and a time base interrupt. The Interrupt Con-

trol registers (INTC:0BH) contain the interrupt control

bits to set to enable/disable and the interrupt request

flags.

Once an interrupt subroutine is serviced, all other inter-

rupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt needs servicing within the service routine, the

EMI bit and the corresponding INTC bit may be set to al-

low interrupt nesting. If the stack is full, the interrupt re-

quest will not be acknowledged, even if the related

interrupt is enabled, until the SP is decremented. If im-

mediate service is desired, the stack must be prevented

from becoming full.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack and then

branching to subroutines at the specified location(s) in

the program memory. Only the program counter is

pushed onto the stack. The programmer must save the

contents of the register or status register (STATUS) in

advance if they are altered by an interrupt service pro-

gram which corrupts the desired control sequence.

The Internal Timer Counter 0 Interrupt is initialized by

setting the timer counter 0 interrupt request flag (T0F:bit

5 of INTC), caused by a timer counter 0 overflow. When

the interrupt is enabled, and the stack is not full and the

T0F bit is set, a subroutine call to location 08H will occur.

The related interrupt request flag (T0F) will be reset and

the EMI bit cleared to disable further interrupts.

The Internal Timer Counter 1 Interrupt is initialized by

setting the timer counter 1 interrupt request flag (T1F:bit

6 of INTC), caused by a timer counter 1 overflow. When

the interrupt is enabled, and the stack is not full and the

T1F bit is set, a subroutine call to location 0CH will oc-

cur. The related interrupt request flag (T1F) will be reset

and the EMI bit cleared to disable further interrupts.

Time Base Interrupt is triggered by set INTC.1 (ETBI)

which sets the related interrupt request flag (TBF:bit 4 of

INTC). When the interrupt is enabled, and the stack is

not full and the external interrupt is active, a subroutine

call to location 04H will occur. The interrupt request flag

(TBF) and EMI bits will be cleared to disable other inter-

rupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgment are held until the RETI instruc-

tion is executed or the EMI bit and the related interrupt

control bit are set to 1 (of course, if the stack is not full).

To return from the interrupt subroutine, the RET or RETI

instruction may be invoked. RETI will set the EMI bit to

enable an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests,

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

The timer counter 0/1 interrupt request flag (T0F/T1F)

which enables timer counter 0/1 control bit (ET0I/ET1I),

the time base interrupt request flag (TBF) which enables

time base control bit (ETTBI) from the interrupt control

control the enabling/disabling of interrupts. These bits

prevent the requested interrupt begin serviced. Once

the interrupt request flags (T0F, T1F, TBF) are set, they

will remain in the INTC register until the interrupts are

serviced or cleared by a software instruction.

It is recommended that application programs do not use

CALL subroutines within an interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only

HT83XXX

Rev. 0.00 12 February 19, 2003

Preliminary

one stack is left and the interrupt enable is not well controlled, once a CALL subroutine if used in the interrupt subrou-

tine will corrupt the original control sequence.

INTC

(0BH)

0 EMI Controls the master (global) interrupt (1= enabled; 0= disabled)

1 ETBI Controls the time base interrupt (1= enabled; 0= disabled)

2 ET0I Controls the timer 0 interrupt (1= enabled; 0= disabled)

3 ET1I Controls the timer 1 interrupt (1= enabled; 0= disabled)

4 TBF Time base interrupt request flag (1= active; 0= inactive)

5 T0F Timer 0 request flag (1= active; 0= inactive)

6 T1F Timer 1 request flag (1= active; 0= inactive)

7¾Unused bit, read as ²0²

INTC0 register

Interrupt Source Priority Vector

Time Base Interrupt 1 04H

Timer Counter 0 Overflow 2 08H

Timer Counter 1 Overflow 3 0CH

Oscillator Configuration

The HT83XXX provides RC oscillator circuit for the sys-

tem clock. The signal is used for the system clock. The

HALT mode stops the system oscillator to conserve

power. If the RC oscillator is used, an external resistor

between OSC1 and VSS is required, and the range of

the resistance should be from 62kWto 100kW. The sys-

tem clock, divided by 4. The RC oscillator provides the

most cost effective solution. However, the frequency of

the oscillation may vary with VDD, temperature, and the

chip itself due to process variations. It is therefore not

suitable for timing sensitive operations where accurate

oscillator frequency is desired.

Watchdog Timer -WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or instruction clock (sys-

tem clock divided by 4), decided by mask options. This

timer is designed to prevent a software malfunction or

sequence jumping to an unknown location with unpre-

dictable results. The Watchdog Timer can be disabled

by mask option. If the Watchdog Timer is disabled, all

the executions related to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with pe-

riod 78ms normally) is selected, it is first divided by 256

(8-stages) to get the nominal time-out period of approxi-

mately 20ms. This time-out period may vary with tem-

perature, VDD and process variations. By invoking the

WDT prescaler, longer time-out period can be realized.

Writing data to WS2, WS1, WS0 (bit 2,1,0 of

WDTS(09H)) can give different time-out period.

If WS2, WS1, WS0 all equal to 1, the division ratio is up

to 1:128, and the maximum time-out period is 2.6 sec-

onds.

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

R C O s c i l l a t o r

O S C 1

System oscillator

HT83XXX

Rev. 0.00 13 February 19, 2003

Preliminary

The WDT overflow under normal operation will initialize

a²chip reset²and set the status bit ²TO². Whereas in

the HALT mode, the overflow will initialize a ²warm re -

set²only the PC and SP are reset to zero. To clear the

contents of the WDT (including the WDT prescaler),

three methods are adopted; external reset (external re-

set (a low level to RES), software instructions, or a

HALT instruction. The software instruction is ²CLR

WDT²and execution of the ²CLR WDT²instruction will

clear the WDT.

S y s t e m C l o c k / 4

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

M a s k

O p t i o n

S e l e c t

W D T

O S C

Watchdog Timer

WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 Division Ratio

¾¾¾¾¾ 000 1:1

¾¾¾¾¾ 001 1:2

¾¾¾¾¾ 010 1:4

¾¾¾¾¾ 011 1:8

¾¾¾¾¾ 1 0 0 1:16

¾¾¾¾¾ 1 0 1 1:32

¾¾¾¾¾ 1 1 0 1:64

¾¾¾¾¾ 1 1 1 1:128

WDTS register

Power Down -HALT

The HALT mode is initialized by a HALT instruction and

results in the following:

·The system oscillator will be turned off but the WDT

oscillator keeps running (if the WDT oscillator is se-

lected).

·The contents of the on chip RAM and registers remain

unchanged.

·WDT and WDT prescaler will be cleared and recount

again.

·All I/O ports maintain their original status.

·The PD flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a ²warm reset². By examining the TO and PD

flags, the reason for the chip reset can be determined.

The PD flag is cleared when the system powers-up or

executes the ²CLR WDT²instruction, and is set when

the ²HALT²instruction is executed. The TO flag is set if a

WDT time-out occurs, and causes a wake-up that only

resets the PC and SP. The other maintain their original

status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by mask option. Awakening from an I/O port

stimulus, the program will resume execution of the next

instruction. If awakening from an interrupt, two se-

quence may occur. If the related interrupt is disabled or

the interrupt is enabled by the stack is full, the program

will resume execution at the next instruction. If the inter-

rupt is enabled and the stack is not full, the regular inter-

rupt response takes place.

Once a wake-up event occurs, it takes 1024 system

clock period to resume normal operation. In other

words, a dummy cycle period will be inserted after a

wake-up. If the wake-up results from an interrupt ac-

knowledge, the actual interrupt subroutine will be de-

layed by one more cycle. If the wake-up results in next

instruction execution, this will be executed immediately

after a dummy period is finished. If an interrupt request

flag is set to ²1²before entering the HALT mode, the

wake-up function of the related interrupt will be dis-

abled. To minimize power consumption, all I/O pins

should be carefully managed before entering the HALT

status.

HT83XXX

Rev. 0.00 14 February 19, 2003

Preliminary

Reset

There are 3 ways in which a reset can occur:

·RES reset during normal operation

·RES reset during HALT

·WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set²that resets only the PC and SP, leaving the other cir-

cuits in their original state. Some registers remain un-

changed during any other reset conditions. Most

registers are reset to their ²initial condition²when the re-

set conditions are met. By examining the PD flag and

TO flag, the program can distinguish between different

²chip resets².

TO PD RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u²stands for ²unchanged²

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses after a system

power up or when awakening from a HALT state.

When a system power up occurs, the SST delay is

added during the reset period. But when the reset co-

mes from the RES pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

Reset timing chart

Reset circuit

Reset configuration

The functional unit chip reset status are shown below.

PC 000H

Interrupt Disable

Prescaler Clear

WDT Clear. After master reset,

WDT begins counting

Timer counter Off

Input/output ports Input mode

SP Points to the top of the stack

Timer Counter 0/1

The TMR0/TMR1 is internal clock source only, i.e. (TM1,

TM0)=(1,0). There is a 3-bit prescaler (TMRS2, TMRS1,

TMRS0) which defines different division ratio of

TMR0/TMR1¢s clock source.

Label Bits Function

TMRS2,

TMRS1,

TMRS0

0~2

Defines the operating clock source

(TMRS2, TMRS1, TMRS0)

000: clock source/2

001: clock source/4

010: clock source/8

011: clock source/16

100: clock source/32

101: clock source/64

110: clock source/128

111: clock source/256

TE 3 Defines the TMR0/TMR1 active edge

of timer counter

TON 4 Enable/disable timer counting

(0=disabled; 1=enabled)

¾5Unused bit, read as ²0²

TM0,

TM1

Defines the operating mode

(TM1, TM0)

TMR0C/TMR1C register

Note: TMR0C/TMR1C bit 3 always write ²0²

TMR0C/TMR1C bit 5 always write ²0²

TMR0C/TMR1C bit 6 always write ²1²

TMR0C/TMR1C bit 7 always write ²0²

tS S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

R E S

D D

W D T

H A L T

W D T

T i m e - o u t

R e s e t

R E S

C o l d

R e s

W a r m R e s e t

P o w e r - o n D e t e c t i n g

SST

1 0 - s t a g e

R i p p l e C o u n t e r

O S C I

HT83XXX

Rev. 0.00 15 February 19, 2003

Preliminary

The TMR0C is the timer counter 0 control register, which

defines the timer counter 0 options. The timer counter 1

has the same options as the timer counter 0 and is de-

fined by TMR1C.

To enable the counting operation, the Timer ON bit

(TON; bit 4 of TMR0C/TMR1C) should be set to 1. The

overflow of the timer counter is one of the wake-up

sources. No matter what the operation mode is, writing a

0 to ET0I/ET1I can disable the corresponding interrupt

service.

The TMR0/1 is internal clock source only. There is a

3-bit prescaler (TMRS2, TMRS1, TMRS0) which de-

fines different division ratio of TMR0/1¢s clock source.

Time Base

The time base enables the counting operation by

INTC.1 (ETBI) bit. The overflow to interrupt as set

INTC.1. The time base is internal clock source only.

Time base of 1ms to overflow as system clock is 4MHz.

Time base of 0.5ms to overflow as system clock is

8MHz.

S y s t e m C l o c k

8 - S t a g e

P r e s c a l e r

T i m e r C o u n t e r 0 / 1

P r e l o a d R e g i s t e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

T i m e r C o u n t e r 0 / 1

T O N

( T M R S 2 , T M R S 1 , T M R S 0 )

Timer counter 0/1

1024

S y s t e m C l o c k / 4 O v e r f l o w

t o I n t e r r u p t

Time base

The registers states are summarized in the following table.

(Normal Operation)

RES Reset

(Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)

PC 0000H 0000H 0000H 0000H 0000H

MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu

STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu

INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu

TMR0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TMR0C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u---

TMR1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TMR1C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u---

LATCH0H ---- --xx ---- --uu ---- --uu ---- --uu ---- --uu

LATCH0M xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

LATCH0L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PWMCR -00- 00-0 -uu- uu-u -uu- uu-u -uu- uu-u -uu- uu-u

PWMD xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

LATCHD xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

Note: ²u²means ²unchanged²;²x²means ²unknown²;²-² means ²undefined²

HT83XXX

Rev. 0.00 16 February 19, 2003

Preliminary

Low Voltage Reset -LVR

The microcontroller provides low voltage reset circuit in

order to monitor the supply voltage of the device. If the

supply voltage of the device is within 2.2V or 3.3V (by

mask option), such as changing a battery, the LVR will

automatically reset the device internally.

Input/Output Ports

There are 8 bidirectional input/output lines in the

microcontroller, labeled from PA, which are mapped to

the data memory of [12H] respectively. All of these I/O

ports can be used for input and output operations. For

input operation, these ports are non-latching, that is, the

inputs must be ready at the T2 rising edge of instruction

²MOV A, [m]²(m=12H). For output operation, all the

data is latched and remains unchanged until the output

latch is rewritten.

Each I/O line has its own control register (PAC) to con-

trol the input/output configuration. With this control reg-

ister, CMOS output or Schmitt trigger input with or

without pull-high resistor structures can be reconfigured

dynamically under software control. To function as an in-

put, the corresponding latch of the control register must

write ²1². The input source also depends on the control

read the pad state. If the control register bit is ²0², the

contents of the latches will move to the internal bus. The

latter is possible in the ²read-modify-write²instruction.

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H.

After a chip reset, these input/output lines remain at high

levels or floating state (dependent on pull-high options).

Each bit of these input/output latches can be set or

cleared by ²SET [m].i²and ²CLR [m].i²(m=12H) instruc-

tions.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i²,²CLR

[m].i²,²CPL [m]²,²CPLA [m]²read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. The wake-up capability of port A is determined

by mask option. There is a pull-high option available for

all I/O lines. Once the pull-high option is selected, all I/O

lines have pull-high resistors. Otherwise, the pull-high

resistors are absent. It should be noted that a

non-pull-high I/O line operating in input mode will cause

a floating state.

C K

MUX

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e I / O

R e a d I / O

S y s t e m W a k e - U p ( P A o n l y )

W e a k

P u l l - u p

P A 0 ~ P A 7

P B 0 ~ P B 7

P C 0 ~ P C 7

M a s k O p t i o n

D D

Input/output ports

HT83XXX

Rev. 0.00 17 February 19, 2003

Preliminary

Audio Output -PWMD (28H)

The HT83XXX provides one 8-bit PWM interface for driving an external 8Wspeaker. The programmer must write the

voice data to register PWMD (28H)

Pulse Width Modulation Control Register -PWMCR (26H)

Bit 7 Bit 6 (R/W) Bit 5 (R/W) Bit 4 Bit 3 (R/W) Bit 2 (R/W) Bit 1 Bit 0 (R/W)

¾P1 P0 ¾Single_PWM VROMC ¾PWMC

S y s t e m c l o c k

P r e s c a l e r

P W M D a t a

B u f f e r ( 2 8 H )

7 B i t s C o u n t e r

( B i t 6 ~ B i t 0 )

D a t a B u s

O v e r f l o w

P W M D A C 1 f o r S P E A K E R

F 0

S t a r t b i t

2 6 H . 0

D i v .

P W M I

F 2

C K

P E

C K

VD D

F 1

P W M D A C 2 f o r S P E A K E R

B i t 7 ( s i g n b i t )

PWM

PWMC: Start bit of PWM output

·PWM start counter: 0 to 1

·PWM stop counter: 1 to 0

After waiting one cycle end , stop the PWM counter and

keep in low signal

VROMC: Enable voice ROM power circuit (1=enable;

0=disable)

Single_PWM: Driving PWM signal only by PWM1 port.

(1=enable; 0=disable)

The HT83xxx provides an 8-bit (bit 7 is a sign bit, if Sin-

gle_PWM = 0) PWM interface. The PWM provides two

pad outputs: PWM1, PWM2 which can directly drive a

piezo or a 8Wspeaker without adding any external ele-

ment (green mode), or using only port PWM1 (Set Sin-

gle_PWM = 1) to drive piezo or a 8Wspeaker with

external element.

When Setting Single_PWM = 1, choose voice

data7~data1 as the output data (no sign bit on it).

Setting data to P0 and P1 can generate various sam-

pling rates (5kHz/6kHz/8kHz):

P1 P0 Sampling

Rate

Carrier

frequency

Preload

Times

PWM Code

Range

0 0 5kHz 30kHz 6 0~127

0 1 6kHz 30kHz 5 0~127

1 0 8kHz 32kHz 4 0~124

¾¾ XXXX

If the sign bit is 0, then the signal is output to PWM1and

the PWM2 will get a GND level voltage after setting start

bit to 1. If the sign bit is 1, then the signal is output to

PWM2 and the PWM1 will get a GND level voltage after

setting start bit to 1.

PWM output Initial low level , and stop in low level

If PWMC from low to high then start PWM output and

5kHz/6kHz/8kHz latch new data , if no update then keep

the old value.

If PWMC from high to low, in duty end, stop PWM output

and stop the counter.

Voice ROM Data Address Latch Counter

The voice ROM data address latch counter is the hand-

shaking between the microcontroller and voice ROM,

where the voice codes are stored. One 8-bit of voice

ROM data will be addressed by setting 21-bit address

latch counter LATCH0H/LATCH0M/LATCH0L. After the

8-bit voice ROM data is addressed, a few instruction cy-

cles (4ms at least) will be generated to latch the voice

ROM data, then the microcontroller can read the voice

data from LATCHD (2AH).

Example: Read an 8-bit voice ROM data which is lo-

cated at address 000007H by address latch 0

set [26H].2 ; Enable voice ROM circuit

mov A, 07H ;

mov LATCH0L, A ; Set LATCH0L to 07H

mov A, 00H ;

mov LATCH0M, A ; Set LATCH0M to 00H

mov A, 00H ;

mov LATCH0H, A ; Set LATCH0H to 00H

call Delay Time ; Delay a short period of time

mov A, LATCHD ; Get voice data at 000007H

HT83XXX

Rev. 0.00 18 February 19, 2003

Preliminary

Mask Option

Mask Option Description

PA Wake-up Enable or disable PA wake-up function

Watchdog Timer (WDT)

Enable or disable WDT function

One or two CLR instruction

WDT clock source is from WDTOSC or T1

Low Voltage Reset (LVR) Enable or disable low voltage reset

Low voltage reset at 2.2V or 3.3V

PA Pull-high Enable or disable PA pull-high

fOSC -ROSC Table (VDD=5V)

fOSC ROSC

4MHz±10%

6MHz±10%

8MHz±10%

100kW

75kW

62kW

Application Circuits

Single PWM Mode

Note: * For normal application, a capacitor C is not necessary. However, if you want to extend the reset time,a0.1mF

capacitor can be placed on the RES pin.

HT83XXX

Rev. 0.00 19 February 19, 2003

Preliminary

R E S

V D D

O S C 1

H T 8 3 X X X

Speaker

( 8 / 1 6 )

P W M 1

P A 0 ~ P A 7

D D

R ( 1 0 0 k

~ 6 2 k

)

G N D

D D

P W M 2

V C C A 1

G N D A 1

4 7

0 . 1

O S C 1

H T 8 3 X X X

Speaker

( 8 / 1 6 )

P W M 1

R ( 1 0 0 k

~ 6 2 k

)

VD D

P W M 2

V C C A 1

G N D A 1

4 7

FVD D

Q 2

N P N B C E

R E S

V D D

P A 0 ~ P A 7

VD D

G N D

0 . 1

Package Information

32-pin DIP (600mil) Outline Dimensions

Symbol Dimensions in mil

Min. Nom. Max.

A 1635 ¾1665

B 535 ¾555

C 145 ¾155

D 125 ¾145

E16

¾20

F50

¾70

G¾100 ¾

H 595 ¾615

I 635 ¾670

a0°¾15°

HT83XXX

Rev. 0.00 20 February 19, 2003

Preliminary

3 2

1 7

1 6

EF G

HT83XXX

Rev. 0.00 21 February 19, 2003

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due

malfunction

otherwise.

Holtek¢s

products

are

not

authorized

for

use

critical

components

life

support

devices

systems.

Holtek

reserves

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right

alter

its

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without

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notification.

For

the

most

up-to-date

information,

please visit our web site at http://www.holtek.com.tw.

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