14-Bit, 8-Channel,
250 kSPS PulSAR ADC
Enhanced Product AD7949-EP
Rev. B Document Feedbac
k
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FEATURES
14-bit resolution with no missing codes
8-channel multiplexer with choice of inputs
Unipolar single-ended
Differential (GND sense)
Pseudobipolar
Throughput: 250 kSPS
INL/DNL: ±0.5/±0.25 LSB typical
SINAD: 85 dB at 20 kHz
THD: −100 dB at 20 kHz
Analog input range: 0 V to VREF with VREF up to VDD
Multiple reference types
Internal selectable 2.5 V or 4.096 V
External buffered (up to 4.096 V)
External (up to VDD)
Internal temperature sensor (TEMP)
Channel sequencer, selectable 1-pole filter, busy indicator
No pipeline delay, SAR architecture
Single-supply 2.3 V to 5.5 V operation with
1.8 V to 5.5 V logic interface
Serial interface compatible with SPI, MICROWIRE,
QSPI, and DSP
Power dissipation
2.9 mW at 2.5 V/200 kSPS
10.8 mW at 5 V/250 kSPS
Standby current: 50 nA
20-lead 4 mm × 4 mm LFCSP package
Supports defense and aerospace applications (AQEC
standard)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Multichannel system monitoring
Battery-powered equipment
Medical instruments: ECG/EKG
Mobile communications: GPS
Power line monitoring
Data acquisition
Seismic data acquisition systems
Instrumentation
Process control
FUNCTIONAL BLOCK DIAGRAM
AD7949-EP
REF
GND
VDD
VIO
DIN
SCK
SDO
CNV
1.8V
TO
VDD
2.3 V TO 5.5
V
SEQUENCER
SPI SERIAL
INTERFACE
MUX 14-BIT S AR
ADC
BAND GAP
REF
TEMP
SENSOR
REFIN
IN0
IN1
IN4
IN5
IN6
IN7
IN3
IN2
COM
0.5V T O VDD
10µF
ONE-POLE
LPF
0.5V TO V DD – 0. 5V
0.1µF
09822-001
Figure 1.
GENERAL DESCRIPTION
The AD7949-EP is an 8-channel, 14-bit, charge redistribution
successive approximation register (SAR) analog-to-digital
converter (ADC) that operates from a single power supply, VDD.
The AD7949-EP contains all components for use in a multi-
channel, low power data acquisition system, including a true
14-bit SAR ADC with no missing codes; an 8-channel, low
crosstalk multiplexer that is useful for configuring the inputs as
single-ended (with or without ground sense), differential, or
bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V)
and buffer; a temperature sensor; a selectable one-pole filter;
and a sequencer that is useful when channels are continuously
scanned in order.
The AD7949-EP uses a simple SPI interface for writing to the
configuration register and receiving conversion results. The SPI
interface uses a separate supply, VIO, which is set to the host
logic level. Power dissipation scales with throughput.
The AD7949-EP is housed in a tiny 20-lead LFCSP with operation
specified from −55°C to +125°C. Full details about this enhanced
product are available in the AD7949 data sheet, which should
be consulted in conjunction with this data sheet.
Table 1. Multichannel 14-/16-Bit PulSAR® ADCs
Type Channels 250 kSPS 500 kSPS ADC Driver
14-Bit 8 AD7949 ADA4841-1
16-Bit 4 AD7682 ADA4841-1
16-Bit 8 AD7689 AD7699 ADA4841-1
AD7949-EP Enhanced Product
Rev. B | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions ..............................8
Typical Performance Characteristics ..............................................9
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
5/2018—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
5/2015—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 1
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
4/2011—Revision 0: Initial Version
Enhanced Product AD7949-EP
Rev. B | Page 3 of 12
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, VREF = VDD, all specifications −55°C to +125°C, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 14 Bits
ANALOG INPUT
Voltage Range Unipolar mode 0 +VREF V
Bipolar mode
−V
REF
/2
+V
REF
/2
Absolute Input Voltage Positive input, unipolar and bipolar modes −0.1 VREF + 0.1 V
Negative or COM input, unipolar mode −0.1 +0.1
Negative or COM input, bipolar mode VREF/2 − 0.1 VREF/2 VREF/2 + 0.1
Analog Input CMRR fIN = 250 kHz 68 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance1
THROUGHPUT
Conversion Rate
Full Bandwidth
2
VDD = 4.5 V to 5.5 V
0
250
kSPS
VDD = 2.3 V to 4.5 V 0 200 kSPS
¼ Bandwidth2 VDD = 4.5 V to 5.5 V 0 62.5 kSPS
VDD = 2.3 V to 4.5 V 0 50 kSPS
Transient Response Full-scale step, full bandwidth 1.8 μs
Full-scale step, ¼ bandwidth
14.5
μs
ACCURACY
No Missing Codes 14 Bits
Integral Linearity Error −1 ±0.5 +1 LSB3
Differential Linearity Error −1 ±0.25 +1 LSB
Transition Noise REF = VDD = 5 V 0.1 LSB
Gain Error4 −5 ±0.5 +5 LSB
Gain Error Match −1 ±0.2 +1 LSB
Gain Error Temperature Drift ±1 ppm/°C
Offset Error
4
±0.5
LSB
Offset Error Match −1 ±0.2 +1 LSB
Offset Error Temperature Drift ±1 ppm/°C
Power Supply Sensitivity VDD = 5 V ± 5% ±0.2 LSB
AC ACCURACY5
Dynamic Range 85.6 dB6
Signal-to-Noise fIN = 20 kHz, VREF = 5 V 84.5 85.5 dB
fIN = 20 kHz, VREF = 4.096 V internal REF 85 dB
fIN = 20 kHz, VREF = 2.5 V internal REF 84 dB
SINAD fIN = 20 kHz, VREF = 5 V 84 85 dB
fIN = 20 kHz, VREF = 5 V, −60 dB input 33.5 dB
fIN = 20 kHz, VREF = 4.096 V internal REF 85 dB
fIN = 20 kHz, VREF = 2.5 V internal REF 84 dB
Total Harmonic Distortion
f
IN
= 20 kHz
−100
dB
Spurious-Free Dynamic Range fIN = 20 kHz 108 dB
Channel-to-Channel Crosstalk fIN = 100 kHz on adjacent channel(s) −125 dB
SAMPLING DYNAMICS
−3 dB Input Bandwidth Full bandwidth 1.7 MHz
¼ bandwidth 0.425 MHz
Aperture Delay VDD = 5 V 2.5 ns
AD7949-EP Enhanced Product
Rev. B | Page 4 of 12
Parameter Test Conditions/Comments Min Typ Max Unit
INTERNAL REFERENCE
REF Output Voltage 2.5 V, at 25°C 2.490 2.500 2.510 V
4.096 V, at 25°C 4.086 4.096 4.106 V
REFIN Output Voltage7 2.5 V, at 25°C 1.2 V
4.096 V, at 25°C
2.3
V
REF Output Current ±300 µA
Temperature Drift ±10 ppm/°C
Line Regulation VDD = 5 V ± 5% ±15 ppm/V
Long-Term Drift 1000 hours 50 ppm
Turn-On Settling Time CREF = 10 µF 5 ms
EXTERNAL REFERENCE
Voltage Range REF input 0.5 VDD + 0.3 V
REFIN input (buffered) 0.5 VDD − 0.5 V
Current Drain
250 kSPS, REF = 5 V
50
µA
TEMPERATURE SENSOR
Output Voltage
8
At 25°C
283
mV
Temperature Sensitivity 1 mV/°C
DIGITAL INPUTS
Logic Levels
VIL −0.3 +0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format9
Pipeline Delay10
VOL ISINK = +500 µA 0.4 V
VOH ISOURCE = −500 µA VIO − 0.3 V
POWER SUPPLIES
VDD Specified performance 2.3 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
Operating range 1.8 VDD + 0.3 V
Standby Current11, 12 VDD and VIO = 5 V, at 25°C 50 nA
Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.5 µW
VDD = 2.5 V, 100 kSPS throughput 1.45 2.0 mW
VDD = 2.5 V, 200 kSPS throughput
2.9
4.0
mW
VDD = 5 V, 250 kSPS throughput 10.8 12.5 mW
VDD = 5 V, 250 kSPS throughput with internal
reference
13.5 15.5 mW
Energy per Conversion 50 nJ
TEMPERATURE RANGE13
Specified Performance TMIN to TMAX −55 +125 °C
1 See the AD7949 data sheet.
2 The bandwidth is set in the configuration register.
3 LSB means least significant bit. With the 5 V input range, one LSB = 305 µV.
4 See the AD7949 data sheet. These specifications include full temperature range variation but not the error contribution from the external reference.
5 With VDD = 5 V, unless otherwise noted.
6 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
7 This is the output from the internal band gap.
8 The output voltage is internal and present on a dedicated multiplexer input.
9 Unipolar mode: serial 14-bit straight binary.
Bipolar mode: serial 14-bit twos complement.
10 Conversion results available immediately after completed conversion.
11 With all digital inputs forced to VIO or GND as required.
12 During acquisition phase.
13 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Enhanced Product AD7949-EP
Rev. B | Page 5 of 12
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications −55°C to +125°C, unless otherwise noted.
Table 3.
Parameter1 Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 2.2 µs
Acquisition Time tACQ 1.8 µs
Time Between Conversions tCYC 4.0 µs
Data Write/Read During Conversion tDATA 1.0 µs
CNV Pulse Width tCNVH 10 ns
SCK Period tSCK tDSDO + 2 ns
SCK Low Time tSCKL 11 ns
SCK High Time tSCKH 11 ns
SCK Falling Edge to Data Remains Valid tHSDO 4 ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 23 ns
VIO Above 1.8 V 28 ns
CNV Low to SDO D15 MSB Valid tEN
VIO Above 2.7 V 18 ns
22
ns
VIO Above 1.8 V 25 ns
CNV High or Last SCK Falling Edge to SDO High Impedance tDIS 32 ns
CNV Low to SCK Rising Edge tCLSCK 10 ns
DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns
DIN Valid Hold Time from SCK Rising Edge tHDIN 5 ns
1 See Figure 2 and Figure 3 for load conditions.
AD7949-EP Enhanced Product
Rev. B | Page 6 of 12
VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications −55°C to +125°C, unless otherwise noted.
Table 4.
Parameter1 Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 3.2 µs
Acquisition Time tACQ 1.8 µs
Time Between Conversions tCYC 5 µs
t
DATA
1.2
µs
CNV Pulse Width tCNVH 10 ns
SCK Period tSCK tDSDO + 2 ns
SCK Low Time tSCKL 12 ns
SCK High Time tSCKH 12 ns
t
HSDO
5
ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO Above 3 V 24 ns
VIO Above 2.7 V 30 ns
VIO Above 2.3 V 38 ns
VIO Above 1.8 V 48 ns
CNV Low to SDO D15 MSB Valid tEN
VIO Above 3 V 21 ns
VIO Above 2.7 V 27 ns
VIO Above 2.3 V 35 ns
VIO Above 1.8 V 45 ns
CNV High or Last SCK Falling Edge to SDO High Impedance tDIS 50 ns
CNV Low to SCK Rising Edge tCLSCK 10 ns
DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns
DIN Valid Hold Time from SCK Rising Edge tHDIN 5 ns
1 See Figure 2 and Figure 3 for load conditions.
I
OL
500µA
500µA
I
OH
1.4V
TO SDO C
L
50pF
09822-002
Figure 2. Load Circuit for Digital Interface Timing
30% VIO 70% VIO
2V OR V IO – 0.5V1
0.8V OR 0. 5V 2
0.8V OR 0. 5V 2
2V OR V IO – 0.5V1
tDELAY tDELAY
1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
09822-003
Figure 3. Voltage Levels for Timing
Enhanced Product AD7949-EP
Rev. B | Page 7 of 12
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
INx, COM
1
GND − 0.3 V to VDD + 0.3 V
or VDD ± 130 mA
REF, REFIN GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VIO to VDD −0.3 V to VDD + 0.3 V
DIN, CNV, SCK to GND
−0.3 V to VIO + 0.3 V
SDO to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance (LFCSP) 47.6°C/W
θJC Thermal Impedance (LFCSP) 4.4°C/W
1 See the AD7949 data sheet.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD7949-EP Enhanced Product
Rev. B | Page 8 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD
REF
REFIN
GND
GND
SCK
SDO
VIO
DIN
CNV
IN4
IN5
IN6
COM
IN7 IN2
IN3
VDD
IN1
IN0
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTER NALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECO MMENDE D THAT TH E PAD BE
SOLDERED TO THE SYSTEM
GR OUND PLANE .
09822-004
14
13
12
1
3
4
15
11
2
5
7
6
8
9
10
19
20
18
17
16
AD7949-EP
TOP VIEW
(No t t o Scale)
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 20 VDD P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with
10 μF and 100 nF capacitors.
When using the internal reference for 2.5 V output, the minimum should be 3.0 V.
When using the internal reference for 4.096 V output, the minimum should be 4.5 V.
2 REF AI/O
Reference Input/Output. See the AD7949 data sheet.
When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or
4.096 V.
When the internal reference is disabled and the buffer is enabled, REF produces a buffered
version of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost,
low power references.
For improved drift performance, connect a precision reference to REF (0.5 V to VDD).
For any reference method, this pin needs decoupling with an external 10 μF capacitor
connected as close to REF as possible. See the AD7949 data sheet.
3 REFIN AI/O
Internal Reference Output/Reference Buffer Input. See the AD7949 data sheet.
When using the internal reference, the internal unbuffered reference voltage is present and
needs decoupling with a 0.1 μF capacitor.
When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is
buffered to the REF pin as described above.
4, 5 GND P Power Supply Ground.
6 to 9 IN4 to IN7 AI Channel 4 through Channel 7 Analog Inputs.
10 COM AI Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode
point of 0 V or VREF/2 V.
11 CNV DI Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is
held high, the busy indictor is enabled.
12 DIN DI Data Input. This input is used for writing to the 14-bit configuration register. The configuration
register can be written to during and after conversion.
13 SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN
in an MSB first fashion.
14 SDO DO Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar
modes, conversion results are straight binary; in bipolar modes, conversion results are twos
complement.
15 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
16 to 19 IN0 to IN3 AI Channel 0 through Channel 3 Analog Inputs.
21
(EPAD)
Exposed Pad
(EPAD)
NC The exposed pad is not connected internally. For increased reliability of the solder joints, it is
recommended that the pad be soldered to the system ground plane.
1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
Enhanced Product AD7949-EP
Rev. B | Page 9 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted.
1.0
0.5
0
–0.5
–1.0 04,096 8,192 12,288 16,384
INL (LSB)
CODES
09822-005
Figure 5. Integral Nonlinearity vs. Code, VREF = VDD = 5 V
300k
250k
200k
150k
100k
50k
01FFC
COUNTS
CODE IN HEX
1FFD 1FFE 1FFF 2000 2001 2002 2003
0 0 0 1 0 0 0 0
VREF = VDD = 5V
261,120
09822-006
Figure 6. Histogram of a DC Input at Code Center
0
–20
–40
–60
–80
–100
–120
–140
–160 05025 75 100 125
AMPLITUDE (dB of Full-Scale)
FREQUENCY ( kHz )
V
REF
= VDD = 5V
f
S
= 250kSPS
f
IN
= 19.9kHz
SNR = 85. 3dB
SINAD = 85.2d B
THD = –100dB
SFDR = 103dB
SECO ND HARM ONI C = –110dB
THI RD HARMONIC = –103dB
09822-007
Figure 7. 20 kHz FFT, VREF = VDD = 5 V
DNL ( LSB)
CODES
04,096 8,192 12,288 16,384
1.0
0.5
0
–0.5
–1.0
09822-008
Figure 8. Differential Nonlinearity vs. Code, VREF = VDD = 5 V
COUNTS
CODE IN HEX
259,473
300k
250k
200k
150k
100k
50k
01FFC 1FFD 1FFE 1FFF 2000 2001 2002 2003 2004
0 0 0 955 693 0 0 0
V
REF
= V
DD
= 2.5V
09822-009
Figure 9. Histogram of a DC Input at Code Center
0
–20
–40
–60
–80
–100
–120
–140
–160
–180 05025 75 100
AMPLITUDE (dB of Full-Scale)
FREQUENCY ( kHz )
V
REF
= VDD = 2.5V
f
s
= 200kSPS
f
IN
= 19.9kHz
SNR = 84. 2dB
SINAD = 82.4d B
THD = –84dB
SFDR = 85dB
SECO ND HARM ONI C = –100dB
THI RD HARMONIC = –85dB
09822-010
Figure 10. 20 kHz FFT, VREF = VDD = 2.5 V
AD7949-EP Enhanced Product
Rev. B | Page 10 of 12
90
85
80
75
70
65
60 050 100 150 200
SNR (dB)
FREQUENCY ( kHz )
VDD = V
REF
= 5V, –0.5d B
VDD = V
REF
= 5V, –10dB
VDD = V
REF
= 2.5V , –0. 5dB
VDD = V
REF
= 2.5V , –10d B
09822-011
Figure 11. SNR vs. Frequency
88
86
84
82
80
78
15.5
15.0
14.5
14.0
13.5
13.0
1.0
SNR, S INAD (dB)
ENOB ( Bits)
REFERENCE VOLTAGE (V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SNR
SINAD
ENOB
09822-012
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
90
85
80
75
70
65
60
–55
SNR (dB)
TEMPERATURE (°C)
–35 –15 525 45 65 85 105 125
f
IN
= 20kHz VDD = V
REF
= 5V
VDD = V
REF
= 2.5V
09822-013
Figure 13. SNR vs. Temperature
90
85
80
75
70
65
60 050 100 150 200
SINAD ( dB)
FREQUENCY ( kHz )
VDD = V
REF
= 5V, –0.5d B
VDD = V
REF
= 5V, –10dB
VDD = V
REF
= 2.5V , –0. 5dB
VDD = V
REF
= 2.5V , –10d B
09822-014
Figure 14. SINAD vs. Frequency
130
125
120
115
110
105
100
95
90
85
80
75
70
1.0
SFDR (dB)
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
THD ( dB)
REFERENCE VOLTAGE (V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SFDR
THD
09822-015
Figure 15. SFDR and THD vs. Reference Voltage
–90
–95
–100
–105
–110
–55
THD ( dB)
TEMPERATURE (°C)
–35 –15 525 45 65 85 105 125
fIN = 20kHz
VDD = VREF = 5V
VDD = VREF = 2. 5V
09822-016
Figure 16. THD vs. Temperature
Enhanced Product AD7949-EP
Rev. B | Page 11 of 12
–60
–70
–80
–90
–100
–110
–120 050 100 150 200
THD ( dB)
FREQUENCY ( kHz )
VDD = V REF = 5V , –0.5dB
VDD = V REF = 2.5V, –0.5d B
VDD = V REF = 2.5V, –10dB
VDD = V REF = 5V , –10dB
09822-017
Figure 17. THD vs. Frequency
90
89
88
87
86
85
84
83
82
81
80
79
78
–10
SNR (dB)
INPUT LEVEL (d B)
–8 –6 –2 0
–4
f
IN
= 20kHz
VDD = V
REF
= 2.5V
09822-018
VDD = V
REF
= 5V
Figure 18. SNR vs. Input Level
2
1
0
–1
–2
OF FSE T ERRO R AND GAI N E RROR (L S B)
–55 TEMPERATURE (°C)
–35 –15 525 45 65 85 105 125
UNIPOLAR ZERO
UNIPOLAR GAIN
BIPOLAR ZERO
BIPOLAR GAIN
09822-019
Figure 19. Offset and Gain Errors vs. Temperature
2750
2500
2250
2000
1750
1500
1250
1000
750
100
90
80
70
60
50
40
30
20
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD CURRENT ( µA)
VIO CURRENT (µ A)
VDD SUPPLY (V)
2.5VINTERNALREF
4.096V INTERNALREF
INTERNALBUFFER, TEMP ON
INTERNALBUFFER, TEMP OFF
EXTERNALREF, TEMP ON
EXTERNALREF,TEMP OFF
VIO
fS = 200kSPS
09822-020
Figure 20. Operating Currents vs. Supply
3000
2750
2500
2250
2000
1750
1500
1250
1000
180
160
140
120
100
80
60
40
20
VDD CURRENT ( µA)
VIO CURRENT (µ A)
–55 TEMPERATURE (°C)
–35 –15 525 45 65 85 105 125
f
S
= 200kSPS
VDD = 5V, INTERNAL4.096V REF
VDD = 5V, EXTERNAL REF
VDD = 2.5, EXTERNAL REF VIO
09822-021
Figure 21. Operating Currents vs. Temperature
AD7949-EP Enhanced Product
Rev. B | Page 12 of 12
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDS M O-220- WGGD-11.
4.10
4.00 SQ
3.90
0.80
0.75
0.70 0. 05 M AX
0.02 NO M
0.20 REF
0.20 M I N
COPLANARITY
0.08
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
1
20
6
10
11
15
16
5
BOTTOM VIEW
TOP VIEW
SIDE VIEW FO R P ROPE R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFI G URATI ON AND
FUNCTION DES CRI P TI ONS
SECTION OF THIS DATA SHEET.
10-12-2017-C
EXPOSED
PAD
PKG-003578
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPT IO NS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 22. 20-Lead Lead Frame Chip Scale Package (LFCSP)
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature
Range Package Description
Package
Option
Ordering
Quantity
AD7949SCPZ-EP-RL7 –55°C to +125°C 20-Lead LFCSP, 7” Tape and Reel CP-20-10 1,500
AD7949SCPZ-EP-R2 –55°C to +125°C 20-Lead LFCSP, 7” Tape and Reel CP-20-10 1,500
1 Z = RoHS Compliant Part.
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D09822-0-5/18(B)