eroflex Circuit Technology - Advanced Multichip Modules © SCD1665 REV B 6/29/01
General Description
The ACT–F512K32 is a high
speed, 16 megabit CMOS flash
multichip module (MCM)
designed for full temperature
range military, space, or high
reliability applications.
The MCM can be organized
as a 512K x 32bits, 1M x 16bits
or 2M x 8bits device and is input
TTL and output CMOS
compatible. The command
register is written by bringing
WE to a logic low level (VIL),
while CE is low and OE is at
logic high level (VIH). Reading is
accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The ACT–F512K32 is
packaged in a hermetically
Features
512Kx8 512Kx8 512Kx8 512Kx8
CE4
OE
A0 – A18
I/O0-7 I/O8-15 I/O16-23 I/O24-31
8888
CE3WE4
WE3
WE2
WE1CE1CE2
Block Diagram – PGA Type Package(P3,P7) & CQFP(F5)
Pin Description
I/O0-31 Data I/O
A0–18 Address Inputs
WE1-4 Write Enables
CE1-4 Chip Enables
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
■ 4 Low Power 512K x 8 FLASH Die in One MCM
Package
■ TTL Compatible Inputs and CMOS Outputs
■ Access Times of 60, 70, 90, 120 and 150ns
■ +5V Programing, 5V ±10% Supply
■ 100,000 Erase/Program Cycles
■ Low Standby Current
■ Page Program Operation and Internal Program
Control Time
■ Sector Architecture (Each Die)
● 8 Equal size sectors of 64K bytes each
● Any Combination of Sectors can be erased with
one command sequence
● Supports full chip erase
■ Embedded Erase and Program Algorithms
■ MIL-PRF-38534 Compliant MCMs Available
■ Industry Standard Pinouts
■ Packaging – Hermetic Ceramic
● 68 Lead, .88" x .88" x .160" Single-Cavity Small
Outline gull wing, Aeroflex code# "F5"
(Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No
Shoulder, Aeroflex code# "P3"
● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
■ Internal Decoupling Capacitors for Low Noise
Operation
■ Commercial, Industrial and Military Temperature
Ranges
■ DESC SMD# 5962–94612
Released (P3,P7,F5)
ACT–F512K32 High Speed
16 Megabit FLASH Multichip Module
CIRCUIT TECHNOLOGY
www.aeroflex.com
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sealed co-fired ceramic 66 pin, 1.08"SQ PGA
or a 68 lead, .88"SQ Ceramic Gull Wing CQFP
package for operation over the temperature
range of -55°C to +125°C and military
environment.
Each flash memory die is organized as
512KX8 bits and is designed to be
programmed in-system with the standard
system 5.0V Vcc supply. A 12.0V VPP is not
required for write or erase operations. The
MCM can also be reprogrammed with standard
EPROM programmers (with the proper socket).
The standard ACT–F512K32 offers access
times between 60ns and 150ns, allowing
operation of high-speed microprocessors
without wait states. To eliminate bus
contention, the device has separate chip
enable (CE) and write enable (WE). The
ACT-F512K32 is command set compatible with
JEDEC standard 4 Mbit EEPROMs.
Commands are written to the command
register using standard microprocessor write
timings. Register contents serve as input to an
internal state-machine which controls the
erase and programming circuitry. Write cycles
also internally latch addresses and data
needed for the programming and erase
operations.
Reading data out of the device is similar to
reading from 12.0V Flash or EPROM devices.
The ACT-F512K32 is programmed by
executing the program command sequence.
This will invoke the Embedded Program
Algorithm which is an internal algorithm that
automatically times the program pulse widths
and verifies proper cell margin. Typically, each
sector can be programmed and verified in less
than one second. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm
which is an internal algorithm that
automatically preprograms the array, (if it is not
already programmed) before executing the
erase operation. During erase, the device
automatically times the erase pulse widths and
verifies proper cell margin.
Each die in the module or any individual
sector of the die is typically erased and verified
in 1.5 seconds (if already completely
preprogrammed).
Each die also features a sector erase
architecture. The sector mode allows for 64K
byte blocks of memory to be erased and
reprogrammed without affecting other blocks.
The ACT-F512K32 is erased when shipped
from the factory.
The device features single 5.0V power
supply operation for both read and write
functions. lnternally generated and regulated
voltages are provided for the program and
erase operations. A low VCC detector
automatically inhibits write operations on the
loss of power. The end of program or erase is
detected by Data Polling of D7 or by the Toggle
Bit feature on D6. Once the end of a program
or erase cycle has been completed, the device
internally resets to the read mode.
All bits of each die, or all bits within a
sector of a die, are erased via
Fowler-Nordhiem tunneling. Bytes are
programmed one byte at a time by hot electron
injection.
DESC Standard Military Drawing (SMD)
numbers are released.
General Description, Cont’d,
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z Absolute Maximum Ratings
Parameter Symbol Range Units
Case Operating Temperature TC-55 to +125 °C
Storage Temperature Range TSTG -65 to +150 °C
Supply Voltage Range VCC -2.0 to +7.0 V
Signal Voltage Range (Any Pin Except A9) Note 1 VG-2.0 to +7.0 V
Maximum Lead Temperature (10 seconds) -300 °C
Data Retention -10Years
Endurance (Write/Erase cycles) - 100,000 Minimum
A9 Voltage for sector protect, Note 2 VID -2.0 to +14.0 V
Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0v for periods of up to
20ns. Maximum DC voltage on input and I/O pins is VCC + 0.5V. During voltage transitions, inputs and I/O pins may overshoot to
VCC + 2.0V for periods up to 20 ns.
Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.
Normal Operating Conditions
Symbol Parameter Minimum Maximum Units
VCC Power Supply Voltage +4.5 +5.5 V
VIH Input High Voltage +2.0 VCC + 0.5 V
VIL Input Low Voltage -0.5 +0.8 V
T
AOperating Temperature (Military) -55 +125 °C
VID A9 Voltage for sector protect 11.5 12.5 V
Capacitance
(VIN= 0V, f = 1MHz, Tc = 25°C)
Symbol Parameter Maximum Units
CAD A0 – A16 Capacitance 50 pF
COE OE Capacitance 50 pF
CWE Write Enable Capacitance
CQFP(F5) Package 20 pF
PGA(P3,P7) Package 20 pF
CCE Chip Enable Capacitance 20 pF
CI/OI/O0 – I/O31 Capacitance 20 pF
Parameters Guaranteed but not tested
DC Characteristics – CMOS Compatible
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C, unless otherwise indicated)
Parameter Sym Conditions Speeds 60, 70, 90, 120 & 150ns
Minimum Maximum Units
Input Leakage Current ILI VCC = 5.5V, ViN = GND to VCC 10 µA
Output Leakage Current ILOX32 VCC = 5.5V, ViN = GND to VCC 10 µA
Active Operating Supply Current for Read (1) ICC1CE = VIL, OE = VIH, f = 5MHz 190 mA
Active Operating Supply Current for Program or Erase (2) ICC2CE = VIL, OE = VIH 240 mA
Standby Supply Current ICC4VCC = 5.5V, CE = VIH, f = 5MHz 6.5 mA
Static Supply Current (4) ICC3VCC = 5.5V, CE = VIH 0.6 mA
Output Low Voltage VOL IOL = +8.0 mA, VCC = 4.5V 0.45 V
Output High Voltage VOH IOH = –2.5 mA, VCC = 4.5V 0.85 x VCC V
Low Power Supply Lock-Out Voltage (4) VLKO 3.2 4.2 V
Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 5 MHz). The frequency
component typically is less than 2 mA/MHz, with OE at VIN.
Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress.
Note 3. DC Test conditions: VIL = 0.3V, VIH = VCC - 0.3V, unless otherwise indicated
Note 4. Parameter Guaranteed but not tested.
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AC Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Parameter Symbol
JEDEC Stand’d
–60
Min Max
–70
Min Max
–90
Min Max
–120
Min Max
–150
Min Max Units
Read Cycle Time tAVAV tRC 60 70 90 120 150 ns
Address Access Time tAVQV tACC 60 70 90 120 150 ns
Chip Enable Access Time tELQV tCE 60 70 90 120 150 ns
Output Enable to Output Valid tGLQV tOE 30 35 35 50 55 ns
Chip Enable to Output High Z (1) tEHQZ tDF 20 20 20 30 35 ns
Output Enable High to Output High Z (1) tGHQZ tDF 20 20 20 30 35 ns
Output Hold from Address, CE or OE Change, Whichever is First tAXQX tOH 00000 ns
Note 1. Guaranteed by design, but not tested.
AC Characteristics – Write/Erase/Program Operations, WE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Parameter Symbol
JEDEC Stand’d
–60
Min Max
–70
Min Max
–90
Min Max
–120
Min Max
–150
Min Max Units
Write Cycle Time tAVAC tWC 60 70 90 120 150 ns
Chip Enable Setup Time tELWL tCE 00000 ns
Write Enable Pulse Width tWLWH tWP 40 45 45 50 50 ns
Address Setup Time tAVWL tAS 00000 ns
Data Setup Time tDVWH tDS 40 45 45 50 50 ns
Data Hold Time tWHDX tDH 00000 ns
Address Hold Time tWLAX tAH 45 45 45 50 50 ns
Write Enable Pulse Width High tWHWL tWPH 20 20 20 20 20 ns
Duration of Byte Programming tWHWH114 TYP 14 TYP 14 TYP 14 TYP 14 TYP µs
Sector Erase Time tWHWH230 30 30 30 30 Sec
Chip Erase Time tWHWH3120 120 120 120 120 Sec
Read Recovery Time before Write (2) tGHWL 00000 µs
Vcc Setup Time (2) tVCE 50 50 50 50 50 µs
Chip Programming Time 50 50 50 50 50 Sec
Output Enable Setup Time (2) tOES 00000 ns
Output Enable Hold Time (1) (2) tOEH 10 10 10 10 10 ns
Notes: 1. For Toggle and Data Polling. 2. Guaranteed by design, but not tested.
AC Characteristics – Write/Erase/Program Operations, CE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Parameter Symbol
JEDEC Stand’d
–60
Min Max
–70
Min Max
–90
Min Max
–120
Min Max
–150
Min Max Units
Write Cycle Time tAVAC tWC 60 70 90 120 150 ns
Write Enable Setup Time tWLELtWS 00000 ns
Chip Enable Pulse Width tELEH tCP 40 45 45 50 50 ns
Address Setup Time tAVEL tAS 00000 ns
Data Setup Time tDVEH tDS 40 45 45 50 50 ns
Data Hold Time tEHDX tDH 00000 ns
Address Hold Time tELAX tAH 45 45 45 50 50 ns
Chip Enable Pulse Width High tEHEL tCPH 20 20 20 20 20 ns
Duration of Byte Programming Operation tWHWH114TYP14TYP14TYP14TYP14TYP µs
Sector Erase Time tWHWH230 30 30 30 30 Sec
Chip Erase Time tWHWH3120 120 120 120 120 Sec
Read Recovery Time Before Write (1) tGHEL 00000 µs
Chip Programming Time 50 50 50 50 50 Sec
1. Guaranteed by design, but not tested.
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Device Operation
The ACT-F512K32 MCM is composed of four, four
megabit Flash chips. The following description is for the
individual flash device, is applicable to each of the four
memory chips inside the MCM. Chip 1 is distinguished by
CE1 and I/O1-7, Chip 2 by CE2 and I/08-15, Chip 3 by CE3
and I/016-23, and Chip 4 by CE4 and I/024-31.
Programming of the ACT-F512K32 is accomplished by
executing the program command sequence. The
program algorithm, which is an internal algorithm,
automatically times the program pulse widths and verifies
proper cell status. Sectors can be programed and
verified in less than one second. Erase is accomplished
by executing the erase command sequence. The erase
algorithm, which is internal, automatically preprograms
the array if it is not already programed before executing
the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell status. The entire memory is typically erased
and verified in 1.5 seconds (if pre-programmed). The
sector mode allows for 64K byte blocks of memory to be
erased and reprogrammed without affecting other blocks.
Bus Operation
READ
The ACT-F512K32 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output-Enable (OE)
is the output control and should be used to gate data to
the output pins of the chip selected. Figure 7 illustrates
AC read timing waveforms.
OUTPUT DISABLE
With Output-Enable at a logic high level (VIH), output from
the device is disabled. Output pins are placed in a high
impedance state.
STANDBY MODE
The ACT-F512K32 standby mode consumes less than
6.5 mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input.
If the device is deselected during erasure or
programming, the device will draw active current until the
operation is completed.
WRITE
Device erasure and programming are accomplished via
the command register. The contents of the register serve
as input to the internal state machine. The state machine
outputs dictate the function of the device.
The command register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and data
information needed to execute the command. The
command register is written by bringing WE to a logic low
level (VIL), while CE is low and OE is at VIH. Addresses
are latched on the falling edge of WE or CE, whichever
happens later. Data is latched on the rising edge of the
WE or CE whichever occurs first. Standard
microprocessor write timings are used. Refer to AC
Program Characteristics and Waveforms, Figures 3,
8 and 13.
Command Definitions
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. The device will automatically
power-up in the read/reset state. In this case, a
command sequence is not required to read data.
Standard Microprocessor read cycles will retrieve array
data. This default value ensures that no spurious
alteration of the memory content occurs during the power
transition. Refer to the AC Read Characteristics and
Figure 7 for the specific timing parameters.
Table 1 – Bus Operations
Operation CE OE WE A0 A1 A6 A9 I/O
READ LLHA
0A1A6A9DOUT
STANDBY HXXXXXXHIGH Z
OUTPUT DISABLE LHHXXXXHIGH Z
WRITE LHLA
0A1A6A9DIN
ENABLE SECTOR
PROTECT LV
ID LXXXV
ID X
VERIFY SECTOR
PROTECT LLHLHLV
ID Code
Table 2 – Sector Addresses Table
A18 A17 A16 Address Range
SA0 0 0 0 00000h – 0FFFFh
SA1 0 0 1 10000h – 1FFFFh
SA2 0 1 0 20000h – 2FFFFh
SA3 0 1 1 30000h – 3FFFFh
SA4 1 0 0 40000h – 4FFFFh
SA5 1 0 1 50000h – 5FFFFh
SA6 1 1 0 60000h – 6FFFFh
SA7 1 1 1 70000h – 7FFFFh
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BYTE PROGRAMING
The device is programmed on a byte-byte basis.
Programming is a four bus cycle operation. There are
two "unlock" write cycles. These are followed by the
program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE,
whichever occurs later, while the data is latched on the
rising edge of CE or WE whichever occurs first. The
rising edge of CE or WE (whichever occurs first) begins
programming. Upon executing the Embedded Program
Algorithm command sequence the system is
not
required to provide further controls or timings. The
device will automatically provide adequate internally
generated program pulses and verify the programmed
cell margin. The automatic programming operation is
completed when the data on D7 is equivalent to data
written to this bit at which time the device returns to the
read mode and addresses are no longer latched.
Therefore, the device requires that a valid address to the
device be supplied by the System at this time. Data
Polling must be performed at the memory location which
is being programmed.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data "0" cannot be
programmed back to a “1". Attempting to do so may
cause the device to exceed programming time limits (D5
= 1) or result in an apparent success, according to the
data polling algorithm, but a read from reset/read mode
will show that the data is still “0". Only erase operations
can convert “0"s to “1"s.
Figure 3, 8 and 13 illustrates the programming algorithm
using typical command strings and bus operations.
CHIP ERASE
Chip erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command. Two more"unlock" write cycles are
then followed by the chip erase command.
Chip erase does
not require
the user to program the
Embedded Erase Algorithm (Figure 4) sequence the
device automatically will program and verify the entire
memory for an all zero data pattern prior to electrical
erase. The chip erase is performed sequentially one
sector at a time.
Note: Post Erase data state is all "1"s
.
The system is not required to provide any controls or
timings during these operations.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data in D7 is "1" (see Write Operation Status
section - Table 4) at which time the device returns to
read the mode. See Figures 4 and 9.
SECTOR ERASE
Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"setup" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(data) is latched on the rising edge of WE. A time-out of
80µs from the rising edge of the last sector erase
command will initiate the sector erase command(s).
Please note: Do not attempt to write an invalid
command sequence during the sector erase operation.
otherwise, it wili terminate the sector erase operation
and the device will reset back into the read mode
.
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the sector erase
command (30H) to addresses in other sectors desired to
be concurrently erased. The time between writes must
be less than 80µs, otherwise that command will not be
accepted. A time-out of 80µs from the rising edge of
the WE pulse for the last sector erase command will
initiate the sector erase. If another sector erase
command is written within the 80µs time-out window the
Table 3 — Commands Definitions
Command
Sequence
Bus
Write
Cycles
First Bus Write
Cycle
Second Bus Write
Cycle
Third Bus Write
Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus Write
Cycle
Sixth Bus Write
Cycle
Required Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1 XXXH F0H
Read/Reset 4 5555H AAH 2AAAH 55H 5555H F0H RA RD
Autoselect 4 5555H AAH 2AAAH 55H 5555H 90H
Byte Program 6 5555H AAH 2AAAH 55H 5555H A0H PA PD
Chip Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H
Sector Erase Suspend Erase can be suspended during sector erase with Address (Don’t care), Data (B0H)
Sector Erase Resume Erase can be resumed after suspend with Address (Don’t care), Data (30H)
NOTES:
1. Address bit A15, A16, A17 and A18 = X = Don't Care. Write Sequences may be initiated with A15 in either state.
2. Address bit A15, A16, A17 and A18 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector.
4. RD = Data read from location RA during read Operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
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timer is reset. Any command other than sector erase
within the time-out window will reset the device to the
read mode, ignoring the previous command string.
Loading the sector erase buffer may be done in any
sequence and with any number of sectors (1 to 8).
Sector erase does
not
require the user to program the
device prior to erase. The device automatically
programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not
affected. The system is
not
required to provide any
controls or timings during these operations. Post Erase
data state is all "1"s.
The automatic sector erase begins after the 80µs time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on D7 is “1" at which time the device returns to
read mode.
During the execution of the Sector Erase
command, only the Erase Suspend and Erase Resume
commands are allowed. All other commands will reset
the device to read mode
. Data Polling must be
performed at an address within any of the sectors being
erased.
Data Protection
The ACT-F512K32 is designed to offer protection
against accidental erasure or programming caused by
spurious system level singles that may exist during
power transitions. During power up the device
automatically resets the internal state machine in the
read mode. Also, with its control register architecture,
alteration of the memory content only occurs after
successful completion of specific multi-bus cycle
command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from Vcc power-up
and power-down transitions or system noise.
LOW Vcc WRITE INHIBIT
To avoid initiation of a write cycle during Vcc power-up
and power-down, a write cycle is locked out for VCC less
than 3.2V (typically 3.7V). If VCC <V
LKO, the command
register is disabled and all internal program/erase
circuits are disabled. Under this condition the device will
reset to read mode. Subsequent writes will be ignored
until the Vcc level is greater than VLKO. It is the users
responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when Vcc is
above 3.2V.
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5ns (typical) on OE, CE or
WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding anyone of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be logical zero while OE is a logical one.
POWER-UP WRITE INHIBIT
Power-up of the device with WE = CE = VIL and OE =
VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the
read mode on power-up.
Write Operation Status
D7
DATA POLLING
The ACT-F512K32 features Data Polling as a method to
indicate to the host that the internal algorithms are in
progress or completed. During the program algorithm,
an attempt to read the device will produce compliment
data of the data last written to D7. During the erase
algorithm, an attempt to read the device will produce a
"0" at the D7 Output. Upon completion of the erase
algorithm an attempt to read the device will produce a
"1" at the D7 Output.
For chip Erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse
sequence. For sector erase, the Data Polling is valid
after the last rising edge of the sector erase WE pulse.
Data polling must be performed at a sector address
within any of the sectors being erased and not a
protected sector. Otherwise, the status may not be valid.
Once the algorithm operation is close to being
completed, data pins (D7) change asynchronously while
the output enable (OE) is asserted low. This means that
the device is driving status information on D7 at one
instance of time and then that byte's valid data at the
next instant of time. Depending on when the system
samples the D7 Output, it may read the status or valid
data. Even if the device has completed internal
algorithm operation and D7 has a valid data, the data
outputs on D0 - D6 may be still invalid. The valid data on
D0 - D7 will be read on the successive read attempts.
The Data Polling feature is only active during the
programming algorithm, erase algorithm, or sector erase
time-out.
See Figures 6 and 10
D6
TOGGLE BIT
The ACT-F512K32 also features the "Toggle Bit" as a
method to indicate to the host system that algorithms
are in progress or completed.
During a program or erase algorithm cycle, successive
attempts to read data from the device will result in D6
toggling between one and zero. Once the program or
erase algorithm cycle is completed, D6 Will stop toggling
and valid data will be read on successive attempts.
During programming the Toggle Bit is valid after the
rising edge of the fourth WE pulse in the four write pulse
sequence. For chip erase the Toggle Bit is valid after the
rising edge of the sixth WE pulse in the six write pulse
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sequence. For Sector erase, the Toggle Bit is valid after
the last rising edge of the sector erase WE pulse. The
Toggle Bit is active during the sector time out.
See Figure 1 and 5.
D5
EXCEEDED TIMING LIMITS
D5 will indicate if the program or erase time has
exceeded the specified limits. Under these conditions
D5 will produce a "1". The Program or erase cycle was
not successfully completed. Data Polling is the only
operation function of the device under this condition.
The CE circuit will partially power down the device under
these conditions by approximately 8 mA per chip. The
OE and WE pins will control the output disable functions
as shown in Table 1. To reset the device, write the reset
command sequence to the device. This allows the
system to continue to use the other active sectors in the
device.
D3
SECTOR ERASE TIMER
After the completion of the initial sector erase command
sequence the sector erase time-out will begin. D3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, D3 may be
used to determine if the sector erase timer window is still
open. If D3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If D3 is low ("0"), the device will accept
additional sector erase commands. To ensure the
command has been accepted, the software should
check the status of D3 prior to and following each
subsequent sector erase command. If D3 were high on
the second status check, the command may not have
been accepted. See Table 4
Sector Protection
Algorithims
SECTOR PROTECTION
The ACT-F512K32 features hardware sector protection
which will disable both program and erase operations to
an individual sector or any group of sectors. To activate
this mode, the programming equipment must force VID
on control pin OE and address pin A9. The sector
addresses should be set using higher address lines A18,
A17, and A16. The protection mechanism begins on the
falling edge of the WE pulse and is terminated with the
rising edge of the same.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 with CE and OE at VIL and WE at VIH. Scanning the
sector addresses (A16, A17, and A18) while (A6, A1, A0)
= (0, 1, 0,) will produce a logical "1" code at device
output D0 for a protected sector. Otherwise the device
will read 00H for unprotected sector. In this mode, the
lower order addresses, except for 0, A1, and A6 are don't
care.
It is also possible to verify if a sector is protected during
the sector protection operation. This is done by setting
A6 = CE = OE = VIL and WE = VIH (A9 remains high at
VID). Reading the device at address location XXX2H,
where the higher order addresses (AL8, A17, and A16)
define a particular sector, will produce 01H at data
outputs (D0 - D7) for a protected sector.
SECTOR UNPROTECT
The ACT-F512K32 also features a sector unprotect
mode, so that a protected sector may be unprotected to
incorporate any changes in the code. All sectors should
be protected prior to unprotecting any sector.
To activate this mode, the programming equipment must
force Vid on control pins OE, CE, and address pin A9.
The address pins A6, A16, and A12 should be set to VIH.
The unprotection mechanism begins on the falling edge
of the WE pulse and is terminated with the rising edge of
the same.
It is also possible to determine if a sector is unprotected
in the system by writing the autoselect command and A6
is set at VIH. Performing a read operation at address
location XXX2H, where the higher order addresses (A18,
A17, and A16) define a particular sector address, will
produce 00H at data outputs (D0-D7) for an unprotected
sector.
AA
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9
CE
WE
OE
Data
D0-D7
tOEH
tOES
D6=Toggle D6
Valid
tOE
D6=Toggle Stop Toggle
D0-D7
Figure 1
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
IOL
Parameter Typical Units
Input Pulse Level 0 – 3.0 V
Input Rise and Fall 5 ns
Input and Output Timing Reference Level 1.5 V
Output Lead Capacitance 50 pF
Notes:
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance
ZO=75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical
resistance load circuit. 6) ATE Tester includes jig capacitance.
IOH
To Device Under Test VZ ~ 1.5 V (Bipolar Supply)
Current Source
Current Source
CL =
50 pF
Figure 2
AC Test Circuit
Table 4 — Hardware Sequence Flags
In Progress
Status D7D6D5D3D2 – D0
Auto-Programming D7Toggle00 D
Programming in Auto Erase 0Toggle01
Exceeding Time Limits Auto-Programming D7Toggle11 D
Programming in Auto Erase 0Toggle11
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Bus
Operations
Command
Sequence Comments
Standby
Write Program Valid Address/Data Sequence
Read Data Polling to Verify Programming
Standby Compare Data Output to Data Expected
Figure 3
Programming Algorithm
Start
Data Poll Device
Last Address
Increment
Address
(See Below)
No
Yes
Programming Complete
5555H/AAH
2AAAH/55H
5555H/A0H
Programming Address/Program Data
Program Command Sequence (Address/Command):
?
Write Program Command Sequence
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11
Bus
Operations
Command
Sequence Comments
Standby
Write Erase
Read Data Polling to Verify Erasure
Standby Compare Output to FFH
Figure 4
Erase Algorithm
Start
Erasure Completed
Write Erase Command Sequence
(See Below)
Data Poll or Toggle Bit
Successfully Completed
Chip Erase Command Sequence
(Address/Command)
Individual Sector/Multiple Sector
(Address/Command)
Erase Command Sequence
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/AAH
2AAAH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
Additional Sector
Erase Commands
are Optional
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12
Start
Read Byte
D0-D7
Address = VA
D6 = Toggle
D5 = 1
Read Byte
D0-D7
Address = VA
Fail
Pass
Yes
No
No
Yes
No
?
D6 =
Toggle?
(Note 1)
Yes
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
Figure 5
Toggle Bit Algorithm
Start
Read Byte
D0-D7
Address = VA
D7 = Data
D5 = 1
Read Byte
D0-D7
Address = VA
Fail
Pass
Yes
No
No
Yes
No
D7 =
Togg le?
(Note 1)
Yes
Figure 6
Data Polling Algorithm
Note 1. D6 is rechecked even if D5 = "1" because D6 may stop toggling at
the same time as D5 changes to "1".
Note 1. D7 is rechecked even if D5 = "1" because D7 may change
simultaneously with D5.
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
? ?
?
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AC Waveforms for Read Operations
Figure 7
tOH
tCE
tOE
tACC
tRC
tDF
Output Valid High ZHigh Z
Outputs
OE
WE
CE
Addresses Addresses Stable
WE
OE
CE
Data
Addresses
5.0V
5555H PA
Data Polling
PA
D7 DOUT
PDAOH
tWHWH1
tOE
tRC
tCE
tDF
tOH
tAH
tAS
tDH
tWPH
tWP
tDS
tCE
tWC
Write/Erase/Program
Figure 8
Operation, WE Controlled
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the deviced.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
tGHWL
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AC Waveforms Chip/Sector
Figure 9
Erase Operations
Data
Addresses
VCC
5555H
Data Polling
tAH
CE
tAS
WE
5555H 5555H SA2AAAH 2AAAH
tGHWL
tWP
tWPH
tDS
tDH
tCE
tVCE
55H AAH80H 55H 10H/30HAAH
OE
Notes:
1. SA is the sector address for sector erase.
AC Waveforms for Data Polling
Figure 10
During Embedded Algorithm Operations
tOE
tCH
tWHWH1 or 2
tOE
tOH
tDF
tCE
tOEH
*
* DQ7=Valid Data (The device has completed the Embedded operation).
DQ0–DQ6=Invalid
DQ7DQ7=
Valid Data
DQ0–DQ6
Valid Data
High Z
CE
DQ7
OE
WE
DQ0-DQ6
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Start
Data = 01H
Set Up Sector Address
(A18, A17, A16)
Figure 11
Sector Protection Algorithm
PLSCNT = 1
A9 = VID, CE = VIL
OE = VID
Activate WE Pulse
Time Out 100µs
Power Down OE
A9 Should Remain VID
CE = OE = VIL
WE = VIH
Address = SA, A0 = 0, A1 = 1, A6 = 0
Read From Sector
PLSCNT = 25?
Increment
PLSCNT
Protect
Sector?
Another
Device Failure
Remove VID from A9
Write Reset Command
Sector Protection
Complete
Yes
Yes
No
No
No
?
Yes
AA
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Notes:
SA0 = Sector Address for initial sector
SA7 = Sector Address for last sector
Please refer to Table 2 for details
Sector Unprotect Algorithm
Figure 12
Data = 00H PLSCNT = 1000
Address = SA7
Sector Device Failure
Remove VID OR VSP from A9
Sector Unprotect
Completed
Yes
Yes
No
Set OE = VIL, WE = VIH
A6 = VIH, A9 = VID OR VSP
?
Read Data
From Device
Increment
PLSCNT
Increment
Sector Address No
?
Yes
No
?
Set Up Sector Address
Unprotected Mode
(A5 = VIH, A9 = VIL)
WE = VSP
Set OE = VID OR VSP
PLSCNT = 1
StartStart
Protect All Sectors
Device Code
Verify 98403/98406
Activate CE Pulse
Time Out 5 mS
CE = VIL
Set A1, A0 = 1, 0
Setup Sector Address SA0
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CE
OE
WE
Data
Addresses
5.0V
5555H PA
Data Polling
PA
D7 DOUT
PDAOH
tWHWH1
tAHtAS
tDH
tCPH
tCP
tDS
tWS
tWC
tGHEL
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Alternate CE Controlled Programming Operation Timings
Figure 13
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Pin Numbers & Functions
66 Pins — PGA
Pin# Function Pin# Function Pin# Function Pin# Function
1I/O
818 A15 35 I/O25 52 WE3
2I/O
919 Vcc 36 I/O26 53 CE3
3I/O
10 20 CE137 A754 GND
4A
14 21 NC 38 A12 55 I/O19
5A
16 22 I/O339 NC 56 I/O31
6A
11 23 I/O15 40 A13 57 I/O30
7A
024 I/O14 41 A858 I/O29
8A
18 25 I/O13 42 I/O16 59 I/O28
9I/O
026 I/O12 43 I/O17 60 A1
10 I/O127 OE 44 I/O18 61 A2
11 I/O228 A17 45 VCC 62 A3
12 WE229 WE146 CE463 I/O23
13 CE230 I/O747 WE464 I/O22
14 GND 31 I/O648 I/O27 65 I/O21
15 I/O11 32 I/O549 A466 I/O20
16 A10 33 I/O450 A5
17 A934 I/O24 51 A6
1.085 SQ
1.000
.600
1.000
.100
.020
.016
.100
.180
TYP
1.030
1.040
.160
Pin 56
Pin 66
Pin 11
Pin 1
Bottom View (P7 & P3)
MAX
MAX
"P3" — 1.08" SQ PGA Type (without shoulder) Package
"P7" — 1.08" SQ PGA Type (with shoulder) Package
1.030
1.040
.020
.016
.100
.025
.185
MAX
Side View
(P7)
Side View
(P3)
.050
.180
TYP
.035
All dimensions in inches
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Pin Numbers & Functions
68 Pins — CQFP Package
Pin# Function Pin# Function Pin# Function Pin# Function
1GND18GND35OE 52 GND
2CE
319 I/O836 CE253 I/O23
3A
520 I/O937 A17 54 I/O22
4A
421 I/O10 38 WE255 I/O21
5A
322 I/O11 39 WE356 I/O20
6A
223 I/O12 40 WE457 I/O19
7A
124 I/O13 41 A18 58 I/O18
8A
025 I/O14 42 NC 59 I/O17
9 NC 26 I/O15 43 NC 60 I/O16
10 I/O027 VCC 44 I/O31 61 VCC
11 I/O128 A11 45 I/O30 62 A10
12 I/O229 A12 46 I/O29 63 A9
13 I/O330 A13 47 I/O28 64 A8
14 I/O431 A14 48 I/O27 65 A7
15 I/O532 A15 49 I/O26 66 A6
16 I/O633 A16 50 I/O25 67 WE1
17 I/O734 CE151 I/O24 68 CE4
Top View
All dimensions in inches
0.015
0.990 SQ
±.010
0.880 SQ
±.010
0.800 REF
0.050
See Detail “A”
TYP
±.002
Pin 60
Pin 44
Pin 43Pin 27
Pin 26
Pin 10
Pin 9 Pin 61
Side View
0.946
±.010
0.160
MAX
Detail “A”
0.010
1°-7°
0.040
.010 R
0.010
±.005
REF
"F5" — Single-Cavity CQFP
AA
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Ordering Information
Model Number DESC Drawing Number Speed Package
ACT–F512K32N–060P3Q 5962–9461205HXX*60 ns PGA
ACT–F512K32N–070P3Q 5962–9461204HXX 70 ns PGA
ACT–F512K32N–090P3Q 5962–9461203HXX 90 ns PGA
ACT–F512K32N–120P3Q 5962–9461202HXX 120 ns PGA
ACT–F512K32N–150P3Q 5962–9461201HXX 150 ns PGA
ACT–F512K32N–060P7Q 5962–9461205HUX*60 ns PGA
ACT–F512K32N–070P7Q 5962–9461204HUX 70 ns PGA
ACT–F512K32N–090P7Q 5962–9461203HUX 90 ns PGA
ACT–F512K32N–120P7Q 5962–9461202HUX 120 ns PGA
ACT–F512K32N–150P7Q 5962–9461201HUX 150 ns PGA
ACT–F512K32N–060F5Q 5962–9461205HMX*60 ns CQFP
ACT–F512K32N–070F5Q 5962–9461204HMX 70 ns CQFP
ACT–F512K32N–090F5Q 5962–9461203HMX 90 ns CQFP
ACT–F512K32N–120F5Q 5962–9461202HMX 120 ns CQFP
ACT–F512K32N–150F5Q 5962–9461201HMX 150 ns CQFP
* Pending
CIRCUIT TECHNOLOGY
Part Number Breakdown
ACT– F 512K 32 N– 090 F5 Q
Aeroflex Circuit
Technology
Memory Type
F = FLASH EEPROM
Memory Depth
Options
Memory Width, Bits
N = None
Memory Speed, ns
Package Type & Size
Surface Mount Packages Thru-Hole Packages
F5 = .88"SQ 68 Lead
Single-Cavity CQFP
P3 = 1.075"SQ PGA 66 Pins W/O Shoulder
P7 = 1.075"SQ PGA 66 Pins With Shoulder
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screened *
Q = MIL-PRF-38534 Compliant/SMD if applicable
Screening
* Screened to the individual test methods of MIL-STD-883
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Telephone: (516) 694-6700
FAX: (516) 694-6715
Toll Free Inquiries: 1-(800) 843-1553
Specification subject to change without notice
