© Semiconductor Components Industries, LLC, 2017
October, 2017 − Rev. 2
1Publication Order Number:
ESDM3031/D
ESDM3031
ESD Protection Diode
Micro−Packaged Diodes for ESD Protection
The ESDM3031 is designed to protect voltage sensitive components
that require low capacitance from ESD and transient voltage events.
Excellent clamping capability, low capacitance, low leakage, and fast
response time, make these parts ideal for ESD protection on designs
where board space is at a premium.
Features
•Low Clamping Voltage
•Small Body Outline Dimensions: 0.62 mm x 0.32 mm
•Low Body Height: 0.3 mm
•Stand−off Voltage: 3.3 V
•IEC61000−4−2 Level 4 ESD Protection
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•mSD Card Protection
•Audio Line
•GPIO
MAXIMUM RATINGS
Rating Symbol Value Unit
IEC 61000−4−2 (ESD) Contact
Air
±30
±30
kV
Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C
Thermal Resistance, Junction−to−Ambient
°PD°
RqJA
250
400
mW
°C/W
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
Lead Solder Temperature − Maximum
(10 Second Duration)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
Device Package Shipping†
ORDERING INFORMATION
www.onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
ESDM3031MXT5G X3DFN2
(Pb−Free)
10000 / Tape &
Reel
X3DFN2
CASE 152AF
MARKING
DIAGRAM
PIN 1
5 = Specific Device Code
M = Date Code
12
M
5
Bi−Directional
IPP
IPP
V
I
IR
IT
IT
IR
VRWM
VCVBR
VRWM VC
VBR
ESDM3031
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2
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VCClamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM 3.3 V
Breakdown Voltage (Note 2) VBR IT = 1 mA 4.4 6.2 V
Reverse Leakage Current IRVRWM = 3.3 V 0.1 mA
Clamping Voltage (Note 3) VCIPP = 5 A 6.3 V
Clamping Voltage (Note 3) VCIPP = 10 A 8.0 V
Peak Pulse Current (Note 3) IPP tP = 8/20 ms11 A
Clamping Voltage
TLP (Note 4)
VCIPP = 16 A IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
7.2 V
Junction Capacitance CJVR = 0 V, f = 1 MHz 20 pF
Dynamic Resistance RDYN TLP Pulse 0.13 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
3. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform.
4. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
VOLTAGE (V)
TIME (ns)
−5
0
5
10
15
20
25
30
35
40
−20 0 20 40 60 80 100 120 140
VOLTAGE (V)
TIME (ns)
−40
−35
−30
−25
−20
−15
−10
−5
0
5
−20 0 20 40 60 80 100 120 140
ESDM3031
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3
Figure 3. Positive TLP I−V Curve Figure 4. Negative TLP I−V Curve
IR (A)
VR (V)
1.E−11
1.E−10
1.E−09
1.E−08
1.E−07
1.E−06
1.E−05
1.E−04
1.E−03
−8−6−4−20 2 4
Figure 5. IV Characteristics
68
ITLP (A)
VCTLP (V)
0
2
4
6
8
10
12
14
16
18
22
048121620
ITLP (A)
VCTLP (V)
−20
−18
−16
−14
−12
−10
−8
−6
−4
−2
0
−2−4−8−12 −16 −202 6 10 14 18 −6−10 −14 −180
20
−10 10−9−7−5−3−11 3 5 7 9
25
20
15
10
5
0
−5−4−3−2−1012345
VBIAS (V)
Figure 6. Line Capacitance, f = 1 MHz
C (pF)
10
VC @ IPK (V)
0
IPK (A)
Figure 7. Positive Clamping Voltage vs. Peak
Pulse Current (tp = 8/20 ms)
9
8
7
6
5
4
3
2
1
01614121024 86
10
VC @ IPK (V)
0
IPK (A)
Figure 8. Negative Clamping Voltage vs. Peak
Pulse Current (tp = 8/20 ms)
9
8
7
6
5
4
3
2
1
0121024 86
ESDM3031
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5
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 11. IEC61000−4−2 Spec
Figure 12. Diagram of ESD Test Setup
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
50 W
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 13. 8 x 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
ESDM3031
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6
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 14. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 15 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
Figure 14. Simplified Schematic of a Typical TLP
System
DUT
LS
÷
Oscilloscope
Attenuator
10 MW
VC
VM
IM
50 W Coax
Cable
50 W Coax
Cable
Figure 15. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
DATE 17 FEB 2015
SCALE 8:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A B
E
D
BOTTOM VIEW
b
e
2X
L22X
TOP VIEW
2X
A
A1
0.05 C
0.05 C
CSEATING
PLANE
SIDE VIEW
DIM MIN MAX
MILLIMETERS
A0.25 0.33
A1 −−− 0.05
b0.22 0.28
e0.355 BSC
L2 0.17 0.23
MOUNTING FOOTPRINT*
DIMENSIONS: MILLIMETERS
0.74
1
0.30
0.31
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
2
1
GENERIC
MARKING DIAGRAM*
PIN 1
X = Specific Device Code
M = Date Code
XM
See Application Note AND8398/D for more mounting details
A
M
0.05 BC
A
M
0.05 BC
2X
2X
RECOMMENDED
PIN 1
INDICATOR
(OPTIONAL)
D0.58 0.66
E0.28 0.36
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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X3DFN2, 0.62X0.32, 0.355P, (0201)
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