ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS87016 is a low skew, 1:16 LVCMOS/ LVTTL Clock Generator and is a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions. The device has 4 banks of 4 outputs and each bank can be independently selected for /1 or /2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. * Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs) The divide select inputs, DIV_SELA:DIV_SELD, control the output frequency of each bank. The output banks can be independently selected for /1 or /2 operation. The bank enable inputs, CLK_ENA:CLK_END, support enabling and disabling each bank of outputs individually. The CLK_ENA:CLK_END circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, nMR/OE, resets the /1//2 flip flops and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. * Independent bank control for /1 or /2 operation The ICS87016 is characterized to operate with the core at 3.3V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and part-to-part skew characteristics make the 87016 ideal for those clock applications demanding welldefined performance and repeatability. * 0C to 85C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT ICS * Selectable differential CLK1, nCLK1 or LVCMOS clock input * CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * CLK0 supports the following input types: LVCMOS, LVTTL * Maximum output frequency: 250MHz * Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation * Asynchronous clock enable/disable * Output skew: 170ps (maximum) * Bank skew: 30ps (maximum) * Part-to-part skew: 750ps (maximum) * 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply * Available in both standard and lead-free RoHS compliant packages QA3 VDDOA QA2 GND QA1 VDDOA QA0 GND CLK_SEL nCLK1 CLK1 VDD nMR/OE D CLK0 CLK1 nCLK1 CLK_SEL 0 /1 1 1 /2 0 LE 4 QA0:QA3 VDD CLK0 DIV_SELA QB0:QB3 DIV_SELB DIV_SELC DIV_SELD CLK_ENA QC0:QC3 CLK_ENB CLK_ENC CLK_END nMR/OE QD0:QD3 GND D 1 LE 4 0 DIV_SELA D DIV_SELB 1 DIV_SELC 0 4 D DIV_SELD 1 CLK_ENA LE LE 4 0 ICS87016 GND QB0 VDDOB QB1 GND QB2 VDDOB QB3 GND QC0 VDDOC QC1 GND QC2 VDDOC QC3 GND QD0 VDDOD QD1 GND QD2 VDDOD QD3 CLK_ENB CLK_ENC 48-Pin LQFP 7mm x 7mm x 1.4mm body package Y Package Top View CLK_END 87016AY 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 www.icst.com/products/hiperclocks.html 1 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 48 VDD Power 2 CLK0 Input 3 DIV_SELA Input 4 DIV_SELB Input 5 DIV_SELC Input 6 DIV_SELD Input 7 CLK_ENA Input 8 CLK_ENB Input 9 CLK_ENC Input 10 CLK_END Input 11 nMR/OE Input 12, 16, 20, 24, 28, 32, 36, 40, 44 GND Power Power supply ground. Output Bank D outputs. LVCMOS / LVTTL interface levels. Power Output Bank D power supply pins. Output Bank C outputs. LVCMOS / LVTTL interface levels. Power Output Bank C power supply pins. Output Bank B outputs. LVCMOS / LVTTL interface levels. Power Output Bank B power supply pins. Output Bank A outputs. LVCMOS / LVTTL interface levels. 13, 15, 17, 19 14, 18 21, 23, 25, 27 22, 26 QD3, QD2, QD1, QD0 VDDOD QC3, QC2, QC1, QC0 VDDOC Type 38, 42 QB3, QB2, QB1, QB0 VDDOB QA3, QA2, QA1, QA0 VDDOA 45 CLK_SEL Input 46 47 nCLK1 CLK1 Input 29, 31, 33, 35 30, 34 37, 39, 41, 43 Description Positive supply pins. Pulldown LVCMOS / LVTTL clock input. Controls frequency division for Bank A outputs. Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs Pullup LVCMOS / LVTTL interface levels.. Controls frequency division for Bank C outputs. Pullup LVCMOS / LVTTL interface levels. Controls frequency division for Bank D outputs. Pullup LVCMOS / LVTTL interface levels. Output enable for Bank A outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank B outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank C outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Output enable for Bank D outputs. Active HIGH. Pullup If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. Master reset. When LOW, resets the /1//2 flip flops and sets the Pullup outputs to high impedance. LVCMOS / LVTTL interface levels. Power Output Bank A power supply pins. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 87016AY Input www.icst.com/products/hiperclocks.html 2 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions RPULLUP Input Pullup Resistor ROUT Typical Maximum 4 Units pF 51 Power Dissipation Capacitance (per output); NOTE 1 CPD Minimum k VDD, VDDOx = 3.465V 18 pF VDD = 3.465, VDDOx = 2.625V 20 pF VDD = 3.465, VDDOx = 1.89V 30 pF Output Impedance 7 NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD. TABLE 3. FUNCTION TABLE nMR/OE 0 Inputs CLK_ENx X DIV_SELx X Bank X Hi Z 1 1 1 1 1 0 0 1 X Active Active Low 87016AY Outputs Qx Frequency N/A fIN/2 fIN N/A www.icst.com/products/hiperclocks.html 3 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDOx + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C Symbol Parameter Positive Supply Voltage VDD Test Conditions VDDOx Output Supply Voltage; NOTE 1 IDD Power Supply Current IDDOx Output Supply Current; NOTE 2 Minimum 3.135 Typical 3.3 Maximum 3.465 Units V 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.71 1.8 1.89 V 100 mA 15 mA Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 3.465V 5 A VDD = VIN = 3.465V 150 A NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD. NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, and IDDOD. TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C Symbol Parameter VIH VIL IIH IIL VOH VOL IOZL Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions DIV_SELA:DIV_SELD, CLK_ENA:CLK_END, nMR/OE, CLK_SEL CLK0 DIV_SELA:DIV_SELD, CLK_ENA:CLK_END, nMR/OE, CLK_SEL CLK0 CLK_ENA:CLK_END, DIV_SELA:DIV_SELD, nMR/OE CLK0, CLK_SEL CLK_ENA:CLK_END, DIV_SELA:DIV_SELD, nMR/OE CLK0, CLK_SEL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Minimum Typical VDD = 3.465V, VIN = 0V -150 A VDD = 3.465V, VIN = 0V -5 A VDDOx = 3.3V 5%; NOTE 2 2.6 V VDDOx = 2.5V 5%; NOTE 2 1.8 V VDDOx = 1.8V 5%; NOTE 2 IOH = -2mA VDD - 0.45 V VDDOx = 3.3V 5%; NOTE 2 0.5 V VDDOx = 2.5V 5%; NOTE 2 0.5 V VDDOx = 1.8V 5%; NOTE 2 IOL = 2mA 0.45 V Output Tristate Current Low -5 A IOZH Output Tristate Current High 5 NOTE 1: Outputs terminated with 50 to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuit. NOTE 2: VDDOx denotes VDDOA, VDDOB, VDDOC and VDDOD. 87016AY www.icst.com/products/hiperclocks.html 4 A REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 85C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units nCLK1 VIN = VDD = 3.465V Test Conditions Minimum Typical 5 A CLK1 VIN = VDD = 3.465V 150 A nCLK1 VIN = 0V, VDD = 3.465V -150 A CLK1 VIN = 0V, VDD = 3.465V -5 A VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 1. 3 V VDD - 0.85 V Maximum Units 250 MH z TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 85C X Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low to High Test Conditions Minimum Typical t sk(b) CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 7 2.8 3.2 3.7 ns 2.9 3.4 3.9 ns Measured on the Rising Edge 30 ps t sk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge 150 ps t sk(pp) Par t-to-Par t Skew; NOTE 5, 7 tR / tF Output Rise/Fall Time; NOTE 6 odc Output Duty Cycle tEN Output Enable Time; NOTE 6 750 ps 20% to 80% 200 700 ps f < 175MHz 45 55 % f 175MHz 40 60 % 10 ns Output Disable Time; NOTE 6 10 tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VDDOX/2. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87016AY www.icst.com/products/hiperclocks.html 5 ns REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 85C X Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low to High t sk(b) Test Conditions CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 7 Measured on the Rising Edge Measured on the Rising Edge t sk(o) Output Skew; NOTE 3, 7 t sk(pp) Par t-to-Par t Skew; NOTE 5, 7 tR / tF Output Rise/Fall Time; NOTE 6 odc Output Duty Cycle tEN Output Enable Time; NOTE 6 Minimum Typical Maximum Units 250 MH z 2.9 3. 3 3.8 ns 3 3.5 4 ns 30 ps 160 ps 750 ps 200 700 ps f < 175MHz 45 55 % f 175MHz 40 60 % 10 ns 20% to 80% Output Disable Time; NOTE 6 10 tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VDDOX/2. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87016AY www.icst.com/products/hiperclocks.html 6 ns REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V5%, TA = 0C TO 85C X Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low to High t sk(b) Test Conditions CLK0; NOTE 1A CLK1, nCLK1; NOTE 1B Bank Skew; NOTE 2, 7 Measured on the Rising Edge Measured on the Rising Edge t sk(o) Output Skew; NOTE 3, 7 t sk(pp) Par t-to-Par t Skew; NOTE 5, 7 tR / tF Output Rise/Fall Time; NOTE 6 odc Output Duty Cycle tEN Output Enable Time; NOTE 6 Minimum Typical Maximum Units 250 MH z 3.1 3.8 4.5 ns 3.1 3.8 4.5 ns 30 ps 170 ps 750 ps 20% to 80% 200 700 ps f < 175MHz 45 55 % f 175MHz 40 60 % 10 Output Disable Time; NOTE 6 10 tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VDDOX/2. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87016AY www.icst.com/products/hiperclocks.html 7 ns ns REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V5% 2.05V5% SCOPE VDD, VDDOx SCOPE V DD VDDOx Qx LVCMOS 1.25V5% Qx LVCMOS GND GND -1.65V5% -1.25V5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.40.9V +0.9V5% VDD SCOPE V DD VDDOx nCLK1 Qx LVCMOS GND V Cross Points PP V CMR CLK1 -0.9V5% GND 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT PART 1 Qx PART 2 DIFFERENTIAL INPUT LEVEL V V DDOX DDOX Qx 2 V V DDOX Qy DDOX Qy 2 tsk(pp) PART-TO-PART SKEW 87016AY 2 2 tsk(o) OUTPUT SKEW www.icst.com/products/hiperclocks.html 8 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. QX0:QX3 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR VDDOX 2 Clock Outputs VDDOX 2 QX0:QX3 80% 80% 20% 20% tR tF tsk(b) BANK SKEW (where X denotes outputs in the same bank) OUTPUT RISE/FALL TIME V DDOX QAx, QBx, QCx, QDx 2 VDD 2 CLK0 t PW t nCLK1 PERIOD CLK1 odc = t PW x 100% t PERIOD VDDOX 2 QAx,QBx, QCx, QDx OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 87016AY tPD PROPAGATION DELAY www.icst.com/products/hiperclocks.html 9 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD VCC R1 1K Single Ended Clock Input R1 1K CLK CLK_IN + V_REF nCLK V_REF C1 0.1u R2 1K C1 0.1uF - R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. 87016AY www.icst.com/products/hiperclocks.html 10 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 2B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 87016AY BY www.icst.com/products/hiperclocks.html 11 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR SCHEMATIC EXAMPLE are shown in the application section of this data sheet. The single ended input CLK0 is driven by a 7 LVMCOS driver through series termination. The ICS87016 outputs are LVCMOS drivers. Series termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. Figure 3 shows an application schematic example of the ICS87016. This schematic provides examples of input and output handling. The differential CLK1/nCLK1 input can accept various types of differential signal. This example shows the ICS87016 input driven by a 3.3V LVPECL driver. Additional examples for the input driven by other types of drivers 3.3V Zo = 50 R1 ~43 Zo = 50 ~43 Zo = 50 Zo = 50 LVPECL VDDO R3 50 R4 50 VDD R5 50 Ro=7 Ohm LVCMOS 43 Zo = 50 Ohm 1 2 3 4 5 6 7 8 9 10 11 12 Ro+Rs=50 Ohm Set Logic Input to '1' VCC Set Logic Input to '0' VCC RU1 1K U1 ICS87016 RU2 SPARE To Logic Input pins GND QB0 VDDOB QB1 GND QB2 VDDOB QB3 GND QC0 VDDOC QC1 36 35 34 33 32 31 30 29 28 27 26 25 QD3 VDDOD QD2 GND QD1 VDDOD QD0 GND QC3 VDDOC QC2 GND Logic Input Pin Examples VDD CLK0 DIV_SELA DIV_SELB DIV_SELC DIV_SELD CLK_ENA CLK_ENB CLK_ENC CLK_END nMR/OE GND 13 14 15 16 17 18 19 20 21 22 23 24 RS VDD CLK1 nCLK1 CLK_SEL GND QA0 VDDOA QA1 GND QA2 VDDOA QA3 48 47 46 45 44 43 42 41 40 39 38 37 3.3V To Logic Input pins RD1 SPARE RD2 1K R2 VDD=3.3V VDDO=3.3V, 2.5V or 1.8V VDD VDDO (U1-1) C9 0.1u (U1-48) C10 0.1u (U1-14) C1 0.1u (U1-18) C2 0.1u (U1-22) (U1-26) C3 0.1u (U1-30) C4 0.1u (U1-34) C5 0.1u (U1-38) C6 0.1u (U1-42) C7 0.1u C8 0.1u FIGURE 3. APPLICATION SCHEMATIC EXAMPLE 87016AY www.icst.com/products/hiperclocks.html 12 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 48 LEAD LQFP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8C/W 47.9C/W 55.9C/W 42.1C/W 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87016 is: 2034 87016AY www.icst.com/products/hiperclocks.html 13 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR FOR 48 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC L 0.45 0.60 0.75 0 -- 7 ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 87016AY www.icst.com/products/hiperclocks.html 14 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS87016AY ICS87016AY 48 Lead LQFP tray 0C to 85C ICS87016AYT ICS87016AY 48 Lead LQFP 1000 tape & reel 0C to 85C ICS87016AYLF ICS87016AYLF 48 Lead "Lead-Free" LQFP tray 0C to 85C ICS87016AYLFT ICS87016AYLF 48 Lead "Lead-Free" LQFP 1000 tape & reel 0C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87016AY www.icst.com/products/hiperclocks.html 15 REV. A FEBRUARY 28, 2006 ICS87016 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR REVISION HISTORY SHEET Rev A Table T5A, T5B, T5C Page 6, 7, 8 A T5A & T5B A 6&7 12 A 1 A 12 1 10 A T8 87016AY 15 Description of Change AC Characteristics Table - corrected the first line in the Notes section, from "All parameters measured at 150MHz..." to 250MHz. Revised par t description title from "Differential-to-LVCMOS Clock Generator" to "LVCMOS Clock Generator". AC Characteristics Table - switched prop delay values for CLK0 and CLK1, nCLK1. Updated format. Modified Block Diagram, corrected latch block. 8/9/02 6/4/03 Added Schematic Example Features Section - added Lead-Free bullet. Application Section - added Recommendations for Unused Input and Output Pins. Ordering Information Table - add Lead-Free par t number, marking and note. 16 7/31/02 5/05/03 Added Differential Clock Input Interface section. www.icst.com/products/hiperclocks.html Date 12/10/04 2/28/06 REV. A FEBRUARY 28, 2006