GAL16LV8ZD
Low Voltage, Zero Power E2CMOS PLD
Generic Array Logic™
1
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 1997
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
220
I/CLKII
I
I
I
I
DPP
IGND
Vcc
I/O/Q I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
4
6
8911 13 14
16
18
GAL16LV8ZD
Top View
PLCC
I/CLK
I
I/O/Q
I
I/O/Q
DPP
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
CLK
8
8
8
8
8
8
8
8
OE
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
PROGRAMMABLE
AND-ARRAY
(64 X 32)
I/OE
16lv8zd_03
Features
•3.3V LOW VOLTAGE, ZERO POWER OPERA TION
—JEDEC Compatible 3.3V Interface Standard
—Interfaces with Standard 5V TTL Devices
—50µA Typical Standby Current (100µA Max.)
—45mA Typical Active Current (55mA Max.)
—Dedicated Power-down Pin
•HIGH PERFORMANCE E2CMOS TECHNOLOGY
—TTL Compatible Balanced 8 mA Output Drive
—15 ns Maximum Propagation Delay
—Fmax = 62.5 MHz
—10 ns Maximum from Clock Input to Data Output
—UltraMOS® Advanced CMOS Technology
•E2 CELL TECHNOLOGY
—Reconfigurable Logic
—Reprogrammable Cells
—100% Tested/100% Y ields
—High Speed Electrical Erasure (<100ms)
—20 Year Data Retention
•EIGHT OUTPUT LOGIC MACROCELLS
—Maximum Flexibility for Complex Logic Designs
—Programmable Output Polarity
•PRELOAD AND POWER-ON RESET OF ALL REGISTERS
—100% Functional Testability
•APPLICATIONS INCLUDE:
—Glue Logic for 3.3V Systems
—Ideal for Mixed 3.3V and 5V Systems
•ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL16L V8ZD, at 100 µA standby current and 15ns propagation
delay provides the highest speed low-voltage PLD available in the
market. The GAL16LV8ZD is manufactured using Lattice
Semiconductor's advanced 3.3V E2CMOS process, which com-
bines CMOS with Electrically Erasable (E2) floating gate technology.
The GAL16LV8ZD utilizes a dedicated power-down pin (DPP) to
put the device into standby mode. It has 15 inputs available to the
AND array and is capable of interfacing with both 3.3V and stan-
dard 5V devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration
Specifications GAL16LV8ZD
2
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Isb (µA) Ordering # Package
15 12 10 55 100 GAL16LV8ZD-15QJ 20-Lead PLCC
25 15 15 55 100 GAL16LV8ZD-25QJ 20-Lead PLCC
Blank = Commercial
Grade
Package
Active Power
Q = Quarter Power
XXXXXXXX XX X X X
Device Name
_
J = PLCC
GAL16LV8ZD (Zero Power DPP)
Speed (ns)
GAL16LV8ZD Ordering Information
Commercial Grade Specifications
Part Number Description
Specifications GAL16LV8ZD
3
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in-
put/output configuration. These two global and 16 individual archi-
tecture bits define all possible configurations in a GAL16LV8ZD.
The information given on these architecture bits is only to give a
better understanding of the device. Compiler software will trans-
parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.
Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft-
ware manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 1 1 are permanently configured
as clock and output enable, respectively . These pins cannot be con-
figured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 1 1 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively . Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
When using the standard GAL16V8 JEDEC fuse pattern generated
by the logic compilers for the GAL16L V8ZD, special attention must
be given to pin 4 (DPP) to make sure that it is not used as one of
the functional inputs.
Output Logic Macrocell (OLMC)
Compiler Support for OLMC
Specifications GAL16LV8ZD
4
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK & OE
for registered output configuration.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK & OE
for registered output configuration.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
DQ
Q
CLK
OE
XOR
XOR
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to the
common 16R8 and 16RP4 devices with various permutations of
polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
Pin 4 is used as dedicated power-down pin on GAL16LV8ZD. It
cannot be used as functional input.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
Registered Mode
Specifications GAL16LV8ZD
5
PLCC Package Pinout
MSB LSB
64-USER ELECTRONIC SIGNATURE FUSES
2056, 2057, .... .... 2118, 2119
Byte7 Byte6 .... .... Byte1 Byte0 SYN-2192
AC0-2193
1
2
3
4
5
6
7
8
911
12
13
14
15
16
17
18
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
19
XOR-2048
AC1-2120
XOR-2049
AC1-2121
XOR-2050
AC1-2122
XOR-2051
AC1-2123
XOR-2052
AC1-2124
XOR-2053
AC1-2125
XOR-2054
AC1-2126
XOR-2055
AC1-2127
28
24
201612840
PTD
2128
2191
OE
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
Power
Management
Control
Registered Mode Logic Diagram
Specifications GAL16LV8ZD
6
In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 16L8 and 16P8 devices with programmable polarity in
each macrocell.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 12 & 19) do not have input capability. De-
signs requiring eight I/Os can be implemented in the Registered
mode.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
11 are always available as data inputs into the AND array.
Pin 4 is used as dedicated power-down pin on GAL16LV8ZD. It
cannot be used as functional input.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no ef fect on this mode.
- Pin 13 through Pin 18 are configured to this function.
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no ef fect on this mode.
- Pin 12 and Pin 19 are configured to this
function.
XOR
XOR
Complex Mode
Specifications GAL16LV8ZD
7
PLCC Package Pinout
MSB LSB
64-USER ELECTRONIC SIGNATURE FUSES
2056, 2057, .... .... 2118, 2119
Byte7 Byte6 .... .... Byte1 Byte0 SYN-2192
AC0-2193
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
PTD
2128
2191
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
XOR-2055
AC1-2127
XOR-2054
AC1-2126
XOR-2053
AC1-2125
XOR-2052
AC1-2124
XOR-2051
AC1-2123
XOR-2050
AC1-2122
XOR-2049
AC1-2121
XOR-2048
AC1-2120
OLMC
OLMC
28
24
201612840
Power
Management
Control
Complex Mode Logic Diagram
Specifications GAL16LV8ZD
8
Combinatorial Output with Feedback Configuration
for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
Combinatorial Output Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- Pins 15 & 16 are permanently configured to this
function.
Dedicated Input Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.
Architecture configurations available in this mode are similar to the
common 10L8 and 12P6 devices with many permutations of ge-
neric output polarity or input choices.
All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro-
grammable polarity.
Pins 1 and 11 are always available as data inputs into the AND
array. The center two macrocells (pins 15 & 16) cannot be used
in the input configuration.
Pin 4 is used as dedicated power-down pin on GAL16LV8ZD. It
cannot be used as a functional input.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.
Vcc
XOR
Vcc
XOR
Simple Mode
Specifications GAL16LV8ZD
9
PLCC Package Pinout
MSB LSB
64-USER ELECTRONIC SIGNATURE FUSES
2056, 2057, .... .... 2118, 2119
Byte7 Byte6 .... .... Byte1 Byte0 SYN-2192
AC0-2193
1
11
12
13
14
15
16
17
18
19
2
3
4
5
6
7
9
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
PTD
2128
2191
8
XOR-2048
AC1-2120
OLMC
XOR-2049
AC1-2121
XOR-2050
AC1-2122
XOR-2051
AC1-2123
XOR-2052
AC1-2124
XOR-2053
AC1-2125
XOR-2054
AC1-2126
XOR-2055
AC1-2127
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
28
24
201612840
Power
Management
Control
Simple Mode Logic Diagram
Specifications GAL16LV8ZD
10
Recommended Operating Conditions
Commercial Devices:
Ambient Temperature (TA) .............................0 to +75°C
Supply voltage (VCC)
with Respect to Ground ......................... +3.0 to +3.6V
Absolute Maximum Ratings(1)
Supply voltage VCC .................................... -0.5 to +5.6V
Input voltage applied ................................. -0.5 to +5.6V
Off-state output voltage applied ................ -0.5 to +5.6V
Storage Temperature .................................-65 to 150°C
Ambient Temperature with
Power Applied.........................................-55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
VIL Input Low V oltage Vss – 0.5 — 0.8 V
VIH Input High V oltage 2.0 — 5.25 V
IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -10 µA
IIH Input or I/O High Leakage Current (VCC-0.2)V ≤ VIN ≤ VCC ——10µA
VCC ≤ VIN ≤ 5.25V—— 1mA
VOL Output Low V oltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
IOL = 0.5 mA Vin = VIL or VIH — — 0.2 V
VOH Output High V oltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOH = -0.5 mA Vin = VIL or VIH Vcc-0.45 — — V
IOH = -100 µA Vin = VIL or VIH Vcc-0.2 — — V
IOL Low Level Output Current — — 8 mA
IOH High Level Output Current — — -8 mA
IOS1Output Short Circuit Current VCC = 3.3V VOUT = GND TA = 25°C -30 — -130 mA
SYMBOL PARAMETER CONDITION MIN. TYP.2MAX. UNITS
COMMERCIAL
ISB Stand-by Power VIL = GND VIH = Vcc Outputs Open ZD -15/-25 — 50 100 µA
Supply Current
ICC Operating Power VIL = 0.5V VIH = 3.0V ZD -15/-25 — 45 55 mA
Supply Current ftoggle = 15 MHz Outputs Open
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2) Typical values are at Vcc = 3.3V and TA = 25 °C
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
Specifications GAL16LV8ZD
11
tpd A Input or I/O to Combinatorial Output 3 15 3 25 ns
tco A Clock to Output Delay 2 10 2 15 ns
tcf2— Clock to Feedback Delay — 8 — 10 ns
tsu — Setup T ime, Input or Fdbk before Clk↑12 — 15 — ns
th — Hold T ime, Input or Fdbk after Clk↑0—0—ns
A Maximum Clock Frequency with 45.5 — 33.3 — MHz
External Feedback, 1/(tsu + tco)
fmax3A Maximum Clock Frequency with 50 — 40 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 62.5 — 41.6 — MHz
No Feedback
twh — Clock Pulse Duration, High 8 — 12 — ns
twl — Clock Pulse Duration, Low 8 — 12 — ns
ten B Input or I/O to Output Enabled — 17 — 25 ns
BOE↓ to Output Enabled — 16 — 20 ns
tdis C Input or I/O to Output Disabled — 18 — 25 ns
COE↑ to Output Disabled — 17 — 20 ns
-25
MIN. MAX.
-15
MIN. MAX.
AC Switching Characteristics
Over Recommended Operating Conditions
UNITS
PARAM TEST
COND.1DESCRIPTION
COM
COM
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIInput Capacitance 8 pF VCC = 3.3V, VI = 0V
CI/O I/O Capacitance 8 pF VCC = 3.3V, VI/O = 0V
Capacitance (TA = 25°C, f = 1.0 MHz)
Specifications GAL16LV8ZD
12
t
dhcx
DPP
INPUT or
I/O FEEDBACK
OE
CLK
OUTPUT
t
cvdh
t
gvdh
t
ivdh
t
dhgx
t
dhix
t
pd,
t
en,
t
dis
t
co
t
dliv
t
dlgv
t
dlcv
t
dlov
t
cxdl
t
gxdl
t
ixdl
twhd —DPP Pulse Duration High 40 —40 —ns
twld —DPP Pulse Duration Low 30 —40 —ns
tivdh —Valid Input before DPP High 0 —0—ns
tgvdh —Valid OE before DPP High 0 —0—ns
tcvdh —Valid Clock before DPP High 0 —0—ns
tdhix —Input Don't Care after DPP High —15 —25 ns
tdhgx —OE Don't Care after DPP High —15 —25 ns
tdhcx —Clock Don't Care after DPP High —15 —25 ns
tixdl —Input Don't Care before DPP Low —0—0ns
tgxdl —OE Don't Care before DPP Low —0—0ns
tcxdl —Clock Don't Care before DPP Low —0—0ns
tdliv —DPP Low to Valid Input 20 —25 —ns
tdlgv —DPP Low to Valid OE 20 —25 —ns
tdlcv —DPP Low to Valid Clock 30 —35 —ns
tdlov A DPP Low to Valid Output 5 45 5 45 ns
Dedicated Power-Down Pin Specifications
Over Recommended Operating Conditions
PARAMETER UNITS
-25
MIN. MAX.
TEST
COND1.DESCRIPTION -15
MIN. MAX.
ACTIVE T O STANDBY
STANDBY TO ACTIVE
COM COM
1) Refer to Switching Test Conditions section.
Dedicated Power-Down Pin Timing Waveforms
Specifications GAL16LV8ZD
13
Registered Output
Combinatorial Output
Input or I/O to Output Enable/Disable
Clock Width
OE to Output Enable/Disable
fmax with Feedback
COMBINATIONAL
OUTPUT
VALID INPUT
INPUT or
I/O FEEDBACK
tpd
COMBINATIONAL
OUTPUT
INPUT or
I/O FEEDBACK
ten
tdis
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
(external fdbk)
t
su
t
co
t
h
1/
f
max
CLK
REGISTERED
FEEDBACK
tcf tsu
1/fmax (internal fdbk)
CLK
(
w/o fb
)
1/fmax
twl
twh
OE
REGISTERED
OUTPUT
ten
tdis
Switching Waveforms
Specifications GAL16LV8ZD
14
fmax with Internal Feedback 1/(tsu+tcf)
fmax with External Feedback 1/(tsu+tco)
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh
+ twl). This is to allow for a clock duty cycle of other
than 50%.
Note: fmax with external feedback is calculated from
measured tsu and tco.
Note: tcf is a calculated value, derived by subtracting
tsu from the period of fmax w/internal feedback (tcf
= 1/fmax - tsu). The value of tcf is used primarily
when calculating the delay from clocking a register
to a combinatorial output (through registered feed-
back), as shown above. For example, the timing
from clock to a combinatorial output is equal to tcf
+ tpd.
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+3.3V
*CL
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 2ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
level. 3-state to active transitions are measured at (Voh - 0.5)
V and (Vol + 0.5) V.
Output Load Conditions (see figure)
Test Condition R1R2CL
A 270Ω220Ω35pF
B Active High 270Ω220Ω35pF
Active Low 270Ω220Ω35pF
C Active High 270Ω220Ω5pF
Active Low 270Ω220Ω5pF
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
REGISTER
LOGIC
ARRAY
CLK
tsu + th
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
fmax Descriptions
Switching Test Conditions
Specifications GAL16LV8ZD
15
Electronic Signature
An electronic signature word is provided in every GAL16LV8ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is al-
ways available to the user independent of the state of the security
cell.
NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter checksum.
Security Cell
A security cell is provided in the GAL16LV8ZD devices to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The electronic signature data is always avail-
able regardless of the security cell state.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-ap-
proved Logic Programmer , available from a number of manufac-
turers. Complete programming of the device takes only a few sec-
onds. Erasing of the device is transparent to the user , and is done
automatically as part of the programming cycle.
Output Register Preload
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL16L V8ZD devices includes circuitry that allows each reg-
istered output to be synchronously set either high or low . Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
Input Buffers
GAL16L V8ZD devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
Dedicated Power-Down Pin
The GAL16LV8ZD uses pin 4 as the dedicated power-down sig-
nal to put the device in to the power-down state. DPP is an active
high signal where a logic high driven on this signal puts the device
into power-down state. Input pin 4 cannot be used as a logic func-
tion input on this device.
Specifications GAL16LV8ZD
16
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Vcc (min.)
tpr
Internal Register
Reset to Logic "0"
Dev ic e P in
Reset to Logic "1"
twl
tsu
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the GAL16LV8ZD.
First, the VCC rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in
normal system operation, avoid clocking the device until all input
and feedback path setup times have been met. The clock must
also meet the minimum pulse width requirements.
Circuitry within the GAL16L V8ZD provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 10µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
Typical OutputTypical Input
Vcc
PIN
Tri-State
Control
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Vcc
PIN
Vcc
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Power-Up Reset
Input/Output Equivalent Schematics
Specifications GAL16LV8ZD
17
Normalized Tpd vs Vcc
Supply Voltage (V)
Normalized Tpd
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)
Normalized Tco
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Normalized Tsu
0.8
0.9
1
1.1
1.2
3.00 3.15 3.30 3.45 3.60
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Normalized Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Normalized Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25
0
25
50
75
100
125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Normalized Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25
0
25
50
75
100
125
PT H->L
PT L->H
Delta Tpd vs # of Outputs
Switching
Number of Outputs Switching
Delta Tpd (ns)
-1
-0.75
-0.5
-0.25
0
12345678
RISE
FALL
Delta Tco vs # of Outputs
Switching
Number of Outputs Switching
Delta Tco (ns)
-0.5
-0.4
-0.3
-0.2
-0.1
0
12345678
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
-2
0
2
4
6
8
10
12
0 50 100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Delta Tco (ns)
-4
-2
0
2
4
6
8
10
12
0 50 100 150 200 250 300
RISE
FALL
Typical AC and DC Characteristics
Specifications GAL16LV8ZD
18
Input Clamp (Vik)
Vik (V)
Iik (mA)
0
10
20
30
40
50
60
70
80
90
100
-1.50 -1.20 -0.90 -0.60 -0.30 0.00
Vol vs Iol
Iol (mA)
Vol (V)
0
0.25
0.5
0.75
1
1.25
1.5
0.00 20.00 40.00 60.00 80.00
Voh vs Ioh
Ioh(mA)
Voh (V)
0
0.5
1
1.5
2
2.5
3
0.00 10.00 20.00 30.00 40.00 50.00
Voh vs Ioh
Ioh(mA)
Voh (V)
2.85
2.875
2.9
2.925
2.95
2.975
3
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Normalized Icc
0.70
0.80
0.90
1.00
1.10
1.20
1.30
3.00 3.15 3.30 3.45 3.60
Normalized Icc vs Temp
Temperature (deg. C)
Normalized Icc
0.9
0.95
1
1.05
1.1
1.15
1.2
-55 -25 0 25 50 75 100 125
Normalized Icc vs Freq.
Frequency (MHz)
Normalized Icc
0.75
1.00
1.25
1.50
1.75
2.00
0 25 50 75 100
Delta Icc vs Vin (1 input)
Vin (V)
Delta Icc (mA)
0
1
2
3
4
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
Typical AC and DC Characteristics
