GAL16LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array LogicTM Features Functional Block Diagram * 3.3V LOW VOLTAGE, ZERO POWER OPERATION -- JEDEC Compatible 3.3V Interface Standard -- Interfaces with Standard 5V TTL Devices -- 50A Typical Standby Current (100A Max.) -- 45mA Typical Active Current (55mA Max.) -- Dedicated Power-down Pin I/CLK CLK 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q 8 OLMC I/O/Q I 2 * HIGH PERFORMANCE E CMOS TECHNOLOGY -- TTL Compatible Balanced 8 mA Output Drive -- 15 ns Maximum Propagation Delay -- Fmax = 62.5 MHz -- 10 ns Maximum from Clock Input to Data Output -- UltraMOS(R) Advanced CMOS Technology PROGRAMMABLE AND-ARRAY (64 X 32) I DPP * E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention I I * EIGHT OUTPUT LOGIC MACROCELLS -- Maximum Flexibility for Complex Logic Designs -- Programmable Output Polarity I * PRELOAD AND POWER-ON RESET OF ALL REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- Glue Logic for 3.3V Systems -- Ideal for Mixed 3.3V and 5V Systems I * ELECTRONIC SIGNATURE FOR IDENTIFICATION I Description OE I/OE Pin Configuration The GAL16LV8ZD, at 100 A standby current and 15ns propagation delay provides the highest speed low-voltage PLD available in the market. The GAL16LV8ZD is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. PLCC I DPP The GAL16LV8ZD utilizes a dedicated power-down pin (DPP) to put the device into standby mode. It has 15 inputs available to the AND array and is capable of interfacing with both 3.3V and standard 5V devices. I I/CLK Vcc 2 20 I/O/Q 18 4 I/O/Q I I Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. GAL16LV8ZD Top View 6 16 I/O/Q I/O/Q I I I/O/Q 8 14 9 I GND 11 13 I/OE I/O/Q I/O/Q I/O/Q Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 16lv8zd_03 1 December 1997 Specifications GAL16LV8ZD GAL16LV8ZD Ordering Information Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Isb (A) Ordering # Package 15 12 10 55 100 GAL16LV8ZD-15QJ 20-Lead PLCC 25 15 15 55 100 GAL16LV8ZD-25QJ 20-Lead PLCC Part Number Description XXXXXXXX _ XX Device Name GAL16LV8ZD (Zero Power DPP) X X X Grade Blank = Commercial Package J = PLCC Speed (ns) Active Power Q = Quarter Power 2 Specifications GAL16LV8ZD Output Logic Macrocell (OLMC) each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL16LV8ZD. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of Compiler Support for OLMC Software compilers support the three different global OLMC modes as different device types. Most compilers also have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. For further details, refer to the compiler software manuals. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins ( pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. When using the standard GAL16V8 JEDEC fuse pattern generated by the logic compilers for the GAL16LV8ZD, special attention must be given to pin 4 (DPP) to make sure that it is not used as one of the functional inputs. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. 3 Specifications GAL16LV8ZD Registered Mode In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Registered outputs have eight product terms per output. I/Os have seven product terms per output. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register placement. Pin 4 is used as dedicated power-down pin on GAL16LV8ZD. It cannot be used as functional input. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/ O. Up to eight registers or up to eight I/Os are possible in this mode. Dedicated input or output functions can be implemented as subsets of the I/O function. CLK Registered Configuration for Registered Mode D XOR - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1 controls common CLK for the registered outputs. - Pin 11 controls common OE for the registered outputs. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. Q Q OE Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 1 & Pin 11 are permanently configured as CLK & OE for registered output configuration. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 4 Specifications GAL16LV8ZD Registered Mode Logic Diagram PLCC Package Pinout 1 0 4 8 12 16 20 24 28 2128 PTD 0000 OLMC 0224 19 XOR-2048 AC1-2120 2 0256 OLMC 0480 18 XOR-2049 AC1-2121 3 0512 OLMC 0736 XOR-2050 AC1-2122 Power Management Control 4 17 0768 OLMC 0992 16 XOR-2051 AC1-2123 5 1024 OLMC 1248 15 XOR-2052 AC1-2124 6 1280 OLMC 1504 14 XOR-2053 AC1-2125 7 1536 OLMC 1760 13 XOR-2054 AC1-2126 8 1792 OLMC 2016 XOR-2055 AC1-2127 9 2191 64-USER ELECTRONIC SIGNATURE FUSES 2056, 2057, .... .... 2118, 2119 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB 5 SYN-2192 AC0-2193 12 OE 11 Specifications GAL16LV8ZD Complex Mode In the Complex mode, macrocells are configured as output only or I/O functions. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1 and 11 are always available as data inputs into the AND array. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell. Pin 4 is used as dedicated power-down pin on GAL16LV8ZD. It cannot be used as functional input. Up to six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 12 & 19) do not have input capability. Designs requiring eight I/Os can be implemented in the Registered mode. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1 has no effect on this mode. - Pin 13 through Pin 18 are configured to this function. XOR Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1 has no effect on this mode. - Pin 12 and Pin 19 are configured to this function. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 6 Specifications GAL16LV8ZD Complex Mode Logic Diagram PLCC Package Pinout 1 2128 0 4 8 12 16 20 24 28 PTD 0000 OLMC 19 XOR-2048 AC1-2120 0224 2 0256 OLMC 18 XOR-2049 AC1-2121 0480 3 0512 OLMC 4 17 XOR-2050 AC1-2122 0736 Power Management Control 0768 OLMC 16 XOR-2051 AC1-2123 0992 5 1024 OLMC 15 XOR-2052 AC1-2124 1248 6 1280 OLMC 14 XOR-2053 AC1-2125 1504 7 1536 OLMC 13 XOR-2054 AC1-2126 1760 8 1792 OLMC 12 XOR-2055 AC1-2127 2016 9 11 2191 64-USER ELECTRONIC SIGNATURE FUSES 2056, 2057, .... .... 2118, 2119 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB 7 SYN-2192 AC0-2193 Specifications GAL16LV8ZD Simple Mode In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Pins 1 and 11 are always available as data inputs into the AND array. The center two macrocells (pins 15 & 16) cannot be used in the input configuration. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of generic output polarity or input choices. Pin 4 is used as dedicated power-down pin on GAL16LV8ZD. It cannot be used as a functional input. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has programmable polarity. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. Combinatorial Output with Feedback Configuration for Simple Mode Vcc - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. XOR Combinatorial Output Configuration for Simple Mode Vcc - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 15 & 16 are permanently configured to this function. XOR Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 8 Specifications GAL16LV8ZD Simple Mode Logic Diagram PLCC Package Pinout 1 2128 0 4 8 12 16 20 24 28 PTD 0000 OLMC 19 XOR-2048 AC1-2120 0224 2 0256 OLMC 18 XOR-2049 AC1-2121 0480 3 0512 OLMC 4 17 XOR-2050 AC1-2122 0736 Power Management Control 0768 OLMC 16 XOR-2051 AC1-2123 0992 5 1024 OLMC 15 XOR-2052 AC1-2124 1248 6 1280 OLMC 14 XOR-2053 AC1-2125 1504 7 1536 OLMC 13 XOR-2054 AC1-2126 1760 8 1792 OLMC 12 XOR-2055 AC1-2127 2016 9 11 2191 64-USER ELECTRONIC SIGNATURE FUSES 2056, 2057, .... .... 2118, 2119 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB 9 SYN-2192 AC0-2193 Specifications GAL16LV8ZD Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC .................................... -0.5 to +5.6V Input voltage applied ................................. -0.5 to +5.6V Off-state output voltage applied ................ -0.5 to +5.6V Storage Temperature ................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V 1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IOS1 MIN. TYP.2 MAX. UNITS Input Low Voltage Vss - 0.5 -- 0.8 V Input High Voltage 2.0 -- 5.25 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V VIN VIL (MAX.) -- -- -10 A Input or I/O High Leakage Current (VCC-0.2)V VIN VCC -- -- 10 A VCC VIN 5.25V -- -- 1 mA IOL = MAX. Vin = VIL or VIH -- -- 0.5 V IOL = 0.5 mA Vin = VIL or VIH -- -- 0.2 V IOH = MAX. Vin = VIL or VIH 2.4 -- -- V IOH = -0.5 mA Vin = VIL or VIH Vcc-0.45 -- -- V IOH = -100 A Vin = VIL or VIH Vcc-0.2 -- -- V Low Level Output Current -- -- 8 mA High Level Output Current -- -- -8 mA -30 -- -130 mA Output Low Voltage Output High Voltage Output Short Circuit Current COMMERCIAL ISB Stand-by Power VCC = 3.3V VOUT = GND TA = 25C VIL = GND VIH = Vcc Outputs Open ZD -15/-25 -- 50 100 A VIL = 0.5V VIH = 3.0V ftoggle = 15 MHz Outputs Open ZD -15/-25 -- 45 55 mA Supply Current ICC Operating Power Supply Current 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and TA = 25 C 10 Specifications GAL16LV8ZD AC Switching Characteristics Over Recommended Operating Conditions PARAM TEST COND.1 tpd tco tcf2 tsu th fmax3 twh twl ten tdis COM COM -15 -25 DESCRIPTION MIN. MAX. MIN. MAX. UNITS A Input or I/O to Combinatorial Output 3 15 3 25 ns A Clock to Output Delay 2 10 2 15 ns -- Clock to Feedback Delay -- 8 -- 10 ns -- Setup Time, Input or Fdbk before Clk 12 -- 15 -- ns -- Hold Time, Input or Fdbk after Clk 0 -- 0 -- ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 45.5 -- 33.3 -- MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 50 -- 40 -- MHz A Maximum Clock Frequency with No Feedback 62.5 -- 41.6 -- MHz -- Clock Pulse Duration, High 8 -- 12 -- ns -- Clock Pulse Duration, Low 8 -- 12 -- ns B Input or I/O to Output Enabled -- 17 -- 25 ns B OE to Output Enabled -- 16 -- 20 ns C Input or I/O to Output Disabled -- 18 -- 25 ns C OE to Output Disabled -- 17 -- 20 ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. Capacitance (TA = 25C, f = 1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 3.3V, VI = 0V CI/O I/O Capacitance 8 pF VCC = 3.3V, VI/O = 0V 11 Specifications GAL16LV8ZD Dedicated Power-Down Pin Specifications Over Recommended Operating Conditions PARAMETER twhd twld TEST COND1. COM COM -15 -25 MIN. MAX. MIN. MAX. DESCRIPTION UNITS -- DPP Pulse Duration High 40 -- 40 -- ns -- DPP Pulse Duration Low 30 -- 40 -- ns ACTIVE TO STANDBY tivdh tgvdh tcvdh -- Valid Input before DPP High 0 -- 0 -- ns -- Valid OE before DPP High 0 -- 0 -- ns -- Valid Clock before DPP High 0 -- 0 -- ns tdhix tdhgx tdhcx -- Input Don't Care after DPP High -- 15 -- 25 ns -- OE Don't Care after DPP High -- 15 -- 25 ns -- Clock Don't Care after DPP High -- 15 -- 25 ns -- Input Don't Care before DPP Low -- 0 -- 0 ns -- OE Don't Care before DPP Low -- 0 -- 0 ns -- Clock Don't Care before DPP Low -- 0 -- 0 ns -- DPP Low to Valid Input 20 -- 25 -- ns -- DPP Low to Valid OE 20 -- 25 -- ns -- DPP Low to Valid Clock 30 -- 35 -- ns A DPP Low to Valid Output 5 45 5 45 ns STANDBY TO ACTIVE tixdl tgxdl tcxdl tdliv tdlgv tdlcv tdlov 1) Refer to Switching Test Conditions section. Dedicated Power-Down Pin Timing Waveforms DPP t ivdh t dhix t ixdl t dliv t gvdh t dhgx t gxdl t dlgv INPUT or I/O FEEDBACK OE t cvdh t dhcx t cxdl t dlcv CLK tc o t p d ,t e n ,t di s OUTPUT 12 t dlov Specifications GAL16LV8ZD Switching Waveforms INPUT or I/O FEEDBACK INPUT or I/O FEEDBACK VALID INPUT VALID INPUT tsu tpd th CLK COMBINATIONAL OUTPUT tco REGISTERED OUTPUT 1/fmax (external fdbk) Combinatorial Output INPUT or I/O FEEDBACK Registered Output tdis ten COMBINATIONAL OUTPUT OE tdis Input or I/O to Output Enable/Disable ten REGISTERED OUTPUT OE to Output Enable/Disable twh twl CLK CLK 1/ fmax (w/o fb) 1/ fmax (internal fdbk) tcf REGISTERED FEEDBACK Clock Width fmax with Feedback 13 tsu Specifications GAL16LV8ZD fmax Descriptions CLK LOGIC ARRAY REGISTER CLK tsu LOGIC ARRAY tco REGISTER fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. t cf t pd CLK fmax with Internal Feedback 1/(tsu+tcf) LOGIC ARRAY Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. REGISTER tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Switching Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels +3.3V GND to 3.0V 2ns 10% - 90% 1.5V 1.5V Output Load R1 See Figure 3-state levels are measured 0.5V from steady-state active level. 3-state to active transitions are measured at (Voh - 0.5) V and (Vol + 0.5) V. FROM OUTPUT (O/Q) UNDER TEST Output Load Conditions (see figure) Test Condition B C R2 R1 R2 CL 270 220 35pF Active High 270 220 35pF Active Low 270 220 35pF Active High 270 220 5pF Active Low 270 220 5pF A TEST POINT C L* *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 14 Specifications GAL16LV8ZD Electronic Signature An electronic signature word is provided in every GAL16LV8ZD device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter checksum. Security Cell A security cell is provided in the GAL16LV8ZD devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The electronic signature data is always available regardless of the security cell state. Device Programming GAL devices are programmed using a Lattice Semiconductor-approved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL16LV8ZD devices includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. Input Buffers GAL16LV8ZD devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. Dedicated Power-Down Pin The GAL16LV8ZD uses pin 4 as the dedicated power-down signal to put the device in to the power-down state. DPP is an active high signal where a logic high driven on this signal puts the device into power-down state. Input pin 4 cannot be used as a logic function input on this device. 15 Specifications GAL16LV8ZD Power-Up Reset Vcc Vcc (min.) t su t wl CLK t pr INTERNAL REGISTER Q - OUTPUT Internal Register Reset to Logic "0" FEEDBACK/EXTERNAL OUTPUT REGISTER Device Pin Reset to Logic "1" Circuitry within the GAL16LV8ZD provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 10s MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL16LV8ZD. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Input/Output Equivalent Schematics PIN PIN Feedback Vcc Vcc Tri-State Control Vcc Vcc ESD Protection Circuit Data Output PIN ESD Protection Circuit PIN Feedback (To Input Buffer) Typical Input Typical Output 16 Specifications GAL16LV8ZD Typical AC and DC Characteristics Normalized Tpd vs Vcc 1.2 1.2 PT L->H 1 0.9 0.8 3.00 3.15 3.30 3.45 1.1 FALL 1 0.9 0.8 3.00 3.60 3.15 3.30 3.45 PT L->H 1 0.9 0.8 3.00 3.60 3.15 3.30 3.45 3.60 Supply Voltage (V) Supply Voltage (V) Supply Voltage (V) Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp 1.3 1 0.9 0.8 Delta Tpd vs # of Outputs Switching PT L->H 1.1 1 0.9 0.8 Temperature (deg. C) Delta Tco (ns) 0 -0.25 -0.5 RISE -0.75 FALL -1 -0.1 -0.2 -0.3 RISE -0.4 FALL -0.5 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 12 12 10 8 Delta Tco (ns) RISE 10 FALL 6 4 2 0 RISE 8 FALL 6 4 2 0 -2 -4 -2 0 50 100 150 200 250 0 300 50 100 150 200 250 Output Loading (pF) Output Loading (pF) 17 100 -55 125 0.7 Delta Tco vs # of Outputs Switching 0 Delta Tpd (ns) PT H->L 1.2 Temperature (deg. C) Temperature (deg. C) Delta Tpd (ns) 100 75 50 25 -25 -55 125 100 75 50 25 0 -25 0 0.7 0.7 1.3 75 0.8 FALL 50 1 0.9 1.1 25 PT L->H RISE 0 1.1 1.4 1.2 -25 PT H->L Normalized Tsu 1.2 Normalized Tco 1.3 -55 PT H->L 1.1 300 125 1.1 RISE Normalized Tsu PT H->L Normalized Tco Normalized Tpd 1.2 Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc Specifications GAL16LV8ZD Typical AC and DC Characteristics Voh vs Ioh 3 3 2.5 2.975 1 2 2.95 0.75 0.5 1.5 1 0.25 0.5 0 0 20.00 40.00 60.00 Voh (V) 1.5 0.00 10.00 20.00 30.00 40.00 50.00 1.10 1.00 0.90 0.80 1.1 1.05 1 0.95 3.60 Supply Voltage (V) -25 0 25 50 75 100 125 Temperature (deg. C) Delta Icc vs Vin (1 input) 0 20 30 Iik (mA) Delta Icc (mA) 10 2 40 50 60 70 1 80 90 0 0.00 0.50 1.00 1.50 2.00 Vin (V) 2.50 3.00 3.50 1.75 1.50 1.25 1.00 100 -1.50 -1.20 -0.90 -0.60 Vik (V) 18 -0.30 0 25 50 75 Frequency (MHz) Input Clamp (Vik) 3 4.00 0.75 -55 4 3.00 2.00 0.9 3.45 2.00 Normalized Icc vs Freq. Normalized Icc 1.15 Normalized Icc 1.2 1.20 3.30 1.00 Ioh(mA) Normalized Icc vs Temp 1.30 3.15 0.00 Ioh(mA) Normalized Icc vs Vcc 0.70 3.00 2.9 2.85 0.00 80.00 2.925 2.875 Iol (mA) Normalized Icc Voh vs Ioh 1.25 Voh (V) Vol (V) Vol vs Iol 0.00 100