Freescale Semiconductor Technical Data MC33397 Rev. 3.0, 12/2006 Dual / Hex Low-Side Switch with Both SPI and Parallel Input Control 33397 The 33397 is a low-side switch that is user configurable to be either two 333 m outputs (dual mode) or six 900 m outputs (hex mode). Each output is internally current limited and short-circuit protected. Output fault detection capability includes "off state" open loads and "on state" short-to-battery conditions. Faults for each output are latched into the fault register and serially shifted out during serial communication. DUAL / HEX LOW-SIDE SWITCH Features * User Configurable to be Either Two 333 m Outputs (Dual Mode) or Six 900 m Outputs (Hex Mode) * Output Inductive Energy Clamps * Parallel Input (3.3 V and 5.0 V Compatible) or Serial Peripheral Interface (SPI) Control * 8-Bit SPI Control and Fault Diagnostics * Short-to-Battery Detection and Shutdown with Automatic Retry * OFF-State Open-Circuit Detection * Programmable Overvoltage Shutdown (VPWR Pin) * Undervoltage Shutdown (VDD Pin) * Sleep Mode -- IDD 25 A (1.0 A Typical) DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42344B 24-PIN SOICW ORDERING INFORMATION Device A0 23 Microcontroller with Bus A1 14 33397 CMOS Input Logic CMOS Serial Shift Registers and Latches Output Switches and Sense Circuits A2 12 A3 11 A4 2 SO 9 A5 1 GND 5-8, 17-20 Figure 1. 33397 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2007. All rights reserved. Package - 40 to 125C 24 SOICW MC33397DW/R2 MCZ33397EG/R2 EN 15 CS 10 SCLK 3 SI 4 Temperature Range (TA) INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM CS SI A0 8-Bit SPI Interface 3.0 V + Sleep Mode 40 A 50 1.2 + 3.0 V - Logic Dual Mode Dual Mode 1.2 A2 + 3.0 V Sleep Mode 40 A 50 V 1.2 Logic Logic Dual Mode Dual Mode 3.0 V + Sleep Mode 1.2 A3 + 3.0 V Sleep Mode 40 A 40 A 50 V 50 V ILIMIT ILIMIT A5 Sleep 40 1.2 Logic 3.0 + Sleep Mode 40 A 50 V A1 ILIMIT ILIMIT A4 SO SCLK Logic 50 V 1.2 Logic ILIMIT ILIMIT 10 A 10 s Filter P2 10 A P1 Parallel Gate Control and Mode Control Logic P0 + 0.75 VDD 0.25 VDD + - S Q R VPWR 10 A 30 V Overvoltage Shutdown Low VDD Detect + - 3.0 V VDD VDD EN Figure 2. 33397 Simplified Internal Block Diagram 33397 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS A5 1 24 VPWR A4 2 23 A0 SCLK 3 22 P2 SI 4 21 P1 GND 5 20 GND GND 6 19 GND GND 7 18 GND GND 8 17 GND SO 9 16 P0 CS 10 15 EN A3 11 14 A1 A2 12 13 VDD Figure 3. 33397 Pin Connections Table 1. 33397 Pin Definitions Pin Number Pin Name Definition 1, 2, 11, 12, 14, 23 A0 - A5 Power outputs 3 SCLK SPI clock input 4 SI SPI serial input 5 - 8, 17 - 20 GND 9 SO SPI serial output 10 CS SPI chip select 13 VDD Supply input pin 15 EN Enable 16 P0 In hex mode, P0 controls output A0. In dual mode, P0 controls outputs A0, A4, and A5 simultaneously 21 P1 In hex mode, P1 controls output A1. In dual mode, P2 controls outputs A1, A2, and A3 simultaneously 22 P2 In hex mode, P2 controls output A2. P2 is also the mode control pin. If 0.25*VDD<P2<0.75*VDD for more than 10 s, the 33397 will change to dual mode 24 VPWR Power and signal ground Overvoltage threshold shutdown monitoring pin (not a power supply pin for the IC) 33397 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Ratings Symbol Value Unit Power Supply Voltage VPWR 50 V Logic Supply Voltage VDD -0.3 to 7.0 V Input Pin Voltage VIN -0.3 to VDD+0.3 V Human Body Model VESD1 2000 Machine Model VESD2 200 ESD Voltage (1) V Single Pulse Output Clamp Energy mJ IO = 500 mA, TJ = 150C (Hex Mode) JCLAMP1 50 IO = 1.5 A, TJ = 150C (Dual Mode) JCLAMP1 100 fOP 3.5 MHz TSTG -55 to 150 C TJ -40 to 150 C TPPRT Note 3 C RJ-L 15 C/W Recommended SPI Operating Frequency Storage Temperature Operating Junction Temperature Peak Package Reflow Temperature During Reflow Thermal Resistance, Junction-to-Lead (4) (2) (3) , Notes 1. ESD1 performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 2. 3. 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Leads 5, 6, 7, 8, 17, 18, 19, and 20 are soldered to a heat-sinking ground plane. See Figure 14. 33397 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS) STATIC ELECTRICAL CHARACTERISTICS) Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.75 V VDD 5.25 V, -40C TA 125C, unless otherwise noted Characteristic Symbol Min Typ Max Unit IPWR(ON) - 1.0 50 A IPWR(SS) - 1.0 10 VP(OV) 30 33 38 V VP(OV)Hys 0.3 0.5 1.5 V IDD - 1.20 5.0 mA IDDSS - 1.0 25 A VDD(LVI) 2.5 3.0 3.5 V High VIH 0.8 - - Low VIL - - 0.2 Upper Threshold VDMH 0.7 0.75 0.8 Lower Threshold VDML 0.2 0.25 0.3 Pull-Down (P0, P1) - VIN = VDD IINPD 10 20 30 Pull-Down (P2) - VIN = VDD IINPD 5.0 10 30 Pull-Up (CS) - VIN = 0 V IINPU -20 -10 -5.0 IINPU -100 - -10 IINPU -10 0 10 IO = 0.35 A, TJ = -40C 0.39 0.5 1.2 IO = 0.35 A, TJ = 25C 0.51 0.7 1.2 IO = 0.35 A, TJ = 150C 0.51 1.0 1.2 IDS = 20 mA, Output Off 50 55 60 IDS = 200 mA, Output Off 50 56 60 0.0 - 10 POWER INPUT VPWR Supply Current (All Outputs ON) A VPWR Sleep State Supply Current VPWR = 17 V, SPI Bit 7 = 1, EN = 5.0 V Overvoltage Shutdown Overvoltage Shutdown Hysteresis Logic Supply Current (All Outputs ON) Logic Supply Current (Sleep State: EN = 5.0 V, SPI Bit 7 = 1) Logic Supply Undervoltage Inhibit Threshold INPUT Input Voltage (P0, P1, P2, EN, SI, SCLK, CS) VDD Dual Mode Threshold (P2) VDD A Input Current Pull-Up (EN) - VIN = 0 V Pull-Up (SCLK, SI) - VIN = 2.5 V OUTPUT Output Drain to Source ON Resistance (Hex Mode) (6) Output Voltage Clamp Output Leakage Current (Hex Mode) RDS(ON) BVDSS V A IO(SS) EN = H, bit 7 = 1, VDRAIN = 24 V Output Logic Voltage (SO), ILOAD = 1.0 mA VDD High VOH 0.8 - - Low VOL - - 0.2 ISOT -10 - 10 Output Tristate Leakage (SO), VSO = 2.5 V A Notes 5. This parameter is specified for hex mode. In dual mode, the parameter will be three times smaller. 33397 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS) Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V VDD 5.25 V, -40C TA 125C, unless otherwise noted Characteristic Symbol Min Typ Max 1.0 1.5 2.0 Unit FAULT DETECTION Output Self-Limiting Current (Hex Mode) (6) IO(LIM) Outputs Programmed ON Output Fault Detect Threshold Voltage VOF(TH) Outputs Programmed OFF, EN = 0 Output OFF Open Load Detect Current Output Programmed OFF, EN = 0 A VDD 0.5 0.6 0.7 20 40 80 A IO(OFF) Notes 6. This parameter is specified for hex mode. In dual mode, the parameter will be three times smaller. 33397 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.75 V VDD 5.25 V, -40C TA 125C, unless otherwise noted. Characteristic Symbol Min Typ Max 1.0 1.2 10 Unit OUTPUT TIMING Output Rise Time Output Fall Time s tR VPWR = 14 V, RLOAD = 25 , 20 - 80% s tF VPWR = 14 V, RLOAD = 25 , 80 - 20% 1.0 2.0 10 Output Turn-On Propagation Delay tPON 1.0 4.0 10 s Output Turn-Off Propagation Delay tPOFF 1.0 4.0 10 s Output Short-to-Battery Fault Filter Time tSS 30 50 90 s Output Refresh Timer tREF 3.0 4.1 6.0 ms D 0.2 1.56 3.0 % tOOF 30 50 90 s - 80 110 FAULT TIMING Output Refresh Timer Duty Cycle Output Off-State Open Circuit Fault Filter Time SPI/MISCELLANEOUS TIMING SO Disable Time (10 K Pull-Up Resistor on SO) tSODIS CS = 0.8 V to SO > 0.8*VDD SO Enable Time (10 K Pull-Up Resistor on SO) ns tSOEN CS = 0.8 V to SO Low Impedance ns - 80 110 - 30 50 - 30 50 - 65 80 - 100 140 tSU - 25 45 ns POR/EN Wake-Up Timer tPOR 20 40 60 s Mode Change Timer (P2) tMODE 5.0 10 25 s SO Rise Time tSORISE CL < 200 pF SO Fall Time tSOFALL CL < 200 pF SO Valid Time Required Time Between SI to Rising Edge of SCLK ns tVALID Falling Edge of SCLK to SO Valid Required Time Between Falling Edge of CS to Rising Edge of SCLK ns ns tLEAD ns 33397 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS CS tLEAD tLAG SCLK SI tSU SO tSOEN tSODIS tVALID Figure 4. SPI Timing Diagram CS SCLK SI HIZ SO PO P1 P2 EN A0 tPON A1 A2 tFALL tRISE tPOFF A3-A5 Note: In hex mode, the outputs are controlled by the SPI or by the parallel inputs. However, P0, P1, and P2 only control A0, A1, and A2, respectively. When EN goes high, the part is disabled. Figure 5. Operation Waveforms for Hex Control 33397 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS . VDD 0.8 VDD P0, P1 0.2 VDD tPON 0V tR tF tPOFF 80% VDS 20% 0V Figure 6. Response Times Short-to-Battery Period VDD VIN (P0, P1) VDS ILIMIT ILOAD ILOAD tREF tREF tSS Figure 7. Short-to-Battery Fault 33397 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS VDDLV1 VDD tPOR Power On Reset (Internal Signal) 2.5 V P2 tMODE tMODE Hex Mode A2 Dual Mode Figure 8. Power-On Reset and Mode Select TYPICAL SWITCHING WAVEFORMS 1.2 58 57.8 DRAIN TO CLAMP (V) 1 RDS(ON) () 0.8 0.6 0.4 0.2 57.6 57.4 57.2 57 56.8 56.6 56.4 0 -50 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (DEG C) Figure 9. Output on Resistance vs. Temperature 150 56.2 -50 -25 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (DEG C) Figure 10. Drain to Source Clamp vs. Temperature 33397 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS 1.4 1.74 1.72 1.3 5V SUPPLY CURRENT (A) CURRENT (A) 1.7 1.68 1.66 1.64 1.62 1.6 1.58 -50 -25 0 25 50 75 100 125 1.2 1.1 1 0.9 0.8 -50 150 -25 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (DEG C) TA, AMBIENT TEMPERATURE (DEG C) Figure 13. IDD vs. Temperature Figure 11. Current Limit vs. Temperature 3 0.2 0.18 2.5 CURRENT (A) 0.16 CURRENT (A) 0 0.14 0.12 0.1 0.08 2 1.5 1 0.06 0.04 0.5 0.02 -50 -25 0 25 50 75 100 125 0 -50 150 -25 TA, AMBIENT TEMPERATURE (DEG C) 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (DEG C) Figure 14. IDD Sleep State vs. Temperature Figure 12. IVPWR vs. Temperature SPI Output Word Definition SPI Input Word Definition MSB 7 0 MSB 6 5 4 3 2 1 0 7 <-DIN 6 5 A4 Enable Enable Sleep Mode 3 2 1 0 <-DIN A0 Fault A1 Fault A0 Enable A1 Enable A2 Enable A3 Enable A5 Enable Not Used (Don't Care) 4 <DOUT A2 Fault A3 Fault A4 Fault A5 Fault Zero Sleep Mode Feedback (1=Sleep Mode Enabled) The device will power up with sleep mode enabled. In dual mode, input bits 0, 4, and 5 must all be high to turn on combinational output A0, A4, and A5 via the SPI. In dual mode, input bits 1, 2, and 3 must all be high to turn on combinational output A1, A2, and A3 via the SPI. Figure 15. SPI Input/Output Word Definition 33397 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS Table 5. Truth Table Inputs EN P0 P1 P2 0 0 0 0 0 0 1 0 1 0 SPI Bit 7 Outputs Comments A0 A1 A2 A3 A4 A5 X OFF OFF OFF * * * 0 X OFF OFF ON * * * 0 0 X OFF ON OFF * * * 1 1 0 X OFF ON ON * * * 1 0 0 0 X ON OFF OFF * * * 1 0 1 0 X ON OFF ON * * * 1 1 0 0 X ON ON OFF * * * 1 1 1 0 X ON ON ON * * * 0 0 0 1 0 OFF OFF OFF OFF OFF OFF 0 0 1 1 0 OFF OFF ON OFF OFF OFF 0 1 0 1 0 OFF ON OFF OFF OFF OFF 0 1 1 1 0 OFF ON ON OFF OFF OFF Outputs A0, A1, and A2 are only controlled via inputs P0, P1, and P2. 1 0 0 1 0 ON OFF OFF OFF OFF OFF Sleep mode disabled. 1 0 1 1 0 ON OFF ON OFF OFF OFF 1 1 0 1 0 ON ON OFF OFF OFF OFF 1 1 1 1 0 ON ON ON OFF OFF OFF 0 0 2.5 V 0 X OFF OFF OFF OFF OFF OFF 0 1 2.5 V 0 X OFF ON ON ON OFF OFF 1 0 2.5 V 0 X ON OFF OFF OFF ON ON 1 1 2.5 V 0 X ON ON ON ON ON ON 0 0 2.5 V 1 0 OFF OFF OFF OFF OFF OFF DUAL MODE 0 1 2.5 V 1 0 OFF ON ON ON OFF OFF Outputs are not controlled via SPI. Outputs are controlled via inputs P0 and P1. Sleep mode disabled. 1 0 2.5 V 1 0 ON OFF OFF OFF ON ON 1 1 2.5 V 1 0 ON ON ON ON ON ON X X X 1 1 OFF OFF OFF OFF OFF OFF HEX MODE * = Outputs A3, A4, and A5 are SPI controlled only. X = Don't care. Outputs A0, A1, and A2 are controlled either via SPI or inputs P0, P1, and P2. HEX MODE Outputs A3, A4, and A5 are always OFF. Outputs are not controlled via SPI. DUAL MODE Outputs are also controlled via SPI. SPI fully functional. All outputs disabled. SPI is reset and ignored. No fault detection. 33397 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS 65 C/W 60 PCB Heat Sink Flag 1 55 PCB Heat Sink Flag 2 50 45 0 1 2 3 4 5 6 7 8 Total Square Inches of Heat Sink Flag Area (Flag 1 + Flag 2) 9 10 Figure 16. Approximate Thermal Resistance Using PCB Heat Sinking 33397 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33397 is a versatile dual-mode low-side switch that can be output-configured as two 333 m open drain outputs in the dual mode or as six 900 m open drain outputs in the hex mode (RDS(ON) @ 25C). Each open drain output has internal current limit and shortcircuit protection. Current limit is typically 1.5 A, with 2.0 A maximum. The outputs can be input controlled via parallel inputs or the SPI. Three inputs provide parallel control, while a serial 8-bit word provides SPI control of the outputs. Output fault detection capability includes OFF-state open loads and ON-state short-to-battery conditions. Individual output faults are latched into the fault register and serially shifted out during serial communication to the 33397. The 33397 has both overvoltage and undervoltage shutdown. A low quiescent current sleep slate feature can be enabled or disabled on command via the SPI port. FUNCTIONAL PIN DESCRIPTION VDD Logic power supply pin. A0 - A5 A0 - A5 are the drains of the 1.2 (max.) MOSFETs. They each have an internal voltage clamp of 50 V (min.) to clamp inductive loads during turn-off. When enabled, they are each internally current limited to a maximum of 2.0 A. If any output is in current limit (output voltage >3.0 V) for a time greater than tSS, the output will be disabled for a time tREF and then try to turn on again. When disabled, open circuits are detected if the output is less than 3.0 V for a time of tSS. Either type of fault is reported as a fault on the SPI output word. If EN input is high and SPI bit 7 =1, the pull-down current sources on the outputs are disabled to minimize VDD supply current. In hex mode, all six outputs are independent. Outputs A0, A1, and A2 are controlled by either the SPI input word bits 0, 1, and 2, respectively, or parallel inputs P0, P1, and P2. Outputs A3, A4, and A5 are controlled only by SPI input word bits 3, 4, and 5, respectively. In dual mode, outputs A0, A4, and A5 are all controlled simultaneously by input P0 or by SPI bits 0, 4, and 5. All three bits must be high to enable this output via the SPI. Outputs A1, A2, and A3 are all controlled simultaneously by input P1 or by SPI bits 1, 2, and 3. All three bits must be high to enable this output via the SPI. P0 - P2 In hex mode, P0 is the parallel input to control output A0. It is OR'd with SPI bit 0 to enable output A0. Either one will enable output A0. In dual mode, P0 controls outputs A0, A4, and A5 simultaneously. P0 has a pull down current of 10 A. It is ignored when EN is high and bit 7 = 1. In hex mode, P1 is the parallel input to control output A1. It is OR'd with SPI bit 1 to enable output A1. Either one will enable output A1. In dual mode, P1 controls outputs A1, A2, and A3 simultaneously. P1 has a pull-down current of 10 A. It is ignored when EN is high and bit 7 = 1. In hex mode, P2 is the parallel input to control output A2. It is OR'd with SPI bit 2 to enable output A2. Either one will enable output A2. P2 also is used to program the 33397 to either a dual or hex output device. The 33397 will be the hex mode if P2 is biased above 0.75*VDD (typical) or below 0.25*VDD (typical). Normal 5.0 V control logic on this parallel input will maintain the 33397 in hex mode and allow control of output A2. If 0.25*VDD <P2 <0.75*VDD for more than 10 s, the 33397 will switch to dual mode. P2 has a pull-down current of 10 A. It is ignored when EN is high and bit 7 = 1. VPWR VPWR is used to sense an overvoltage condition on the supply pin. When the voltage on VPWR exceeds VOV, all outputs are disabled for the duration of the overvoltage condition. If VPWR is grounded, overvoltage shutdown is disabled. VPWR threshold can be modified with an external resistor divider if higher thresholds are desired. SCLK SCLK is the clock for the serial interface. SI SI is the serial input for the SPI port. When CS is low, SI is read on the positive edge of SCLK and SO is updated on the falling edge. When CS is high, SI is ignored. SI has a pulldown current source to pull it low in the event of an open circuit. SO SO is the serial output of the SPI port. When CS goes low, SO outputs bit 7 of the output word. On each falling edge of SCLK, SO will shift the next SPI output bit until on the eighth SCLK falling edge the bit present on SI during the first rising edge will appear. In this way devices can be daisy-chained to operate on a common CS. When CS is high, SO is high impedance. 33397 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CS CS is the chip select to enable the SPI interface. When CS is high, no SPI communication is possible. When CS goes low, SI will be read on each rising SCLK edge and SO will shift on each SCLK falling edge. When CS goes high, the bits present in the SPI input register will be interpreted as the SPI input command. Also when CS goes high, all faults that were latched into the SPI output register are cleared. If faults are still present on outputs, they will be re-latched after tSS. EN mode or when the IC is powered up from VDD, a power-up timer of 40 s is started to allow the 33397 to determine which mode it is in (hex or dual). During this time all parallel inputs and serial control SPI bits will be ignored and all outputs will remain off. If EN transitions low when not in the sleep mode, this "dead" time will not occur. If a one was written to bit 7, the 33397 will be in the sleep mode when EN goes high. In this mode all SPI registers are reset to zero and all faults are cleared. No fault detection is possible. The standby supply current on VDD and VPWR is minimized. EN must be low for complete IC functionality in either the dual or hex mode. When EN transitions low while in the sleep 33397 Analog Integrated Circuit Device Data Freescale Semiconductor 15 TYPICAL APPLICATION INTRODUCTION TYPICAL APPLICATION INTRODUCTION A voltage on the P2 input pin determines the mode. All six outputs can operate either independently (hex mode) (Figure 15) or in paralleled groups of three (dual mode) (Figure 16). In the dual mode, outputs A0, A1, and A2 are controlled by parallel inputs P0, P1, and P2, respectively, and they are also controlled by the SPI port with which they are OR'd. On the other hand, outputs A3, A4, and A5 are controlled only through the SPI port. When the voltage on P2 is between 0.25 VDD and 0.75 VDD (i.e., when P2 is held at an intermediate voltage, neither high nor low), the 33397 operates in the dual mode. However, the P2 pin must stay at that level for a minimum specified time. In this mode, outputs A0, A4, and A5 are all controlled in parallel by input P0. Outputs A1, A2, and A3 are all controlled in parallel by input P1. Both outputs can also be controlled via the SPI port as well, but only if the three outputs are commanded ON at the same time. VBAT VBAT VBAT VBAT VBAT VBAT 33397 A5 VPWR A4 A0 SCLK P2 P1 SI To Microprocessor VBAT VDD GND GND GND GND GND GND GND GND SO Parallel Inputs (Optional) P0 CS EN A3 A1 A2 VDD From Microprocessor VDD 33397 A5 VPWR A4 A0 SCLK P2 SI To Microprocessor VBAT VBAT P1 GND GND GND GND GND GND GND GND SO Figure 18. Dual Mode Application Circuit Parallel Inputs (Optional) P0 CS EN A3 A1 A2 VDD From Microprocessor VDD VBAT Figure 17. Hex Mode Application Circuit 33397 16 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using "98ASB42344B". DW SUFFIX EG SUFFIX (PB-FREE) 20-PIN PLASTIC PACKAGE 98ASB42344B ISSUE F 33397 Analog Integrated Circuit Device Data Freescale Semiconductor 17 REVISION HISTORY PACKAGE DIMENSIONS REVISION HISTORY REVISION DATE DESCRIPTION * * * * * 3.0 12/2006 Implemented Revision History page Converted to Freescale template Added EG Pb-FREE suffix. Added MCZ33397EG/R2 to the Ordering Information Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. * Added notes Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. on page 4 and Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on page 4 33397 18 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MC33397 Rev. 3.0 12/2006 RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. 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