© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 7 1Publication Order Number:
MC74VHCU04/D
MC74VHCU04
Hex Inverter
(Unbuffered)
The MC74VHCU04 is an advanced high speed CMOS unbuffered
inverter fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The inputs tolerate voltages up to 7.0 V, allowing the interface of
5.0 V systems to 3.0 V systems.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 10% VCC (Min.)
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 12 FETs or 3 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
Figure 1. Logic Diagram
Y1A1
A2
A3
A4
A5
A6
Y2
Y3
Y4
Y5
Y6
1
3
5
9
11
13
2
4
6
8
10
12
Y = A
MARKING
DIAGRAMS
TSSOP−14
DT SUFFIX
CASE 948G
1
SOIC−14
D SUFFIX
CASE 751A
1
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
A = Assembly Location
WL, L = Wafer Lot
Y, YY = Year
WW, W = Work Week
G or G= Pb−Free Package
VHCU04G
AWLYWW
1
14
VHCU
04
ALYWG
G
1
14
(Note: Microdot may be in either location)
L
H
FUNCTION TABLE
Inputs Outputs
A
H
L
Y
MC74VHCU04
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2
Figure 2. Pinout: 14−Lead Packages
1314 12 11 10 9 8
21 34567
VCC A6 Y6 A5 Y5 A4 Y4
A1 Y1 A2 Y2 A3 Y3 GND
(Top View)
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage –0.5 to + 7.0 V
Vin DC Input Voltage –0.5 to + 7.0 V
Vout DC Output V oltage –0.5 to VCC + 0.5 V
IIK Input Diode Current −20 mA
IOK Output Diode Current ±20 mA
Iout DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, SOIC Package†
TSSOP Package† 500
450 mW
Tstg Storage Temperature – 65 to + 150 _C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage 2.0 5.5 V
Vin DC Input Voltage 0 5.5 V
Vout DC Output V oltage 0 VCC V
TAOperating Temperature −40 + 85 _C
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74VHCU04
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3
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions VCC
V
TA = 25°C TA = −40 to 85°C
Unit
Min Typ Max Min Max
VIH Minimum High−Level
Input Voltage 2.0
3.0 to 5.5 1.70
VCC x 0.8 1.70
VCC x 0.8 V
VIL Maximum Low−Level
Input Voltage 2.0
3.0 to 5.5 0.30
VCC x 0.2 0.30
VCC x 0.2 V
VOH Minimum High−Level
Output Voltage Vin =VIL
IOH = −50mA2.0
3.0
4.5
1.8
2.7
4.0
2.0
3.0
4.5
1.8
2.7
4.0
V
Vin = GND
IOH = −4mA
IOH = −8mA 3.0
4.5 2.58
3.94 2.48
3.80
VOL Maximum Low−Level
Output Voltage Vin = VIH
IOL = 50mA2.0
3.0
4.5
0.0
0.0
0.0
0.2
0.3
0.5
0.2
0.3
0.5
V
Vin = VCC
IOL = 4mA
IOL = 8mA 3.0
4.5 0.36
0.36 0.44
0.44
Iin Maximum Input
Leakage Current Vin = 5.5 or GND 0 to 5.5 ±0.1 ±1.0 mA
ICC Maximum Quiescent
Supply Current Vin = VCC or GND 5.5 2.0 20.0 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol Parameter Test Conditions
TA = 25°C TA = −40 to 85°C
Unit
Min Typ Max Min Max
tPLH,
tPHL Maximum Propagation Delay
,
A or B to Y VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF 5.0
7.5 8.9
11.4 1.0
1.0 10.5
13.0 ns
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF 3.5
5.0 5.5
7.0 1.0
1.0 6.5
8.0
Cin Maximum Input Capacitance 5 10 10 pF
CPD Power Dissipation Capacitance (Per Inverter) (Note 1)
Typical @ 25°C, VCC = 5.0V
pF
9
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/6 (per buffer). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
Symbol Characteristic
TA = 25°C
Unit
Typ Max
VOLP Quiet Output Maximum Dynamic VOL 0.5 0.8 V
VOLV Quiet Output Minimum Dynamic VOL −0.5 −0.8 V
VIHD Minimum High Level Dynamic Input Voltage 4.0 V
VILD Maximum Low Level Dynamic Input Voltage 1.0 V
MC74VHCU04
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4
Figure 3. Switching Waveforms
VCC
GND
50%
50% VCC
A
Y
tPHL
tPLH
*Includes all probe and jig capacitance
Figure 4. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5. Input Equivalent Circuit
INPUT OUTPUT
Parasitic Diode
Parasitic Diode
ORDERING INFORMATION
Device Package Shipping
MC74VHCU04DR2G SOIC−14
(Pb−Free) 2500 / Tape & Reel
MC74VHCU04DTR2G TSSOP−14
(Pb−Free) 2500 / Tape & Reel
NLV74VHCU04DTR2G* TSSOP−14
(Pb−Free) 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC74VHCU04
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5
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−− 1.20 −− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74VHCU04
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6
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
MC74VHCU04/D
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Order Literature: http://www.onsemi.com/orderlit
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al
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