Advance Product Brief
June 2003
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD)
SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Features
General
■Section and line overhead termination/generation:
— On the line-side SFI-4 ® interface, either:
❏One STS-192/STM-64 or
❏Four STS-48/STM-16
—On the system interface, either:
❏One STS-192/STM-64 or
❏Four STS-48/STM-16
■Low-voltage differential signal (LVDS) I/O for line
and system interfaces operating at 622 MHz
(T-Pro and TD-Pro). CML differential I/O for system
interfaces operating at 2.5 GHz (T-Pro).
■Path processing:
—Full receive
1 and transmit path processing for
any valid2 mix of STS-1 and concatenated pay-
loads from STS-3c to STS-48c.
■Flexible (hitless switching) interfaces (most DWDM
applications will not require the backplane inter-
face3):
— The MARS10G T-Pro system transmit (add)
interface consists of four input ports which can
operate simultaneously. The system transmit
data path includes 4:1 selection function which
can select input data at STS-1 granularity. The
maximum bandwidth of selected transmit sig-
nals is 10 Gbits/s:
❏Two 16 × 1 @ 6224 Mbits/s ports for back-
plane redundancy/mate-port with clock and
data recovery.
❏Two 4 × 1 @ 2.5 Gbits/s ports for backplane
redundancy/mate-port with clock and data
recovery.
—The MARS10G TD-Pro system transmit (add)
interface consists of one input port. The maxi-
mum bandwidth of the transmit signals is
10 Gbits/s:
❏One 1 × 16/4 × 4 @ 622 Mbits/s secondary
line interface (SFI-4) port allowing
optics-to-optics (OEO) applications (forward
or contraclocked
STS-192/STM-64/STS-48/STM-16).
—The MARS10G T-Pro system receive (drop)
data path provides a 1:4 splitter function to the
following four output interfaces (each line of a
622 Mbits/s backplane port is an STS-12. A line
of a 2.5 Gbits/s backplane port is either an
aggregate of four STS-12s or a single STS-48):
❏Two 16 × 1 @ 622 Mbits/s ports for backplane
redundancy/mate-port with clock and data
recovery generation.
❏Two 4 × 1 @ 2.5 Gbits/s ports for backplane
redundancy/mate-port with clock and data
recovery.
—The MARS10G TD-Pro system receive (drop)
data path provides:
❏One 1 × 16/4 × 4 @ 622 Mbits/s secondary
line interface (SFI-4) port (forward or contra-
clocked STS-192/STM-64/STS-48/STM-16).
■10 Gbits/s cross connect:
— Independent 10 Gbits/s cross connect in each
data path (transmit and receive) with dual con-
nection maps and synchronized switching.
■Mate-port to mate interface:
— Interconnects MARS10G T-Pros on different line
cards supporting 1 + 1, 1:1, UPSR, and BLSR
ring applications.
— Reduces the size of cross connect hardware by
20% in some 1 + 1 protection switching archi-
tectures.
■Loopbacks:
— Terminal and facility loopbacks on line interface.
— Terminal loopbacks on each of the system back-
plane interfaces.
— Regenerator loopback facility on the line inter-
face.
1. Receive is used to indicate the line interface to system data flow
direction, while transmit is used to indicate the system to line inter-
face data flow direction.
2. Valid means concatenated payloads must begin on an STS-3
boundary.
3. The DWDM version (MARS10G TD-Pro) of the product does not
support the 622 MHz or 2.5 GHz backplane drivers. In applica-
tions where the backplane is required, it is recommended to use
the MARS10G T-Pro, the SONET/SDH version.
4. n × m @ z Mbits/s = n groups of m lines are grouped together in
parallel at line speed of z. Special case: shortened forms are as
follows: 1 × 4 @ 622 MHz → 4 @ 622, 16 × 1 @ 622 → 16 × 622.
2Agere Systems Inc.
Advance Product Brief
June 2003
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD)
SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Features (continued)
General (continued)
■Transparency:
— Full bidirectional TOH transparency support with
timing independence (pointer processor) enabled
or disabled in the transmit and receive directions,
optionally, with two steps of stacked overhead
transparency.
■Tandem connection maintenance (TCM) in receive
and transmit data paths, on a per STS-1 granularity,
to originate and terminate a tandem connection.
■Built-in PRBS generator and monitor with STS-12
granularity for self test and system diagnostics.
■The microprocessor interface can be configured to
operate with most commercial microprocessors at up
to 66 MHz.
■IEEE ® 1149.1 port with memory BIST and boundary
scan (JTAG).
■Low-power 1.5 V operation with 3.3 V (5 V tolerant1)
inputs and outputs.
■Selectable powerup of only the required system ports.
The power for any given configuration is determined
by the number of active ports/lines and how many
internal functions are active. For the MARS10G T-Pro
version, approximately 150 mW per 622 MHz CDR
line and 120 mW per 2.5 GHz CDR line. For the
MARS10G TD-Pro version, approximately 650 mW
for the sixteen-wire secondary line SFI-4
STS-192/STS-48/STM-64/STM-16 interface.
■1724-pin 45 mm × 45 mm FCBGA (flip-chip ball grid
array) package.
■–40 °C to 85 °C temperature range.
Line Interface
■Supports a maximum of 10 Gbits/s data bandwidth
composed of either of the following:
❏One 16-bit parallel (1 × 16 @ 622 Mbits/s
STS-192), forward clocked interface.
❏Up to four 4-bit parallel (4 × 4 @ 622 Mbits/s
STS-48), forward clocked interfaces.
■Optional AIS-L regeneration at receive line interface.
■In regenerator loopback mode, generates AIS-L due
to receive LOS, LOF, or clock failure.
■Synchronizes to the receive data frames and detects
severely errored framing (SEF) and loss of frame
(LOF). It also inserts the framing bytes (A1, A2) in
the transmit data.
■Supports enhanced framing (A1, A1, A2, A2).
■Performs frame synchronous scrambling and
descrambling of the
STS-192/STM-64/STS-48/STM-16 data.
■Detects loss of signal (LOS) with a provisionable win-
dow from 100 ns to 100 µs.
■Extracts the 64-byte or 16-byte section trace mes-
sage (J0) from the receive data and optionally stores
it in, or compares it to, an internal register bank.
Unstable or mismatched messages are detected.
■Optionally inserts a 64-byte or 16-byte section trace
message or a fixed pattern in the J0 byte of the
transmit data.
■Extracts and outputs on a serial link all transport
overhead (TOH) bytes in the incoming data (both
receive and transmit paths) and inserts any or all
transport overhead bytes in the outgoing data (both
receive and transmit paths) using a corresponding
serial input.
■Extracts, integrates, and stores the automatic protec-
tion switch (APS) channel bytes (K1, K2) for the
receive data and detects protection switch failure
alarms. Inserts APS bytes in the transmit data from
internal registers or from overhead bytes in the add
data.
■Detects line alarm indication signal (AIS-L) and
remote defect indication (RDI-L) based on the K2
byte of the receive data. Inserts AIS-L and RDI-L in
the transmit data. Optionally inserts RDI-L automati-
cally due to LOS, LOF, or line AIS defects.
■Extracts, integrates, and stores the synchronization
status byte (S1) for the receive data. Inserts the syn-
chronization status byte into the transmit data from
an internal register or from a value encoded on the
transmit frame sync input.
■Calculates, detects, and counts section and line
BIP-8 errors (B1, B2) for the receive data and inserts
BIP-8 in the transmit data. Supports either bit
(B1, B2) or block (B1) error accumulation, each sep-
arately provisionable.
■Extracts and counts line remote errors (REI-L) for the
receive data (M1) and inserts REI-L in the transmit
data based on B2 errors (provisionable based on bit
or block errors).
1. Tolerant means the inputs will safely survive the application of 5.0 V,
the input voltages should not exceed 3.3 V in normal operation.
Agere Systems Inc. 3
Advance Product Brief
June 2003
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD)
SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Features (continued)
System Interface
■For the MARS10G T-Pro version, clock/data recov-
ery (CDR) and 64-byte buffer for skew compensation
in the add direction.
■Path overhead and SPE timing in the drop direction.
■Port selection—data selected (groomed) at STS-1
granularity, selected to maximum bandwidth of
10 Gbits/s from the following system ports:
— One redundant set of 16 × 1 @ 622 Mbits/s paral-
lel backplane interfaces (T-Pro only).
— One redundant set of 4 × 1 @ 2.5 Gbits/s back-
plane interfaces (T-Pro only).
— Secondary line SFI-4 interface consisting of a 4-bit
wide bus (4 × 4 @ 622 Mbits/s) or one 16-bit par-
allel port (1 × 16 @ 622 Mbits/s) forward or contra-
clocked STS-192/STM-64/STS-48/STM-16
(TD-Pro only):
❏The secondary line interface functions identi-
cally to its complementary line interface (see
Line Interface on page 2).
■For the MARS10G T-Pro version, mate-port function-
ality can be used to connect MARS10G T-Pro
devices on different line cards using either a
622 Mbits/s or a 2.5 Gbits/s backplane interface port,
while other backplane interface ports continue redun-
dant data operations.
■Independent 10 Gbits/s cross connect with STS-1
granularity in the transmit and receive data paths,
with dual connection maps.
■For the MARS10G T-Pro version, port selection (4:1)
and transmit/receive cross connects can be switched
independently or mutually and synchronized either to
software, external, or overhead byte trigger.
■Optional generation of an external or OH trigger in
the drop direction.
■Outputs path alarm information for each receive STS
in the overhead bytes of the drop data (E1/F1).
■Alarms on TFRM out-of-buffer range on add interface.
Path Processing
■Implements the hardware portion of TIM-P and
TIM-S code processing for the section user channel
(F1) and orderwire channels (E1, E2) for the receive
data and the transmit data.
■Interprets the pointer bytes (H1, H2) for each incom-
ing STS and detects loss of pointer (LOP) and path
AIS. Supports STS-1 level provisioning of SS bits
inclusion/exclusion and value for LOP detection.
Generates new pointer bytes in each outgoing STS
to adapt the incoming data to the drop frequency and
phase. Supports STS-1 level provisioning of pass
through or overwriting of generated SS bits. Pointer
generation can be bypassed for synchronous appli-
cations.
■Optionally inserts path AIS in all outgoing STS
pointer bytes during LOS, LOF, SEF, TIM-S, or line
AIS defects. Optionally inserts path AIS in each out-
going STS due to LOP, TIM-P, or path AIS defects in
the corresponding incoming STS or under software
control.
■Extracts the 64-byte or 16-byte path trace message
(J1) from up to sixteen selectable receive STS chan-
nels (one per STS-12) and stores it in an internal
register bank. Optionally compares the message to
an expected message stored in the internal register
bank and detects an unstable or mismatched mes-
sage.
■Calculates, detects, and accumulates path BIP-8
errors (B3) for each receive STS (provisionable
based on bit or block errors). Provides signal fail
detection with provisionable BER. Optionally inserts
path REI in the transmit G1 byte based on receive B3
errors.
■Extracts and counts path REI (provisionable on a bit
or block basis) for each receive STS (G1).
■Detects path unequipped, payload label mismatch
(PLM), and optionally, payload defect indication
(PDI) in the C2 byte of each receive STS. Optionally
inserts AIS-P downstream and ERDI-P upstream
due to PLM-P or UNEQ-P. Inserts unequipped signal
in each transmit STS under software control.
■Detects 1-bit and enhanced path RDI in each receive
STS (G1).
■Path overhead insertion/extraction through serial
ports of both transmit and receive data paths.
4Agere Systems Inc.
Advance Product Brief
June 2003
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD)
SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Features (continued)
Mate-Port—Mate-to-Mate Interface
■The mate interface on the MARS10G T-Pro device is
a mate-port function using the dual redundant sys-
tem ports.
■The mate-to-mate backplane interface allows the
MARS10G T-Pro device, on different line cards, to
be connected to each other using 622 MHz (LVDS)
or 2.5 GHz (CML) backplane signals to support
1 + 1, 1:1, UPSR, and BLSR ring applications. Con-
currently, the other set of ports (2.5 GHz or 622 MHz,
respectively) will continue to be able to carry redun-
dant data.
■Advantages of the mate interface are as follows:
— This feature will enable switching software to
reside on line cards instead of switch cards in
UPSR and BLSR applications. This will help
reduce software development costs by streamlin-
ing software architecture of switch cards and parti-
tioning software on switch cards and line cards.
— The feature will enable more than 20% reduction
in the size of cross connect hardware for a 1 + 1
protection switching case. These savings will
apply to the following architectures:
❏Redundant architectures with framer and cross
connect on the same card.
❏Simplex equipment protection and duplex net-
work protection architectures.
Sample Applications
■SONET/SDH add-drop multiplex equipment.
■SONET/SDH terminal equipment.
■SONET/SDH digital cross-connect equipment.
■SONET/SDH digital line-card with mate-port con-
nect.
■SONET/SDH test equipment.
■ATM or packet over SONET/SDH equipment.
■SONET/SDH DWDM equipment.
Figure 1. SONET/SDH ADM with Redundant
System Connections
Figure 2. DWDM/OADM Concentrator MUX
Figure 3. Transparent MUX
MARS10G
LINE INTERFACE
SYSTEM INTERFACE
OC-48
4×622
TDCS6440G
TDCS6440G
TDCS6440G
TDCS6440G
16 × 622
OC-48
4×622
OC-48
4×622
OC-12
622
OC-12
622
OC-12
622
REDUNDANT
CROSS-CONNECT
CARDS
OC-12
622
T-Pro
MARS10G
LINE INTERFACE
SYSTEM INTERFACE
OC-192
16 @ 622
OC-48
4×622
OC-48
4×622
OC-48
4×622
OC-12
622
OC-12
622
OC-12
622
OC-12
622 TD-Pro
MARS10G
LINE INTERFACE
SYSTEM INTERFACE
OC-12
622
OC-12
622
OC-12
622
OC-12
622
OC-192
16 @ 622
OC-12
622
OC-12
622
(16 TOTAL) T-Pro
OR
TD-Pro
Agere Systems Inc. 5
Advance Product Brief
June 2003
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD)
SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Sample Applications (continued)
Figure 4. Mate-Port Connect using 622 MHz Interface with Cross Connect Connections using Redundant
2.5 GHz Interfaces
TRIB
MARS10G
16 @ 622
REDUNDANT
CROSS-CONNECT
SWITCH CARDS
LINE
SYSTEM
16×622
OC-192
EAST LINE CARD
4×2.5G
MARS10G
WEST LINE CARD
4×2.5G
MATE
LINE
LS
TRIBTRIB
CARD
LS
CARD
SWITCH CARDS
SYSTEM
16×622
OC-192
T-Pro
T-Pro
6Agere Systems Inc.
Advance Product Brief
June 2003
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD)
SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Description
The MARS10G T-Pro and MARS10G TD-Pro are two devices of Agere Systems’ next generation system-on-a-chip
MARS™ family of framers. The MARS10G T-Pro/MARS10G TD-Pro is used to terminate the transport overhead of
one STS-192 (STM-64) signal or four STS-48 (STM-16) signals, to a maximum bandwidth of 10 Gbits/s. It performs
STS path pointer processing to synchronize the incoming data streams to the outgoing frequency and phase. The
MARS10G T-Pro/MARS10G TD-Pro can be provisioned to support any mix of STS-1 (AU-3) or STS-Nc (AU-4-Xc)
payloads from a single STS-192c (AU-4-64c) channel to 192 STS-1 (AU-3) channels.
For the MARS10G T-Pro version, the system interface has four port interfaces which can operate concurrently with
two redundant backplane interfaces (622 MHz and 2.5 GHz). The backplane interface performs clock and data
recovery on the transmit add data. The drop data is not accompanied with a clock, and therefore assumes clock
and data recovery at the destination. The backplane interfaces support 4:1 port selection on the incoming add data,
and 1:4 splitter capability on the drop data.
On the add backplane interface on the system side, the 4:1 port selector permits STS-1 level selection from two
redundant sets of independently timed incoming STS-12s/STS-48s. Two duplicated sets of outgoing
STS-12s/STS-48s can be created. The receive and transmit cross connects provide STS-1 level grooming in both
directions.
The 4:1 port selector can be configured in one of two modes. In backplane interface mode, the port selector acts as
a work/protect switch. In space switch mode, two programable configuration maps allow for hitless 4:1 space
switching at an STS-1 level of granularity between A_DATA1, A_DATA2, A2488DATA1, and A2488DATA2. Also,
the 4:1 space switch (or backplane selector) can be synchronized to switch in conjunction with the add cross con-
nect.
For the MARS10G TD-Pro version, the secondary line interface provides connection to the second fiber and is
used to terminate the transport overhead of an STS-192/STS-48/STM-64/STM-16 signal (bandwidth of 10 Gbits/s).
It performs STS path pointer processing to synchronize incoming data streams to the outgoing frequency and
phase. It can be provisioned to support any mix of STS-1 (AU-3) or STS-Nc (AU-4-Xc) payloads from a single
STS-192c (AU-4-64c) channel to 192 STS-1 (AU-3) channels. The secondary line interface has equivalent fea-
tures to the (primary) line interface functions.
Overall block diagrams are shown in Figure 5 on page 7 and Figure 6 on page 8.
The microprocessor interface allows an external processor to access the MARS10G T-Pro/MARS10G TD-Pro for
configuration and maintenance. The microprocessor interface is designed to support various 16-bit microproces-
sors with minimal glue logic.
The MARS10G T-Pro/MARS10G TD-Pro includes an IEEE 1149.1 compliant JTAG port to support boundary scan
and memory BIST.
Advance Product Brief
June 2003
Agere Systems Inc. 7
SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD)
Description (continued)
Figure 5. MARS10G T-Pro (TSOT1610GP) Block Diagram
RECEIVE
LINE (Rx)
INTERFACE
RECEIVE
SECTION/LINE
OVERHEAD
RECEIVE STS PATH PROCESSOR
RECEIVE
PATH
OVERHEAD
PROCESSOR
RECEIVE
POINTER
GENERATOR
RECEIVE
DROP
CROSS
CONNECT
RECEIVE
SECTION/LINE
OVERHEAD
GENERATOR
RECEIVE
SYSTEM
INTERFACE
TRANSMIT
LINE (TX)
INTERFACE
TRANSMIT
POINTER
INTERPRET
TRANSMIT
PATH
OVERHEAD
PROCESSOR
4:1
TRANSMIT
ALIGNMENT
FIFO
TRANSMIT
SECTION/LINE
OVERHEAD
TERMINATOR
TRANSMIT
SYSTEM
INTERFACE
TRANSMIT
SECTION/LINE
OVERHEAD
GENERATION
TERMINATION
SECTION
TRACE
BUFFER
SECTION
TRACE
BUFFER
PATH
TRACE
BUFFER
PATH
TRACE
BUFFER
TFRM_[1,5,9,13]
T_CLK_[1—16]
TD_[1:16]
T_CLKO_[1,5,9,13]
R_CLK_[1—16]
RD_[1:16]
RFRMO_[1,5,9,13]
R_CLKO_[1,5,9,13]
TRANSMIT
POINTER
GENERATOR
DDATA2_[16:1]
ADATA1_[16:1]
A_CLKL
DDATA1_[16:1]
ADATA2_[16:1]
TADCC1_[1—4]
TADCK_[1—4]
RDDCC_[1—4]
RDDCK_[1—4]
ERTOHDAT_[7:0]
ERTOHFP
ERTOH_CLK
ERTOHVALID
ERTOHSYNC
ITTOHDAT_[7:0]
ITTOHFP
ITTOH_CLK
ITTOHVALID
ITTOHSYNC
ITTOHEN
ETTOHDAT_[7:0]
ETTOHFP
ETTOH_CLK
ETTOHVALID
ETTOHSYNC
IRTOHDAT_[7:0]
IRTOHFP
IRTOH_CLK
IRTOHVALID
IRTOHSYNC
IRTOHEN
PCLK
PARITY_[1:0]
DATA_[15:0]
ADDRESS_[15:0]
CS_N
TS_N
DS_N
RW_N
TA_N
TEA_N
INT_N
PM_CLK
MPMODE_[1:0]
MICROPROCESSOR INTERFACE
JTAG INTERFACE
TOH TRANSPARENCY
LINE FACILITY LOOPBACK
SYSTEM TERMINAL LOOPBACK
LINE TERMINAL LOOPBACK
REGEN LOOPBACK
x16
x16
x16
x16
x4
x4
x4
x16
ERPOHDAT_[7:0]
ERPOHFP
ERPOH_CLK
ERPOHVALID
ERPOHSYNC
IRPOHDAT_[7:0]
IRPOHFP
IRPOH_CLK
IRPOHVALID
IRPOHSYNC
IRPOHEN
ITPOHDAT_[7:0]
ITPOHFP
ITPOH_CLK
ITPOHVALID
ITPOHSYNC
ITPOHEN
ETPOHDAT_[7:0]
ETPOHFP
ETPOH_CLK
ETPOHVALID
ETPOHSYNC
PART_L
REGEN LOOPBACK
x4
TSI (48:12)
x4
D2488DATA1_[4:1]
D2488DATA2_[4:1]
A2488DATA1_[4:1]
A2488DATA2_[4:1]
SYS_LINE
TPPBYP_[1—4]
RPPBYP_[1—4]
1:4
MATE
ALIGNMENT
FIFO
TADSYN_[1—4]
RST_N
HIZ_N
TXSYNC_N_[1—4]
RXSYNC_N_[1—4]
PARITY_EN
PARITY_MODE
RDDSYN_[1—4]
TADCC2_[1—4]
AFRM
RECEIVE DATA FLOW = LINE INTERFACE TO SYSTEM INTERFACE
TRANSMIT DATA FLOW = SYSTEM INTERFACE TO LINE INTERFACE
RECEIVE LINE INTERFACE
TRANSMIT LINE INTERFACE
RECEIVE
SYSTEM
INTERFACES
TRANSMIT
SYSTEM
INTERFACES
DFRM
D_CLKL
TOH Insertion
TOH TRANSPARENCY
AFRMO
TOH Extraction
INTERFACE
PATH OVERHEAD INSERT/
EXTRACT INTERFACES
TOH Insertion
INTERFACE
TOH Extraction
INTERFACE
INTERFACE
PATH OVERHEAD INSERTION/
EXTRACT INTERFACE
RECEIVE
POINTER
INTERPRET
TRANSMIT STS PATH PROCESSOR
TRANSMIT
ADD
CROSS
CONNECT
x4
(Rx)
(Tx)
ADD
ADD
DROP
TDO
TDI
TCK
TMS
TRST_N
8Agere Systems Inc.
Advance Product Brief
June 2003
SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD)
Description (continued)
Figure 6. MARS10G TD-Pro (TSOT1610GPD) Block Diagram
RECEIVE
LINE (Rx)
INTERFACE
RECEIVE
SECTION/LINE
OVERHEAD
RECEIVE STS PATH PROCESSOR
RECEIVE
PAT H
OVERHEAD
PROCESSOR
RECEIVE
POINTER
GENERATOR
RECEIVE
DROP
CROSS
CONNECT
RECEIVE
SECTION/LINE
OVERHEAD
GENERATOR
TRANSMIT
LINE (TX)
INTERFACE
TRANSMIT
POINTER
INTERPRET
TRANSMIT
PAT H
OVERHEAD
PROCESSOR
TRANSMIT
SECTION/LINE
OVERHEAD
TERMINATOR
TRANSMIT
SECTION/LINE
OVERHEAD
GENERATION
TERMINATION
SECTION
TRACE
BUFFER
SECTION
TRACE
BUFFER
PATH
TRACE
BUFFER
PATH
TRACE
BUFFER
TFRM_[1,5,9,13]
T_CLK_[1—16]
TD_[1:16]
T_CLKO_[1,5,9,13]
R_CLK_[1—16]
RD_[1:16]
RFRMO_[1,5,9,13]
R_CLKO_[1,5,9,13]
TRANSMIT
POINTER
GENERATOR
D_CLKO_[1—4]
ERTOHDAT_[7:0]
ERTOHFP
ERTOH_CLK
ERTOHVALID
ERTOHSYNC
ITTOHDAT_[7:0]
ITTOHFP
ITTOH_CLK
ITTOHVALID
ITTOHSYNC
ITTOHEN
ETTOHDAT_[7:0]
ETTOHFP
ETTOH_CLK
ETTOHVALID
ETTOHSYNC
IRTOHDAT_[7:0]
IRTOHFP
IRTOH_CLK
IRTOHVALID
IRTOHSYNC
IRTOHEN
PCLK
PARITY_[1:0]
DATA_[15:0]
ADDRESS_[15:0]
CS_N
TS_N
DS_N
RW_N
TA_N
TEA_N
INT_N
PM_CLK
MPMODE_[1:0]
MICROPROCESSOR INTERFACE JTAG INTERFACE
TOH TRANSPARENCY
LINE FACILITY LOOPBACK
SYSTEM TERMINAL LOOPBACK
SYSTEM FACILITY LOOPBACK
REGEN LOOPBACK
x16
x16
x16
ERPOHDAT[7:0]
ERPOHFP
ERPOH_CLK
ERPOHVALID
ERPOHSYNC
IRPOHDAT_[7:0]
IRPOHFP
IRPOH_CLK
IRPOHVALID
IRPOHSYNC
IRPOHEN
ITPOHDAT_[7:0]
ITPOHFP
ITPOH_CLK
ITPOHVALID
ITPOHSYNC
ITPOHEN
ETPOHDAT_[7:0]
ETPOHFP
ETPOH_CLK
ETPOHVALID
ETPOHSYNC
REGEN LOOPBACK
TSI (48:12)
x2
TPPBYP_[1—4]
RPPBYP_[1—4]
RST_N
HIZ_N
TXSYNC_N_[1—4]
RXSYNC_N_[1—4]
PARITY_EN
PARITY_MODE
A_RD_[16:1]
A_CLK_[1—4]
AFRMO_[1—4]
A_CLKO_[1—4]
TRANSMIT
SECONDARY LINE
(Rx) INTERFACE
RECEIVE
SECONDARY
INTERFACE DFRM_[1—4]
D_CLK_[1—4]
D_TD_[1:16]
RECEIVE DATA FLOW = LINE INTERFACE TO SECONDARY LINE INTERFACES
TRANSMIT DATA FLOW = SECONDARY LINE INTERFACE TO LINE INTERFACE
RECEIVE
LINE INTERFACE
TRANSMIT
LINE INTERFACE
TRANSMIT
SECONDARY
LINE INTERFACE
RECEIVE
SECONDARY
LINE INTERFACE
TOH Insertion
TOH TRANSPARENCY
TOH Extraction
INTERFACE
PATH OVERHEAD INSERT/
EXTRACT INTERFACES
TOH Insertion
INTERFACE
TOH Extraction
INTERFACE
INTERFACE
PATH OVERHEAD INSERTION/
EXTRACT INTERFACE
RECEIVE
POINTER
INTERPRET
TRANSMIT STS PATH PROCESSOR
TRANSMIT
ADD
CROSS
CONNECT
(Rx)
(Tx)
LINE (Tx)
PART_L SYS_LINE
TDO
TDI
TCK
TMS
TRST_N
Agere Systems Inc. 9
Advance Product Brief
June 2003
MARS10G T-Pro (TSOT1610GP)/MARS10G TD-Pro (TSOT1610GPD)
SONET/SDH STS-192/STM-64 Overhead Terminator/Path Processor
Ordering Information
1. Maximum junction temperature 125 °C.
Device Code Package Ambient Temperature Comcode
MARS10G T-Pro
(TSOT1610GP)
1724-pin FCBGA –40 °C to 85 °C1700045919
MARS10G TD-Pro
(TSOT1610GPD)
1724-pin FCBGA –40 °C to 85 °C1TBD
Copyright © 2003 Agere Systems Inc.
All Rights Reserved
June 2003
PB03-036SONT
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere,
Agere Systems, and the Agere Logo are trademarks of Agere Systems Inc. MARS is a trademark of Agere Systems Inc.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@agere.com
N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
EUROPE: Tel. (44) 1344 296 400
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
SFI-4 is a registered trademark of Westinghouse Electric Corporation.
