Data Addendum May 2001 DSP16410C Digital Signal Processor 1 Introduction 3 Device Identification This addendum contains information specific to the DSP16410C. The DSP16410C is pin-compatible and functionally identical to the DSP16410B. However, the DSP16410C provides higher speed operation and lower power dissipation than the DSP16410B. This document describes the differences between the DSP16410B and the DSP16410C. It should be used as a supplement to the DSP16410B Digital Signal Processor Data Sheet (DS01-070WTEC). The DSP16410C has different JTAG identification numbers for each core. These identifiers are different from those of the DSP16410B and can be accessed through the JTAG port of each core. Table 1 lists the JTAG identification numbers for each core of the DSP16410C. 2 Features High performance: -- Up to 800 million MACS per second at 200 MHz Low power: -- 1.575 V internal supply for power efficiency -- 3.3 V I/O pin supply for compatibility Changes from the DSP16410B to the DSP16410C: -- Maximum processor speed has changed from 185 MHz to 200 MHz -- Nominal internal supply voltage changed from 1.8 V to 1.575 V -- New JTAGID register settings for both cores Table 1. Device Identifiers Identifier JTAG0 JTAGID JTAG1 JTAGID DSP16410B 0x2c81403b 0x3c81403b DSP16410C 0x4c81403b 0x5c81403b DSP16410C Digital Signal Processor Data Addendum May 2001 Table of Contents Contents 1 2 3 4 5 6 7 8 9 2 Page Introduction ................................................................................................................................................ 1 Features ..................................................................................................................................................... 1 Device Identification ................................................................................................................................... 1 Notation Conventions................................................................................................................................. 6 Ball Grid Array Information......................................................................................................................... 7 5.1 208-Ball PBGA Package .................................................................................................................. 7 5.2 256-Ball EBGA Package ................................................................................................................ 10 Device Characteristics ............................................................................................................................. 13 6.1 Absolute Maximum Ratings............................................................................................................ 13 6.2 Handling Precautions ..................................................................................................................... 13 6.3 Recommended Operating Conditions ............................................................................................ 14 6.3.1 Package Thermal Considerations .......................................................................................... 14 Electrical Characteristics and Requirements ........................................................................................... 15 7.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs ........................... 17 7.2 Analog Power Supply Decoupling .................................................................................................. 18 7.3 Power Dissipation........................................................................................................................... 19 7.3.1 Internal Power Dissipation...................................................................................................... 19 7.3.2 I/O Power Dissipation............................................................................................................. 20 7.4 Power Supply Sequencing Issues .................................................................................................. 21 7.4.1 Supply Sequencing Recommendations ................................................................................. 21 7.4.2 External Power Sequence Protection Circuits........................................................................ 23 Timing Characteristics and Requirements ............................................................................................... 24 8.1 Phase-Lock Loop ........................................................................................................................... 25 8.2 Wake-Up Latency ........................................................................................................................... 25 8.3 DSP Clock Generation ................................................................................................................... 26 8.4 Reset Circuit ................................................................................................................................... 27 8.5 Reset Synchronization.................................................................................................................... 28 8.6 JTAG .............................................................................................................................................. 29 8.7 Interrupt and Trap........................................................................................................................... 30 8.8 Bit I/O ............................................................................................................................................. 31 8.9 System and External Memory Interface ......................................................................................... 32 8.9.1 Asynchronous Interface.......................................................................................................... 33 8.9.2 Synchronous Interface ........................................................................................................... 36 8.9.3 ERDY Interface ...................................................................................................................... 38 8.10 PIU ................................................................................................................................................. 39 8.11 SIU ................................................................................................................................................. 43 Package Diagrams................................................................................................................................... 53 9.1 208-Pin PBGA ................................................................................................................................ 53 9.2 256-Pin EBGA ................................................................................................................................ 54 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor List of Figures Figure Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Page 208-Ball PBGA Package Ball Grid Array Assignments (See-Through Top View)................................ 7 256-Ball EBGA Package Ball Grid Array Assignments (See-Through Top View).............................. 10 Plot of VOH vs. IOH Under Typical Operating Conditions .................................................................... 16 Plot of VOL vs. IOL Under Typical Operating Conditions ..................................................................... 16 Analog Supply Bypass and Decoupling Capacitors ........................................................................... 18 Power Supply Sequencing Recommendations .................................................................................. 22 Power Supply Example ...................................................................................................................... 23 Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs ....... 24 I/O Clock Timing Diagram ................................................................................................................. 26 Powerup and Device Reset Timing Diagram .................................................................................... 27 Reset Synchronization Timing............................................................................................................ 28 JTAG I/O Timing Diagram ................................................................................................................. 29 Interrupt and Trap Timing Diagram .................................................................................................... 30 Write Outputs Followed by Read Inputs (cbit = IMMEDIATE; a1 = sbit) Timing Characteristics ...... 31 Enable and Write Strobe Transition Timing........................................................................................ 32 Timing Diagram for EREQN and EACKN........................................................................................... 33 Asynchronous Read Timing Diagram (RHOLD = 0 and RSETUP = 0).............................................. 34 Asynchronous Write Timing Diagram (WHOLD = 0, WSETUP = 0) .................................................. 35 Synchronous Read Timing Diagram (Read-Read-Write Sequence).................................................. 36 Synchronous Write Timing Diagram................................................................................................... 37 ERDY Pin Timing Diagram................................................................................................................. 38 Host Data Write to PDI Timing Diagram............................................................................................. 39 Host Data Read from PDO Timing Diagram ...................................................................................... 40 Host Register Write (PAH, PAL, PCON, or HSCRATCH) Timing Diagram ........................................ 41 Host Register Read (PAH, PAL, PCON, or DSCRATCH) Timing Diagram........................................ 42 SIU Passive Frame and Channel Mode Input Timing Diagram.......................................................... 43 SIU Passive Frame Mode Output Timing Diagram ............................................................................ 44 SIU Passive Channel Mode Output Timing Diagram ......................................................................... 45 SCK External Clock Source Input Timing Diagram ............................................................................ 46 SIU Active Frame and Channel Mode Input Timing Diagram ............................................................ 47 SIU Active Frame Mode Output Timing Diagram ............................................................................... 49 SIU Active Channel Mode Output Timing Diagram ............................................................................ 50 ST-Bus 2x Input Timing Diagram ....................................................................................................... 51 ST-Bus 2x Output Timing Diagram .................................................................................................... 52 Agere Systems Inc. 3 DSP16410C Digital Signal Processor Data Addendum May 2001 List of Tables Table Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. 4 Page Device Identifiers.......................................................................................................................................1 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol.........................................................8 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol.......................................................11 Absolute Maximum Ratings for Supply Pins ...........................................................................................13 Recommended Operating Conditions.....................................................................................................14 Package Thermal Considerations ...........................................................................................................14 Electrical Characteristics and Requirements ..........................................................................................15 Internal Power Dissipation at 1.575 V .....................................................................................................19 I/O Power Dissipation at 3.3 V ................................................................................................................20 Power Sequencing Recommendations ...................................................................................................22 Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs.............24 PLL Requirements ..................................................................................................................................25 Wake-Up Latency....................................................................................................................................25 Timing Requirements for Input Clock......................................................................................................26 Timing Characteristics for Input Clock and Output Clock........................................................................26 Timing Requirements for Powerup and Device Reset.............................................................................27 Timing Characteristics for Device Reset .................................................................................................27 Timing Requirements for Reset Synchronization Timing ........................................................................28 Timing Requirements for JTAG I/O .........................................................................................................29 Timing Characteristics for JTAG I/O ........................................................................................................29 Timing Requirements for Interrupt and Trap ...........................................................................................30 Timing Requirements for BIO Input Read ...............................................................................................31 Timing Characteristics for BIO Output ....................................................................................................31 Timing Characteristics for Memory Enables and ERWN ........................................................................32 Timing Requirements for EREQN ...........................................................................................................33 Timing Characteristics for EACKN and SEMI Bus Disable .....................................................................33 Timing Requirements for Asynchronous Memory Read Operations.......................................................34 Timing Characteristics for Asynchronous Memory Read Operations .....................................................34 Timing Characteristics for Asynchronous Memory Write Operations .....................................................35 Timing Requirements for Synchronous Read Operations.......................................................................36 Timing Characteristics for Synchronous Read Operations .....................................................................36 Timing Characteristics for Synchronous Write Operations .....................................................................37 Timing Requirements for ERDY Pin ........................................................................................................38 Timing Requirements for PIU Data Write Operations .............................................................................39 Timing Characteristics for PIU Data Write Operations............................................................................39 Timing Requirements for PIU Data Read Operations .............................................................................40 Timing Characteristics for PIU Data Read Operations............................................................................40 Timing Requirements for PIU Register Write Operations .......................................................................41 Timing Characteristics for PIU Register Write Operations ......................................................................41 Timing Requirements for PIU Register Read Operations .......................................................................42 Timing Characteristics for PIU Register Read Operations......................................................................42 Timing Requirements for SIU Passive Frame Mode Input ......................................................................43 Timing Requirements for SIU Passive Channel Mode Input ...................................................................43 Timing Requirements for SIU Passive Frame Mode Output ...................................................................44 Timing Characteristics for SIU Passive Frame Mode Output ..................................................................44 Timing Requirements for SIU Passive Channel Mode Output ................................................................45 Timing Characteristics for SIU Passive Channel Mode Output...............................................................45 Timing Requirements for SCK External Clock Source............................................................................46 Timing Requirements for SIU Active Frame Mode Input.........................................................................47 Timing Characteristics for SIU Active Frame Mode Input .......................................................................47 Timing Requirements for SIU Active Channel Mode Input......................................................................48 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor List of Tables (continued) Table Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Page Timing Characteristics for SIU Active Channel Mode Input ....................................................................48 Timing Requirements for SIU Active Frame Mode Output ......................................................................49 Timing Characteristics for SIU Active Frame Mode Output.....................................................................49 Timing Requirements for SIU Active Channel Mode Output ...................................................................50 Timing Characteristics for SIU Active Channel Mode Output .................................................................50 ST-Bus 2x Input Timing Requirements....................................................................................................51 ST-Bus 2x Output Timing Requirements.................................................................................................52 ST-Bus 2x Output Timing Characteristics ...............................................................................................52 Agere Systems Inc. 5 Data Addendum May 2001 DSP16410C Digital Signal Processor 4 Notation Conventions [] Square brackets enclose a range of numbers that represents multiple bits in a single register or bus. The range of numbers is delimited by a colon. For example, imux[11:10] are bits 11 and 10 of the program-accessible imux register. Angle brackets enclose a list of items delimited by commas or a range of items delimited by a dash (--), one of which is selected if used in an instruction. For example, SADD0--3 represents the four memory-mapped registers SADD0, SADD1, SADD2, and SADD3, and the general instruction aTEh,l = RB can be replaced with a0h = timer0. The following notation conventions apply to this data addendum: lower-case Registers that are directly writable or readable by DSP16410 core instructions are lower-case. UPPER-CASE Device flags, I/O pins, control register fields, and registers that are not directly writable or readable by DSP16410 core instructions are upper-case. boldface Register names and DSP16410 core instructions are printed in boldface when used in text descriptions. italics Documentation variables that are replaced are printed in italics. courier DSP16410 program examples or C-language representations are printed in courier font. 6 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 5 Ball Grid Array Information 5.1 208-Ball PBGA Package Figure 1 illustrates the ball assignment for the 208-ball PBGA package. This view is from the top of the package. The ball assignment for the DSP16410C is compatible with that of the DSP16410B. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A VDD2 ED5 ED7 ED9 ED11 ED15 ED17 VSS VDD1 ED26 ED30 ERWN1 VSS EION EA1 VDD2 A B ED3 VDD1 ED6 ED8 VSS ED14 ED16 ED20 ED25 ED27 ED31 EROMN ERAMN EA0 VDD1 EA3 B C ED2 ED1 ED4 ED10 ED12 VDD1 ED18 ED21 ED24 VDD2 ED29 ERWN0 VDD2 EA2 EA4 EA5 C D VSS ED0 VDD2 VDD1 ED13 VDD2 ED19 ED22 ED23 VSS ED28 EACKN VDD1 EA8 EA7 EA6 D E EREQN ERDY ESIZE EXM EA11 EA10 VSS EA9 E F TDO0 ERTYPE TRST0N TCK0 VDD2 VDD1 EA12 EA13 F G TDI0 TMS0 VDD2 VSS VSS VSS VSS VSS EA17 EA16 EA14 EA15 G H VDD1A CKI VSS1A RSTN VSS VSS VSS VSS ESEG1 ESEG0 EA18 VSS H J VSS INT2 INT3 TRAP VSS VSS VSS VSS ESEG2 ESEG3 VDD1 ECKO J K SICK0 SIFS0 INT0 INT1 VSS VSS VSS VSS VSS VDD2 TMS1 TDI1 K L SOCK0 SOFS0 VDD1 VDD2 TCK1 TRST1N SOD1 TDO1 L M SOD0 VSS SID0 SCK0 SID1 SCK1 SOCK1 SOFS1 M N IO0BIT5 IO0BIT4 IO0BIT6 VDD1 PD10 PD6 VSS PD1 PD0 PRDY VDD2 PCSN VDD1 VDD2 SIFS1 VSS N P IO0BIT3 IO0BIT2 IO0BIT0 VDD2 PD11 PD7 VDD2 PD2 POBE PINT VDD1 PADD3 PADD1 IO1BIT2 IO1BIT0 SICK1 P R IO0BIT1 VDD1 EYMODE PD14 PD13 PD9 PD5 VDD1 PIBF PODS PRWN VSS PADD0 IO1BIT4 VDD1 IO1BIT1 R T VDD2 VSS PD15 VSS PD12 PD8 PD4 PD3 VSS PRDYMD PIDS PADD2 IO1BIT6 IO1BIT5 IO1BIT3 VDD2 T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 1. 208-Ball PBGA Package Ball Grid Array Assignments (See-Through Top View) Agere Systems Inc. 7 Data Addendum May 2001 DSP16410C Digital Signal Processor 5 Ball Grid Array Information (continued) 5.1 208-Ball PBGA Package (continued) Table 2 describes the PBGA ball assignments sorted by symbol for the 208-ball package. For each signal or power/ground connection, this table lists the PBGA coordinate, the symbol name, the type (I = input, O = output, I/O = input/output, O/Z = 3-state output, P = power, G = ground), and description. Inputs and bidirectional pins do not maintain full CMOS levels when not driven. They must be pulled to VDD2 or VSS through the appropriate pull up/down resistor (refer to Section 7.1). An unused external SEMI data bus (ED[31:0]) can be statically configured as outputs by asserting the EYMODE pin. At full CMOS levels, no significant dc current is drawn. Table 2. 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol Symbol CKI EA[18:0] EACKN ECKO ED[31:0] 208-Ball PBGA Coordinate H2 H15, G13, G14, G16, G15, F16, F15, E13, E14, E16, D14, D15, D16, C16, C15, B16, C14, A15, B14 D12 Type Description I External Clock Input. O External Address Bus, Bits 18--0. O External Device Acknowledge for External Memory Interface (negative assertion). Programmable Clock Output. External Memory Data Bus, Bits 31--0. O I/O EION ERAMN ERDY EREQN J16 B11, A11, C11, D11, B10, A10, B9, C9, D9, D8, C8, B8, D7, C7, A7, B7, A6, B6, D5, C5, A5, C4, A4, B4, A3, B3, A2, C3, B1, C1, C2, D2 A14 B13 E2 E1 EROMN ERTYPE B12 F2 O I ERWN0 ERWN1 ESEG[3:0] ESIZE C12 A12 J14, J13, H13, H14 E3 O O O I EXM EYMODE INT[3:0] IO0BIT[6:0] IO1BIT[6:0] PADD[3:0] PCSN PD[15:0] E4 R3 J3, J2, K4, K3 N3, N1, N2, P1, P2, R1, P3 T13, T14, R14, T15, P14, R16, P15 P12, T12, P13, R13 N12 T3, R4, R5, T5, P5, N5, R6, T6, P6, N6, R7, T7, T8, P8, N8, N9 R9 T11 P10 I I I I/O I/O I I I/O Enable for External I/O (negative assertion). External RAM Enable (negative assertion). External Memory Device Ready. External Device Request for EMI Interface (negative assertion). Enable for External ROM (negative assertion). EROM Type Control: If 0, asynchronous SRAM mode. If 1, synchronous SRAM mode. Read/Write, Bit 0 (negative assertion). Read/Write, Bit 1 (negative assertion). External Segment Address, Bits 3--0. External Memory Bus Size Control: If 0, 16-bit external interface. If 1, 32-bit external interface. External Boot-up Control for CORE0. External Data Bus Mode Configuration Pin. External Interrupt Requests 3--0. BIO0 Status/Control, Bits 6--0. BIO1 Status/Control, Bits 6--0. PIU Address, Bits 3--0. PIU Chip Select (negative assertion). PIU Data Bus, Bits 15--0. O I O PIU Input Buffer Full Flag. PIU Input Data Strobe. PIU Interrupt Request to Host. PIBF PIDS PINT 8 O O I I Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 5 Ball Grid Array Information (continued) 5.1 208-Ball PBGA Package (continued) Table 2. 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol (continued) Symbol POBE PODS PRDY PRDYMD PRWN RSTN SCK0 SCK1 SICK0 SICK1 SID0 SID1 SIFS0 SIFS1 SOCK0 SOCK1 SOD0 SOD1 SOFS0 SOFS1 TCK0 TCK1 TDI0 TDI1 TDO0 TDO1 TMS0 TMS1 TRAP TRST0N 208-Ball PBGA Coordinate P9 R10 N10 T10 R11 H4 M4 M14 K1 P16 M3 M13 K2 N15 L1 M15 M1 L15 L2 M16 F4 L13 G1 K16 F1 L16 G2 K15 J4 F3 Type O I O I I I I I I/O I/O I I I/O I/O I/O I/O O/Z O/Z I/O I/O I I I I O O I I I/O I TRST1N L14 I VDD1 A9, B2, B15, C6, D4, D13, F14, J15, L3, N4, N13, P11, R2, R8, R15 H1 A1, A16, C13, D3, D6, F13, G3, K14, L4, N11, N14, P4, P7, T1, T16, C10 A13, A8, B5, D1, D10, E15, G7, G8, G9, G10, G4, H7, H8, H9, H10, H16, J1, J7, J8, J9, J10, K7, K8, K9, K10, K13, M2, N7, N16, R12, T2, T4, T9 H3 P Description PIU Output Buffer Empty Flag. PIU Output Data Strobe. PIU Host Ready. PRDY Mode. PIU Read/Write (negative assertion). Device Reset (negative assertion). External Clock for SIU0 Active Generator. External Clock for SIU1 Active Generator. SIU0 Input Clock. SIU1 Input Clock. SIU0 Input Data. SIU1 Input Data. SIU0 Input Frame Sync. SIU1 Input Frame Sync. SIU0 Output Clock. SIU1 Output Clock. SIU0 Output Data. SIU1 Output Data. SIU0 Output Frame Sync. SIU1 Output Frame Sync. JTAG Test Clock for CORE0. JTAG Test Clock for CORE1. JTAG Test Data Input for CORE0. JTAG Test Data Input for CORE1. JTAG Test Data Output for CORE0. JTAG Test Data Output for CORE1. JTAG Test Mode Select for CORE0. JTAG Test Mode Select for CORE1. TRAP/Breakpoint Indication. JTAG TAP Controller Reset for CORE0 (negative assertion). JTAG TAP Controller Reset for CORE1 (negative assertion). Power Supply for Internal Circuitry. P P Power Supply for PLL Circuitry. Power Supply for External Circuitry (I/O). G Ground. G Ground for PLL Circuitry. VDD1A VDD2 VSS VSS1A Agere Systems Inc. 9 Data Addendum May 2001 DSP16410C Digital Signal Processor 5 Ball Grid Array Information (continued) 5.2 256-Ball EBGA Package Figure 2 illustrates the ball assignment for the 256-ball EBGA package. This view is from the top of the package. The ball assignment for the DSP16410C is compatible with that of the DSP16410B. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A VSS VDD2 EION ERWN1 VSS VSS VDD2 ED27 ED25 ED23 VDD2 VSS VSS ED15 VDD2 VSS ED9 ED5 VDD2 VSS A B VDD2 VSS EA2 ERAMN ERWN0 ED30 NC ED28 ED26 ED22 ED20 ED18 ED17 ED14 NC ED11 ED7 VDD1 VSS VDD2 B C EA4 EA3 VSS EA1 VDD1 EACKN VDD1 ED29 VDD1 VDD1 ED21 ED19 ED16 ED13 ED12 ED8 NC VSS ED4 ED1 C D EA8 EA6 VDD1 NC EA0 EROMN ED31 VDD2 VDD1 ED24 VDD2 VDD1 VDD1 VDD2 ED10 ED6 NC ED3 ED0 EREQN D E VSS EA10 EA7 EA5 ED2 VDD1 ESIZE VSS E F VDD2 NC EA11 EA9 ERDY EXM TDO0 VSS F G VDD1 EA13 EA12 VDD2 ERTYPE VDD1 NC VDD2 G H VSS EA16 EA15 EA14 VDD2 TRST0N TCK0 TMS0 H J VSS VDD1 EA18 EA17 TDI0 VDD1A CKI VSS1A J K VDD2 ESEG0 NC VDD2 RSTN INT3 VDD1 TRAP K L ESEG2 ESEG1 VDD1 ESEG3 VDD2 INT2 INT1 VDD2 L M ECKO TDI1 VDD1 VDD1 SICK0 INT0 SIFS0 VSS M N TMS1 TCK1 TRST1N VDD2 SOFS0 SOCK0 VDD1 VSS N P VDD2 NC VDD1 SOD1 VDD2 SOD0 SID0 SCK0 P R VSS TDO1 SID1 SOCK1 NC VDD2 R T VSS SCK1 VDD1 IO1BIT0 VSS T U SOFS1 SIFS1 IO1BIT1 NC IO1BIT4 PADD1 VDD2 VDD1 VDD1 VDD2 PD2 VDD1 VDD2 PD9 V SICK1 IO1BIT2 VSS NC IO1BIT6 PADD3 PCSN PODS PRDY POBE VDD1 VDD1 PD7 W VDD2 VSS VDD1 PINT PIBF PD0 PD4 Y VSS VDD2 1 2 VDD1 IO1BIT5 PADD2 IO1BIT3 PADD0 3 IO0BIT4 IO0BIT6 4 NC PRWN PRDYMD IO0BIT2 IO0BIT5 IO0BIT1 IO0BIT3 U PD13 EYMODE NC NC VDD1 PD10 VDD1 VSS VSS NC NC V PD6 NC PD8 PD11 PD14 IO0BIT0 VSS VDD2 W Y VSS VDD2 PIDS VSS VSS VDD2 PD1 PD3 PD5 VDD2 VSS VSS PD12 PD15 VDD2 VSS 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 2. 256-Ball EBGA Package Ball Grid Array Assignments (See-Through Top View) 10 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 5 Ball Grid Array Information (continued) 5.2 256-Ball EBGA Package (continued) Table 3 describes the EBGA ball assignments sorted by symbol for the 256-ball package. For each signal or power/ground connection, this table lists the EBGA coordinate, the symbol name, the type (I = input, O = output, I/O = input/output, O/Z = 3-state output, P = power, G = ground), and description. Inputs and bidirectional pins do not maintain full CMOS levels when not driven. They must be pulled to VDD2 or VSS through the appropriate pull up/down resistor (refer to Section 7.1). An unused external SEMI data bus (ED[31:0]) can be statically configured as outputs by asserting the EYMODE pin. At full CMOS levels, no significant dc current is drawn. Table 3. 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol Symbol CKI EA[18:0] EACKN ECKO ED[31:0] EION ERAMN ERDY EREQN EROMN ERTYPE ERWN0 ERWN1 ESEG[3:0] ESIZE EXM EYMODE INT[3:0] IO0BIT[6:0] IO1BIT[6:0] PADD[3:0] PCSN PD[15:0] PIBF PIDS PBGA Type Description Coordinate J19 I External Clock Input. B3, C1, C2, C4, D1, D2, D5, E2, E3, E4, F3, O External Address Bus, Bits 18--0. F4, G2, G3, H2, H3, H4, J3, J4 C6 O External Device Acknowledge for External Memory Interface (negative assertion). M1 O Programmable Clock Output. A8, A9, A10, A14, A17, A18, B6, B8, B9, I/O External Memory Data Bus, Bits 31--0. B10, B11, B12, B13, B14, B16, B17, C8, C11, C12, C13, C14, C15, C16, C19, C20, D7, D10, D15, D16, D18, D19, E17 A3 O Enable for External I/O (negative assertion). B4 O External RAM Enable (negative assertion). F17 I External Memory Device Ready. D20 I External Device Request for EMI Interface (negative assertion). D6 O Enable for External ROM (negative assertion). G17 I EROM Type Control: If 0, asynchronous SRAM mode. If 1, synchronous SRAM mode. B5 O Read/Write, Bit 0 (negative assertion). A4 O Read/Write, Bit 1 (negative assertion). K2, L1, L2, L4 O External Segment Address, Bits 3--0. E19 I External Memory Bus Size Control: If 0, 16-bit external interface. If 1, 32-bit external interface. F18 I External Boot-up Control for CORE0. U16 I External Data Bus Mode Configuration Pin. K18, L18, L19, M18 I External Interrupt Requests 3--0. R17, R18, T18, T19, U19, U20, W18 I/O BIO0 Status/Control, Bits 6--0. T4, U3, U5, V2, V5, W4, Y3 I/O BIO1 Status/Control, Bits 6--0. U6, V6, W5, Y4 I PIU Address, Bits 3--0. V7 I PIU Chip Select (negative assertion). U11, U14, U15, V13, V15, W11, W12, W13, I/O PIU Data Bus, Bits 15--0. W15, W16, W17, Y11, Y12, Y13, Y17, Y18 W10 O PIU Input Buffer Full Flag. Y7 I PIU Input Data Strobe. PINT Agere Systems Inc. W9 O PIU Interrupt Request To Host. 11 Data Addendum May 2001 DSP16410C Digital Signal Processor 5 Ball Grid Array Information (continued) 5.2 256-Ball EBGA Package (continued) Table 3. 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol (continued) Symbol PBGA Coordinate Type Description POBE V10 O PIU Output Buffer Empty Flag. PODS V8 I PIU Output Data Strobe. PRDY V9 O PIU Host Ready. PRDYMD W8 I PRDY Mode. PRWN W7 I PIU Read/Write (negative assertion). RSTN K17 I Device Reset (negative assertion). SCK0 P20 I External Clock for SIU0 Active Generator. SCK1 T2 I External Clock for SIU1 Active Generator. SICK0 M17 I/O SIU0 Input Clock. SICK1 V1 I/O SIU1 Input Clock. SID0 P19 I SIU0 Input Data. SID1 R3 I SIU1 Input Data. SIFS0 M19 I/O SIFS1 U2 I/O SIU1 Input Frame Sync. SOCK0 N18 I/O SIU0 Output Clock. SOCK1 R4 I/O SIU1 Output Clock. SOD0 P18 O/Z SIU0 Output Data. SOD1 P4 O/Z SIU1 Output Data. SOFS0 N17 I/O SIU0 Output Frame Sync. SOFS1 U1 I/O SIU1 Output Frame Sync. TCK0 H19 I JTAG Test Clock for CORE0. TCK1 N2 I JTAG Test Clock for CORE1. TDI0 J17 I JTAG Test Data Input for CORE0. TDI1 M2 I JTAG Test Data Input for CORE1. TDO0 F19 O JTAG Test Data Output for CORE0. TDO1 TMS0 TMS1 TRAP TRST0N R2 H20 N1 K20 H18 O I I I/O I TRST1N N3 I VDD1 B18, C5, C7, C9, C10, D3, D9, D12, D13, E18, G1, G18, J2, K19, L3, M3, M4, N19, P3, T3, T17, U8, U9, U12, V11, V12, V14, V16, W3 J18 A2, A7, A11, A15, A19, B1, B20, D8, D11, D14, F1, G4, G20, H17, K1, K4, L17, L20, N4, P1, P17, R20, U7, U10, U13, W1, W20, Y2, Y6, Y10, Y14, Y19 P JTAG Test Data Output for CORE1. JTAG Test Mode Select for CORE0. JTAG Test Mode Select for CORE1. TRAP/Breakpoint Indication. JTAG TAP Controller Reset for CORE0 (negative assertion). JTAG TAP Controller Reset for CORE1 (negative assertion). Power Supply for Internal Circuitry. P P Power Supply for PLL Circuitry. Power Supply for External Circuitry (I/O). VDD1A VDD2 12 SIU0 Input Frame Sync. Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 5 Ball Grid Array Information (continued) 5.2 256-Ball EBGA Package (continued) Table 3. 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol (continued) Symbol VSS VSS1A NC PBGA Coordinate A1, A5, A6, A12, A13, A16, A20, B2, B19, C3, C18, E1, E20, F20, H1, J1, M20, N20, R1, T1, T20, V3, V17, V18, W2, W19, Y1, Y5, Y8, Y9, Y15, Y16, Y20 J20 B7, B15, C17, D4, D17, F2, G19, K3, P2, R19, U4, U17, U18, V4, V19, V20, W6, W14 Type G G -- Description Ground. Ground for PLL Circuitry. Not Connected. Tie externally to ground. 6 Device Characteristics 6.1 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. External leads can be bonded and soldered safely at temperatures of up to 220 C. Table 4. Absolute Maximum Ratings for Supply Pins Parameter Voltage on VDD1 with Respect to Ground Voltage on VDD1A with Respect to Ground Voltage on VDD2 with Respect to Ground Voltage Range on Any Signal Pin Junction Temperature (TJ) Storage Temperature Range Min -0.5 -0.5 -0.5 VSS - 0.3 -40 -40 Max 1.8 1.8 4.0 VDD2 + 0.3 4.0 125 150 Unit V V V V C C 6.2 Handling Precautions All MOS devices must be handled with certain precautions to avoid damage due to the accumulation of static charge. Although input protection circuitry has been incorporated into the devices to minimize the effect of this static buildup, proper precautions should be taken to avoid exposure to electrostatic discharge during handling and mounting. Agere Systems Inc. employs a human-body model for ESD-susceptibility testing. Since the failure voltage of electronic devices is dependent on the current, voltage, and hence, the resistance and capacitance, it is important that standard values be employed to establish a reference by which to compare test data. Values of 100 pF and 1500 are the most common and are the values used in the Agere human-body model test circuit. The breakdown voltage for the DSP16410C is greater than 1000 V. Agere Systems Inc. 13 Data Addendum May 2001 DSP16410C Digital Signal Processor 6 Device Characteristics (continued) 6.3 Recommended Operating Conditions Table 5. Recommended Operating Conditions Maximum Internal Clock (CLK) Frequency Minimum Internal Clock (CLK) Period T 200 MHz 5.0 ns Junction Temperature TJ (C) Min Max -40 120 Supply Voltage VDD1, VDD1A (V) Min Max 1.5 1.65 Supply Voltage VDD2 (V) Min Max 3.0 3.6 The ratio of the instruction cycle rate to the input clock frequency is 1:1 without the PLL and ((M + 2)/((D + 2) * f(OD))):1 with the PLL selected. The maximum input clock (CKI pin) frequency when the PLL is not selected as the device clock source is 50 MHz. The maximum input clock frequency is 40 MHz when the PLL is selected. 6.3.1 Package Thermal Considerations The maximum allowable ambient temperature, TAMAX, is dependent upon the device power dissipation and is determined by the following equation: TAMAX = TJMAX - PMAX x JA Where PMAX is the maximum device power dissipation for the application, TJMAX is the maximum device junction temperature specified in Table 6, and JA is the maximum thermal resistance in still-air-ambient specified in Table 6. See Section 7.3 for information on determining the maximum device power dissipation. Table 6. Package Thermal Considerations Device Package Parameter Value Unit 208 PBGA Maximum Junction Temperature (TJMAX) 120 C 208 PBGA Maximum Thermal Resistance in Still-Air-Ambient (JA) 27 C/W 256 EBGA Maximum Junction Temperature (TJMAX) 120 C 256 EBGA Maximum Thermal Resistance in Still-Air-Ambient (JA) 15 C/W WARNING: Due to package thermal constraints, proper precautions in the user's application should be taken to avoid exceeding the maximum junction temperature of 120 C. Otherwise, the device performance and reliability is adversely affected. 14 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 7 Electrical Characteristics and Requirements Electrical characteristics refer to the behavior of the device under specified conditions. Electrical requirements refer to conditions imposed on the user for proper operation of the device. The parameters in Table 7 are valid for the conditions described in Section 6.3, on page 14. Table 7. Electrical Characteristics and Requirements Parameter Symbol Min Max Unit VIL VIH -0.3 0.7 x VDD2 0.3 x VDD2 VDD2 + 0.3 V V Input Current (except TMS0, TMS1, TDI0, TDI1, TRST0N, TRST1N): Low (VIL = 0 V, VDD2 = 3.6 V) High (VIH = 3.6 V, VDD2 = 3.6 V) IIL IIH -5 -- -- 5 A A Input Current (TMS0, TMS1, TDI0, TDI1, TRST0N, TRST1N): Low (VIL = 0 V, VDD2 = 3.6 V) High (VIH = 3.6 V, VDD2 = 3.6 V) IIL IIH -100 -- -- 5 A A Output Low Voltage: Low (IOL = 2.0 mA) Low (IOL = 50 A) VOL VOL -- -- 0.4 0.2 V V Output High Voltage: High (IOH = -2.0 mA) High (IOH = -50 A) VOH VOH VDD2 - 0.7 VDD2 - 0.2 -- -- V V Output 3-State Current: Low (VDD2 = 3.6 V, VIL = 0 V) High (VDD2 = 3.6 V, VIH = 3.6 V) IOZL IOZH -10 -- -- 10 A A CI -- 5 pF Input Voltage: Low High Input Capacitance Agere Systems Inc. 15 Data Addendum May 2001 DSP16410C Digital Signal Processor 7 Electrical Characteristics and Requirements (continued) VDD VOH (V) VDD - 0.1 DEVICE UNDER TEST VDD - 0.2 IOH VDD - 0.3 VDD - 0.4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IOH (mA) 5-4007(C).a Figure 3. Plot of VOH vs. IOH Under Typical Operating Conditions 0.4 VOL (V) 0.3 DEVICE UNDER TEST 0.2 VOL IOL 0.1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IOL (mA) 5-4008(C).b Figure 4. Plot of VOL vs. IOL Under Typical Operating Conditions 16 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 7 Electrical Characteristics and Requirements (continued) 7.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs The DSP16410C does not include any internal circuitry to maintain valid logic levels on input pins or on bidirectional pins that are not driven. For correct device operation and low static power dissipation, valid CMOS levels must be applied to all input and bidirectional pins. Failure to ensure full CMOS levels (VIL or VIH) on pins that are not driven (including floating data busses) may result in high static power consumption and possible device failure. Any unused input pin must be pulled up to the I/O pin supply (VDD2) or pulled down to VSS according to the functional requirements of the pin. The pin can be pulled up or down directly or through a 10 k resistor. Any unused bidirectional pin statically configured as an input should be pulled to VDD2 or VSS through a 10 k resistor. Any bidirectional pin that is dynamically configured, such as the SEMI or PIU data busses, should be tied to VDD2 or VSS through a pull-up/down resistor that supports the performance of the circuit. The value of the resistor should be selected to avoid exceeding the dc voltage and current characteristics of any device attached to the pin. If the SEMI interface is unused in the system, the EYMODE pin should be connected to VDD2 to force the internal data bus transceivers to always be in the output mode. This avoids the need to add 32 pull-up resistors to ED[31:0]. If the SEMI interface is used in the system, the EYMODE pin must be connected to VSS and pull-up or pull-down resistors must be added to ED[31:0] as described below. The value of the pull-up resistors used on the SEMI data bus depends on the programmed bus width, 32-bit or 16-bit, as determined by the ESIZE pin. It is recommended that any 16-bit peripheral that is connected to the external memory interface of the DSP16410C use the upper 16 bits of the data bus (ED[31:16]). This is required if the external memory interface is configured as a 16-bit interface. For the following configurations, 10 k pull-up or pulldown resistors can be used on the external data bus: 32-bit SEMI with no 16-bit peripherals 32-bit SEMI with 16-bit peripherals connected to ED[31:16] 16-bit interface (ED[31:16] only) If the DSP16410C's external memory interface is configured for 32-bit operation with 16-bit peripherals on the lower half of the external data bus (ED[15:0]), the external data bus (ED[31:0]) should have 2 k pull-up or pulldown resistors to meet the rise or fall time requirements of the DSP16410C*. The different requirements for the size of the pull-up/pull-down resistors arise from the manner in which SEMI treats 16-bit accesses if the interface is configured for 32-bit operation. If configured as a 32-bit interface and a 16-bit read is performed to a device on the upper half of the data bus, the SEMI latches the value on the upper 16 bits internally onto the lower 16 bits. This ensures that the lower half of the data bus sees valid logic levels both in this case and also if the bus is operated as a 16-bit bus. However, if a 16-bit read operation is performed (on a 32-bit bus) to a 16-bit peripheral on the lower 16 bits, no data is latched onto the upper 16 bits, resulting in the upper half of the bus floating. In this case the smaller pull-up resistors ensure the floating data bits transition to a valid logic level fast enough to avoid metastability problems when the inputs are latched by the SEMI. * The 2 k resistor value assumes a bus loading of 30 pF and also ensures IOL is not violated. Agere Systems Inc. 17 Data Addendum May 2001 DSP16410C Digital Signal Processor 7 Electrical Characteristics and Requirements (continued) 7.2 Analog Power Supply Decoupling Bypass and decoupling capacitors (0.01 F, 10 F) should be placed between the analog supply pin (VDD1A) and analog ground (VSS1A). These capacitors should be placed as close to the VDD1A pin as possible. This minimizes ground bounce and supply noise to ensure reliable operation. Refer to Figure 5. VDDA VSSA 10 F 0.1 F VSS1A VDD1A DSP16410C 5-8896.a (F) Figure 5. Analog Supply Bypass and Decoupling Capacitors 18 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 7 Electrical Characteristics and Requirements (continued) 7.3 Power Dissipation The total device power dissipation is comprised of two components: The contribution from the VDD1 and VDD1A supplies, referred to as internal power dissipation. The contribution from the VDD2 supply, referred to as I/O power dissipation. The next two sections specify power dissipation for each component. 7.3.1 Internal Power Dissipation Internal power dissipation is highly dependent on operating voltage, core program activity, internal peripheral activity, and CLK frequency. Table 8 lists the DSP16410C typical internal power dissipation contribution for various conditions. The following conditions are assumed for all cases: VDD1 and VDD1A are both 1.575 V. All memory accesses by the cores and the DMAU are to internal memory. SIU0 and SIU1 are operating at 30 MHz in loopback mode. An external device drives the SICK0--1 and SOCK0--1 input pins at 30 MHz, and SIU0--1 are programmed to select passive input clocks (ICKA field (SCON10[2]) and OCKA field (SCON10[6]) are cleared) and internal loopback (SIOLB field (SCON10[8]) is set). The PLL is enabled and selected as the source of the internal clock, CLK. Table 8 specifies the internal power dissipation for the following values of CLK: 185 MHz and 200 MHz. Table 8. Typical Internal Power Dissipation at 1.575 V Type Low-power Standby Typical Worst Case Condition Core Operation The AWAIT field (alf[15]) is set in both cores. Both cores repetitively execute a 20-tap FIR filter. Both cores execute worst-case instructions with worst-case data patterns. Internal Power Dissipation (W) DMAU Activity The DMAU is operating the MMT4 channel to continuously transfer data. 185 MHz 200 MHz 0.24 0.26 0.76 0.82 The DMAU is operating all six channels (SWT0--3 and MMT4--5) to continuously transfer data. 1.37 1.48 To optimize execution speed, the cores each execute the inner loop of the filter from cache and perform a double-word data access every cycle from separate modules of TPRAM. This is an artificial condition that is unlikely to occur for an extended period of time in an actual application because the cores are not performing any I/O servicing. In an actual application, the cores perform I/O servicing that changes program flow and lowers the power dissipation. The internal power dissipation for the low-power standby and typical operating modes described in Table 8 is representative of actual applications. The worst-case internal power dissipation occurs under an artificial condition that is unlikely to occur for an extended period of time in an actual application. This worst-case power should be used for the calculation of maximum ambient operating temperature (TAMAX) defined in Section 6.3.1. This value should also be used for worst-case system power supply design for VDD1 and VDD1A. Agere Systems Inc. 19 Data Addendum May 2001 DSP16410C Digital Signal Processor 7 Electrical Characteristics and Requirements (continued) 7.3 Power Dissipation (continued) 7.3.2 I/O Power Dissipation I/O power dissipation is highly dependent on operating voltage, I/O loading, and I/O signal frequency. It can be estimated as: C L V DD2 2 f where CL is the load capacitance, VDD2 is the I/O supply voltage, and f is the frequency of output signal. Table 9 lists the estimated typical I/O power dissipation contribution for each output and I/O pin for a typical application under specific conditions. The following conditions are assumed for all cases: VDD2 is 3.3 V. The load capacitance for each output and I/O pin is 30 pF. For applications with values of CL, VDD2, or f that differ from those assumed for Table 9, the above formula can be used to adjust the I/O power dissipation values in the table. Table 9. Typical I/O Power Dissipation at 3.3 V Internal Peripheral Pin(s) Type No. of Pins Signal Frequency (MHz) SEMI ED[31:0] I/O 32 CLK/4 ERWN[1:0] O 2 CLK/4 242 15 261 16.2 EA0 O 1 CLK/8 7.6 8.1 EA[18:1] O 18 CLK/4 273 294 ESEG[3:0] O 4 CLK/4 EROMN O 1 CLK/12 60 5.1 65.9 5.4 ERAMN O 1 CLK/12 5.1 5.4 EION O 1 CLK/12 5.4 32 BIO0--1 PIU SIU0--1 I/O Power Dissipation (mW) 185 MHz 200 MHz ECKO O 1 CLK/2 5.1 30.2 IO0--1BIT[6:0] O 14 1 4.6 4.6 PD[15:0] I/O 16 30 78.5 78.5 PINT O 1 1 0.33 0.33 PIBF O 1 30 9.8 9.8 POBE O 1 30 9.8 9.8 PRDY O 1 30 9.8 9.8 SICK0--1 O 2 8 5.2 5.2 SOCK0--1 O 2 8 5.2 5.2 SOD0--1 O 2 8 5.2 5.2 SIFS0--1 O 2 0.03 0.019 0.019 SOFS0--1 O 2 0.03 0.019 0.019 Assumptions: the SEMI is configured for a 32-bit external data bus (the ESIZE pin is high). The contribution from the EACKN pin is negligible. Assumption: the pins switch from input to output at a 50% duty cycle. Assumption: the corresponding core has configured these pins as outputs. 20 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 7 Electrical Characteristics and Requirements (continued) 7.3 Power Dissipation (continued) 7.3.2 I/O Power Dissipation (continued) Power dissipation due to the input buffers is highly dependent upon the input voltage level. At full CMOS levels, essentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the threshold of VDD2/2, high current can flow. See Section 7.1 for more information. WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high currents might flow. 7.4 Power Supply Sequencing Issues The DSP16410B requires two supply voltages. The use of dual voltages reduces internal device power consumption while supporting standard 3.3 V external interfaces. The external (I/O) power supply voltage is VDD2, the internal supply voltage is VDD1, and the internal analog supply voltage is VDD1A. VDD1 and VDD1A are typically generated by the same power supply, with VDD1A receiving enhanced filtering near the device. In the discussion that follows, VDD1 and VDD1A are assumed to rise and fall together, and are collectively referred to as VDD1 throughout the remainder of this section. Power supply design is a system issue. Section 7.4.1 describes the recommended power supply sequencing specifications to avoid inducing latch-up or large currents that may reduce the long term life of the device. Section 7.4.2 discusses external power sequence protection circuits that may be used to meet the recommendations discussed in Section 7.4.1. 7.4.1 Supply Sequencing Recommendations Control of powerup and powerdown sequences is recommended to address the following key issues. See Figure 6 and Table 10, on page 22 for definitions of the terms VSEP, TSEPU, and TSEPD. 1. If the internal supply voltage (VDD1) exceeds the external supply voltage (VDD2) by a specified amount, large currents may flow through on-chip ESD structures that may reduce the long term life of the device or induce latch-up. The difference between the internal and external supply voltages is defined as VSEP. It is recommended that the value of VSEP specified in Table 10 be met during device powerup and device powerdown. External components may be required to ensure this specification is met (see Section 7.4.2). 2. During powerup, if the external supply voltage (VDD2) exceeds a specified voltage (1.2 V) and the internal supply voltage (VDD1) does not reach a specified voltage (0.6 V) within a specified time interval (TSEPU), large currents may flow through the I/O buffer transistors. This is because the I/O buffer transistors are powered by VDD2 but their control transistors powered by VDD1 are not at valid logic levels. If the requirement for TSEPU cannot be met, external components are recommended (see Section 7.4.2). 3. During powerdown, if the internal supply voltage (VDD1) falls below a specified voltage (0.6 V) and the external supply voltage (VDD2) does not fall below a specified voltage (1.2 V) within a specified time interval (TSEPD), large currents may flow through the I/O buffer transistors. This is because the control transistors (powered by VDD1) for the I/O buffer transistors are no longer at valid logic levels while the I/O buffer transistors remain powered by VDD2. If the requirement for TSEPD cannot be met, external components are recommended (see Section 7.4.2). Agere Systems Inc. 21 Data Addendum May 2001 DSP16410C Digital Signal Processor 7 Electrical Characteristics and Requirements (continued) 7.4 Power Supply Sequencing Issues (continued) 7.4.1 Supply Sequencing Recommendations (continued) VDD2 (EXTERNAL SUPPLY) dc POWER SUPPLY VOLTAGE 3V VDD1 (INTERNAL) 2V VSEP VSEP 1.2 V 1V TSEPU TSEPD 0.6 V TIME 0930 (F) Figure 6. Power Supply Sequencing Recommendations Table 10. Power Sequencing Recommendations 22 Parameter Value Description VSEP -0.6 V < VSEP TSEPU 0 TSEPU < 50 ms TSEPD 0 TSEPD < 100 ms Difference between VDD2 and VDD1 supplies. VSEP = VDD2 - VDD1. VSEP constraint must be satisfied for the entire duration of power-on and power-off supply ramp. Time after VDD2 supply reaches 1.2 V and before VDD1 supplies reach 0.6 V. Time after VDD1 supplies reach 0.6 V and before VDD2 reaches 1.2 V. Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 7 Electrical Characteristics and Requirements (continued) 7.4 Power Supply Sequencing Issues (continued) 7.4.2 External Power Sequence Protection Circuits This section discusses external power sequence protection circuits which may be used to meet the recommendations discussed in Section 7.4.1. For the purpose of this discussion, the dual supply configuration of Figure 7 will be used. The recommendations for this series supply system apply to parallel supply configurations where a common power bus simultaneously controls both the internal and external supplies. VDD2 D1 2.4 V SYSTEM POWER BUS DSP1640C D0 EXTERNAL POWER REGULATOR INTERNAL POWER REGULATOR VDD1 1563.a(F) Figure 7. Power Supply Example Figure 7 illustrates a typical supply configuration. The external power regulator provides power to the internal power regulator. Use of schottky diode D1 to bootstrap the VDD2 supply from the VDD1 supply is recommended. D1 ensures that the VSEP recommendation is met during device powerdown and powerup. In addition, D1 protects the DSP16410C from damage in the event of an external power regulator failure. Diode network D0, which may be a series of diodes or a single zener diode, bootstraps the VDD1 supply. After VDD2 is a fixed voltage above VDD1 (2.4 V as determined by D0), the VDD2 supply will power VDD1 until D0 is cut off as VDD1 achieves its operating voltage. If TSEPU/TSEPD recommendations are met, D0 is not required. Since D0 protects the DSP16410C from damage in the event of an internal supply failure and reduces TSEPU, use of D0 is recommended. To ensure D0 cutoff during normal system operation, D0's forward voltage (VF) should be 2.4 V. D0 should be selected to ensure a minimum VDD1 of 0.8 V under DSP load. Agere Systems Inc. 23 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements Timing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions imposed on the user for proper operation of the device. All timing data is valid for the following conditions: TJ = -40 C to +120 C (See Section 6.3, on page 14). VDD2 = 3.3 V 0.3 V, VSS = 0 V (See Section 6.3, on page 14). Capacitance load on outputs (CL) = 30 pF. Output characteristics can be derated as a function of load capacitance (CL). All outputs: 0.025 ns/pF dt/dCL 0.07 ns/pF for 10 CL 100 pF. For example, if the actual load capacitance on an output pin is 20 pF instead of 30 pF, the maximum derating for a rising edge is (20 - 30) pF x 0.07 ns/pF = 0.7 ns less than the specified rise time or delay that includes a rise time. The minimum derating for the same 20 pF load would be (20 - 30) pF x 0.025 ns/pF = 0.25 ns. Test conditions for inputs: Rise and fall times of 4 ns or less. Timing reference levels for CKI, RSTN, TRST0N, TRST1N, TCK0, and TCK1 are VIH and VIL. Timing reference level for all other inputs is VM. (See Table 11.) Test conditions for outputs (unless noted otherwise): CLOAD = 30 pF. Timing reference levels for ECKO are VOH and VOL. Timing reference level for all other outputs is VM. 3-state delays measured to the high-impedance state of the output driver. Unless otherwise noted, ECKO in the timing diagrams is the free-running CLK (ECON1[1:0] = 1). VM - 5-8215 (F) Figure 8. Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs Table 11. Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs Abbreviated Reference Parameter VM Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs 24 Value 1.5 Unit V Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.1 Phase-Lock Loop Table 12. PLL Requirements Parameter VCO Frequency Range (VDD1A = 1.575 V) Input Jitter at CKI PLL Lock Time CKI Frequency with PLL Enabled CKI Frequency with PLL Disabled fCKI/(D + 2) Symbol fVCO Min Max 200 500 Unit MHz -- tL -- -- 6 0 3 200 0.5 40 50 20 ps-rms ms MHz MHz MHz fCKI fCKI -- D is the PLL input divider and is defined by pllfrq[13:9]. 8.2 Wake-Up Latency Table 13 specifies the wake-up latency for the low-power standby mode. The wake-up latency is the delay between exiting low-power standby mode and resumption of normal execution. Table 13. Wake-Up Latency Condition Wake-Up Latency Low-power Standby Mode (AWAIT (alf[15]) = 1) (PLL Deselected During Normal Execution) (PLL Enabled and Selected During Normal Execution) PLL Disabled During Standby 3T 3T + tL PLL Enabled During Standby 3T 3T The PLL is deselected if the PLLSEL field (pllcon[0]) is cleared, which is the default after reset. The PLL is selected if the PLLSEL field (pllcon[0]) is set. The PLL is disabled (powered down) if the PLLEN field (pllcon[1]) is cleared, which is the default after reset. The PLL is enabled (powered up) if the PLLEN field (pllcon[1]) is set. T = CLK clock cycle (fCLK = fCKI if PLL deselected; fCLK = fCKI * ((M + 2)/((D + 2) * f(OD))) if PLL enabled and selected). tL = PLL lock-in time (see Table 12). Agere Systems Inc. 25 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.3 DSP Clock Generation t1 t3 t2 VIH- CKI VIL- t5 t4 ECKO VOH- VOL- t6 5-4009(F).i Figure 9. I/O Clock Timing Diagram Table 14. Timing Requirements for Input Clock Abbreviated Reference Parameter Min Max Unit ns Clock In Period (high to high) 20 -- t2 Clock In Low Time (low to high) 10 -- ns t3 Clock In High Time (high to low) 10 -- ns t1 For timing requirements shown, it is assumed that CKI (not the PLL output) is selected as internal clock source. If the PLL is selected as the internal clock source, the minimum required CKI period is 25 ns and the maximum required CKI period is 167 ns. Device is fully static, t1 is tested at 100 ns input clock option, and memory hold time is tested at 0.1 s. Table 15. Timing Characteristics for Input Clock and Output Clock Abbreviated Reference Parameter Min Max Unit t4 Clock Out High Delay (low to low) -- 10 ns t5 Clock Out Low Delay (high to high) -- 10 ns Clock Out Period (high to high) T -- ns t6 T = internal clock period (CLK). 26 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.4 Reset Circuit The DSP16410C has three external reset pins: RSTN, TRST0N, TRST1N. At initial powerup or if any supply voltage (VDD1, VDD1A, or VDD2) falls below VDD MIN*, a device reset is required and RSTN, TRST0N, TRST1N must be asserted simultaneously to initialize the device. Note: The TRST0N and TRST1N pins must be asserted even if the JTAG controller is not used by the application. VDD MIN VDD1, VDD1A RAMP t146 t153 t8 RSTN, TRST0N, TRST1N VIH VIL t10 t11 OUTPUT VOH PINS VOL CKI 5-4010(F).r When both INT0 and RSTN are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state condition. With RSTN asserted and INT0 not asserted, EION, ERAMN, EROMN, EACKN, ERWN0, and ERWN1 outputs are driven high. EA[18:0], ESEG[3:0], and ECKO are driven low. Figure 10. Powerup and Device Reset Timing Diagram Table 16. Timing Requirements for Powerup and Device Reset Abbreviated Reference t8 Parameter RSTN, TRST0N, and TRST1N Reset Pulse (low to high) t146 VDD1, VDD1A MIN to RSTN, TRST0N, and TRST1N Low t153 RSTN, TRST0N, and TRST1N Rise (low to high) Min Max Unit 7T 2T -- -- ns -- ns 60 ns T = internal clock period (CKI). Table 17. Timing Characteristics for Device Reset Abbreviated Reference Parameter Min Max Unit 50 50 ns t10 RSTN Disable Time (low to 3-state) -- t11 RSTN Enable Time (high to valid) -- ns Note: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high currents may flow. * See Table 5 on page 14. Agere Systems Inc. 27 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.5 Reset Synchronization t24 CKI VIH- VIL- t126 RSTN VIH- VIL- FETCH OF FIRST INSTRUCTION BEGINS EROMN (EXM = 1) 5-4011(F).i Note: See Section 8.9 for timing characteristics of the EROMN pin. Figure 11. Reset Synchronization Timing Table 18. Timing Requirements for Reset Synchronization Timing Abbreviated Reference Parameter t126 Reset Setup (high to high) t24 CKI to Enable Valid Min 3 4T + 0.5 Max T/2 - 1 4T + 4 Unit ns ns T = internal clock period (CKI). 28 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.6 JTAG t12 t155 t13 t14 VIH VIL TCK0, TCK1 t15 t156 t16 TMS0, TMS1 VIH VIL t17 t18 VIH TDI0, TDI1 VIL t19 t20 TDO0, TD01 VOH VOL 5-4017(F).d Figure 12. JTAG I/O Timing Diagram Table 19. Timing Requirements for JTAG I/O Abbreviated Reference t12 t13 t14 t155 t156 t15 t16 t17 t18 Parameter TCK Period (high to high) TCK High Time (high to low) TCK Low Time (low to high) TCK Rise Transition Time (low to high) TCK Fall Transition Time (high to low) TMS Setup Time (valid to high) TMS Hold Time (high to invalid) TDI Setup Time (valid to high) TDI Hold Time (high to invalid) Min 50 22.5 22.5 0.6 0.6 7.5 5 7.5 5 Max -- -- -- -- -- -- -- -- -- Unit ns ns ns V/ns V/ns ns ns ns ns Min -- 0 Max 15 -- Unit ns ns Table 20. Timing Characteristics for JTAG I/O Abbreviated Reference t19 t20 Agere Systems Inc. Parameter TDO Delay (low to valid) TDO Hold (low to invalid) 29 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.7 Interrupt and Trap VOH- ECKO VOL- t21 INT t22 5-4018(F).g ECKO is free-running. INT is one of INT[3:0] or TRAP. Figure 13. Interrupt and Trap Timing Diagram Table 21. Timing Requirements for Interrupt and Trap Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts. Abbreviated Reference t21 t22 Parameter Interrupt Setup (high to low) INT/TRAP Assertion Time (high to low) Min Max Unit 8 -- ns -- ns 2T T = internal clock period (CLK). 30 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.8 Bit I/O t144 VOH- ECKO VOL- t29 IOBIT (OUTPUT) VALID OUTPUT t28 t27 IOBIT (INPUT) DATA INPUT 5-4019(F).c Figure 14. Write Outputs Followed by Read Inputs (cbit = IMMEDIATE; a1 = sbit) Timing Characteristics Table 22. Timing Requirements for BIO Input Read Abbreviated Reference t27 t28 Parameter IOBIT Input Setup Time (valid to low) IOBIT Input Hold Time (low to invalid) Min 10 0 Max -- -- Unit ns ns Min -- 1 Max 9 -- Unit ns ns Table 23. Timing Characteristics for BIO Output Abbreviated Reference t29 t144 Agere Systems Inc. Parameter IOBIT Output Valid Time (high to valid) IOBIT Output Hold Time (high to invalid) 31 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.9 System and External Memory Interface In the following timing diagrams and associated tables: The designation ENABLE refers to one of the following pins: EROMN, ERAMN, or EION. The designation ENABLES refers to all of the following pins: EROMN, ERAMN, and EION. The designation ERWN refers to the following: -- The ERWN0 pin if the external data bus is configured as 16 bits, i.e., if the ESIZE pin is logic low. -- The ERWN1 and ERWN0 pins if the external data bus is configured as 32 bits, i.e., if the ESIZE pin is logic high. -- The ERWN1, ERWN0, and EA0 pins if the external data bus is configured as 32 bits, i.e., if the ESIZE pin is logic high, and if the memory access is synchronous. The designation EA refers to the following: -- The external address pins EA[18:0] and the external segment address pins ESEG[3:0] if the external data bus is configured as 16 bits, i.e., if the ESIZE pin is logic low. -- The external address pins EA[18:1] and the external segment address pins ESEG[3:0] if the external data bus is configured as 32 bits, i.e., if the ESIZE pin is logic high. The designation ED refers to the following: -- The external data pins ED[31:16] if the external data bus is configured as 16 bits, i.e., if the ESIZE pin is logic low. -- The external data pins ED[31:0] if the external data bus is configured as 32 bits, i.e., if the ESIZE pin is logic high. The designation ATIME refers to IATIME (ECON0[11:8]) for accesses to the EIO space, YATIME (ECON0[7:4]) for accesses to the ERAM space, or XATIME (ECON0[3:0]) for accesses to the EROM space. VOH- ECKO VOL- t102 t103 ENABLE t112 t113 ERWN ECKO reflects CLK, i.e., ECON1[1:0] = 1. Figure 15. Enable and Write Strobe Transition Timing Table 24. Timing Characteristics for Memory Enables and ERWN Abbreviated Reference t102 t103 t112 t113 32 Parameter ECKO to ENABLE Active (high to low) ECKO to ENABLE Inactive (high to high) ECKO to ERWN Active (high to low) ECKO to ERWN Inactive (high to high) Min Max Unit 0.5 0.5 0.5 0.5 4 4 4 4 ns ns ns ns Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.9 System and External Memory Interface (continued) 8.9.1 Asynchronous Interface ECKO VOH- VOL- t122 EREQN t122 t123 t129 ED t127 EA ENABLES t128 t124 t125 EACKN ECKO reflects CLK, i.e., ECON1[1:0] = 1. Figure 16. Timing Diagram for EREQN and EACKN Table 25. Timing Requirements for EREQN Abbreviated Reference t122 t129 Parameter EREQN Setup (low to high or high to high) EREQN Deassertion (high to low) Min Max Unit 5 -- ns ATIMEMAX -- ns Min Max Unit -- ATIMEMAX = the greatest of IATIME(ECON0[11:8]), YATIME (ECON0[7:4]), and XTIME (ECON0[3:0]}. Table 26. Timing Characteristics for EACKN and SEMI Bus Disable Abbreviated Reference t123 t124 Parameter Memory Bus Disable Delay (high to 3-state) EACKN Assertion Delay (high to low) 6 ns 4T -- ns 4T 4T + 3 ns t125 EACKN Deassertion Delay (high to high) t127 Memory Bus Enable Delay (high to active) 5 -- ns t128 EACKN Delay (high to low) -- 3 ns If any ENABLE is asserted (low) when EREQN is asserted (low), then the delay occurs from the time that ENABLE is deasserted (high). (The SEMI does not acknowledge the request by asserting EACKN until it has completed any pending memory accesses.) T = internal clock period (CLK). Agere Systems Inc. 33 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.9 System and External Memory Interface (continued) 8.9.1 Asynchronous Interface (continued) ATIME = 3 ECKO VOH- VOL- t90 ENABLE t93 t92 ED READ DATA t91 EA READ ADDRESS t95 ERWN ECKO reflects CLK, i.e., ECON1[1:0] = 1. Figure 17. Asynchronous Read Timing Diagram (RHOLD = 0 and RSETUP = 0) Table 27. Timing Requirements for Asynchronous Memory Read Operations Abbreviated Reference Parameter Min Max Unit t92 Read Data Setup (valid to ENABLE high) 5 -- ns t93 Read Data Hold (ENABLE high to invalid) 0 -- ns Max Unit Table 28. Timing Characteristics for Asynchronous Memory Read Operations Abbreviated Reference t90 Parameter ENABLE Width (low to high) t91 Address Delay (ENABLE low to valid) t95 ERWN Activation (ENABLE high to ERWN low) Min (T x ATIME) - 3 -- -- 2 - (T x RSETUP ) ns T x (1 + RHOLD + WSETUP) - 3 -- -- ns T = internal clock period (CLK). RSETUP = ECON0[12]. RHOLD = ECON0[14]. WSETUP = ECON0[13]. Note: The external memory access time from the assertion of ENABLE can be calculated as t90 - (t91 + t92). 34 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.9 System and External Memory Interface (continued) 8.9.1 Asynchronous Interface (continued) STALL ATIME = 2 ATIME = 2 VOH- ECKO VOL- t90 t101 ENABLE t99 t96 ERWN EA WRITE ADDRESS READ ADDRESS t98 t100 t97 ED t114 WRITE DATA READ DATA ECKO reflects CLK, i.e., ECON1[1:0] = 1. The stall cycle is caused by the read following the write. Figure 18. Asynchronous Write Timing Diagram (WHOLD = 0, WSETUP = 0) Table 29. Timing Characteristics for Asynchronous Memory Write Operations Abbreviated Reference t90 Parameter (T x ATIME) - 3 ENABLE Width (low to high) t96 Enable Delay (ERWN high to ENABLE low) t97 Write Data Setup (valid to ENABLE high) t98 Write Data Deactivation (ERWN high to 3-state) t99 Min Write Address Setup (valid to ENABLE low) t100 Write Data Activation (ERWN low to low-Z) t101 Address Hold Time (ENABLE high to invalid) t114 Write Data Hold Time (ENABLE high to invalid) T x (1 + T WHOLD -- ns -- ns -- ns -- 3 ns -- ns WSETUP) T -3 -2 -3 Unit (T x ATIME) - 3 x (1 + + RSETUP) Max -- ns T x (1 + WHOLD ) - 3 -- ns T-3 -- ns T = internal clock period (CLK). WHOLD = ECON0[15]. RSETUP = ECON0[12]. WSETUP = ECON0[13]. Agere Systems Inc. 35 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.9 System and External Memory Interface (continued) 8.9.2 Synchronous Interface VOH- ECKO VOL- t102 t103 ENABLE ERWN EA READ ADDRESS READ ADDRESS WRITE ADDRESS t107 t106 t105 ED READ DATA READ DATA WRITE DATA t104 t108 ECKO reflects CLK/2, i.e., ECON1[1:0] = 0. Figure 19. Synchronous Read Timing Diagram (Read-Read-Write Sequence) Table 30. Timing Requirements for Synchronous Read Operations Abbreviated Parameter Reference t104 Read Data Setup (valid to high) t105 Read Data Hold (high to invalid) Min Max Unit 4 1 -- -- ns ns Min Max Unit Table 31. Timing Characteristics for Synchronous Read Operations Abbreviated Reference Parameter t102 ECKO to ENABLE Active (high to low) 0.5 4 ns t103 ECKO to ENABLE Inactive (high to high) 0.5 4 ns t106 Address Delay (high to valid) -- 2.5 ns t107 Address Hold (high to invalid) 0.5 -- ns Write Data Active (high to low-Z) -- ns t108 T -3 T = internal clock period (CLK). 36 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.9 System and External Memory Interface (continued) 8.9.2 Synchronous Interface (continued) VOH- ECKO VOL- t102 t103 t112 t113 ENABLE ERWN t107 EA ADDRESS t106 t110 t109 ED DATA t111 ECKO reflects CLK/2, i.e., ECON1[1:0] = 0. Figure 20. Synchronous Write Timing Diagram Table 32. Timing Characteristics for Synchronous Write Operations Abbreviated Reference t102 t103 t106 t107 t109 t110 t111 t112 t113 Agere Systems Inc. Parameter ECKO to ENABLE Active (high to low) ECKO to ENABLE Inactive (high to high) Address Delay (high to valid) Address Hold (high to invalid) Write Data Delay (high to valid) Write Data Hold (high to invalid) Write Data Deactivation Delay (high to 3-state) ECKO to ERWN Active (high to low) ECKO to ERWN Inactive (high to high) Min Max Unit 0.5 0.5 -- 0.5 -- 0.5 -- 0.5 0.5 4 4 2.5 -- 2.5 -- 2.5 4 4 ns ns ns ns ns ns ns ns ns 37 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.9 System and External Memory Interface (continued) 8.9.3 ERDY Interface N x T ATIME END OF ACCESS (UNSTALLED) SEMI SAMPLES ERDY PIN END OF ACCESS (STALLED) VOH- ECKO VOL- 4T t121 ENABLE t115 t115 ERDY N x T 4T ECKO reflects CLK, i.e., ECON1[1:0] = 1. ATIME must be programmed as greater than or equal to five CLK cycles. Otherwise, the SEMI ignores the state of ERDY. T = internal clock period (CLK). N must be greater than or equal to one, i.e., ERDY must be held low for at least one CLK cycle after the SEMI samples ERDY. Figure 21. ERDY Pin Timing Diagram As indicated in the drawing, the SEMI: Samples the state of ERDY at 4T prior to the end of the access (unstalled). (The end of the access (unstalled) occurs at ATIME cycles after ENABLE goes low.) Ignores the state of ERDY before the ERDY sample point. Stalls the external memory access by N x T cycles, i.e., by the number of cycles that ERDY is held low following the ERDY sample point. Table 33. Timing Requirements for ERDY Pin Abbreviated Reference t115 t121 38 Parameter Min Max Unit ERDY Setup to any ECKO (low to high or high to high) ERDY Setup to ECKO at End of Unstalled Access (low to high) 5 4T + 5 -- -- ns ns Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.10 PIU t65 t60 t60 PSTRN t61 t62 PADD[3:0] t67 t66 PRWN t63 t64 PD[15:0] t68 PIBF t69 t74 PRDY 5-7850 (F) PSTRN is the logical OR of the PCSN input pin with the exclusive NOR of the PIDS and PODS input pins, i.e., PSTRN = PCSN | (PIDS ^ PODS). It is assumed that the PRDYMD pin is logic low, configuring the PRDY pin as active-low. Figure 22. Host Data Write to PDI Timing Diagram Table 34. Timing Requirements for PIU Data Write Operations Abbreviated Reference t60 t61 t62 t63 t64 t65 t66 t67 t74 Parameter PSTRN Pulse Width (high to low or low to high) PADD Setup Time (valid to low) PADD Hold Time (low to invalid) PD Setup Time (valid to high) PD Hold Time (high to invalid) PSTRN Request Period (low to low) PRWN Setup Time (low to low) PRWN Hold Time (high to high) PSTRN Hold (low to high) Min max (2T, 15) 5 5 6 5 max (5T, 30) 0 0 1 Max -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns T is the period of the internal clock (CLK). Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last. Time to the rising edge of PIDS, PODS, or PCSN, whichever occurs first. Table 35. Timing Characteristics for PIU Data Write Operations Abbreviated Reference t68 t69 Parameter PIBF Delay (high to high) PRDY Delay (low to valid) Min 1 1 Max 12 12 Unit ns ns Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first. Agere Systems Inc. 39 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.10 PIU (continued) t65 t60 t60 PSTRN t61 t62 PADD[3:0] t71 t73 PD[15:0] t70 t72 POBE t69 t74 PRDY 5-7851 (F) PSTRN is the logical OR of the PCSN input pin with the exclusive NOR of the PIDS and PODS input pins, i.e., PSTRN = PCSN | (PIDS ^ PODS). It is assumed that the PRDYMD pin is logic low, configuring the PRDY pin as active-low. Figure 23. Host Data Read from PDO Timing Diagram Table 36. Timing Requirements for PIU Data Read Operations Abbreviated Reference t60 t61 Parameter PSTRN Pulse Width (high to low or low to high) PADD Setup Time Time (valid to low) t62 PADD Hold t65 PSTRN Request Period (low to low) t74 PSTRN Hold (low to high) (low to invalid) Min Max Unit max (2T , 15) -- ns 5 -- ns 5 -- ns max (5T , 30) -- ns 1 -- ns T is the period of the internal clock (CLK). Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last. Table 37. Timing Characteristics for PIU Data Read Operations Abbreviated Reference Parameter Min Max Unit 1 12 ns T ns t69 PRDY Delay (low to valid) t70 POBE, PRDY Delays (valid to low) T-3 t71 PD Activation Delay 1 6 ns t72 POBE Delay (high to high) 1 12 ns 1 12 ns t73 PD Deactivation (low to low-Z) Delay (high to 3-state) Delay from the falling edge of PIDS, PODS, or PCSN, whichever occurs last. Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first. 40 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.10 PIU (continued) t65 t60 t60 PSTRN t61 t62 PADD[3:0] t67 t66 PRWN t63 t64 PD[15:0] t68 PIBF t69 t74 PRDY 5-7850 (F) PSTRN is the logical OR of the PCSN input pin with the exclusive NOR of the PIDS and PODS input pins, i.e., PSTRN = PCSN | (PIDS ^ PODS). It is assumed that the PRDYMD pin is logic low, configuring the PRDY pin as active-low. Figure 24. Host Register Write (PAH, PAL, PCON, or HSCRATCH) Timing Diagram Table 38. Timing Requirements for PIU Register Write Operations Abbreviated Reference t60 t61 Parameter PSTRN Pulse Width (high to low or low to high) PADD Setup Time (valid to low) Min max (2T , 15) 5 Max -- -- Unit ns ns t62 PADD Hold Time (low to invalid) 5 -- ns 6 -- ns 5 max (5T , 30) -- -- ns ns 0 0 1 -- -- 12 ns ns ns t63 PD Setup Time (valid to high) t64 t65 PD Hold Time (high to invalid) PSTRN Request Period (low to low) t66 t67 t74 PRWN Setup Time (low to low) PRWN Hold Time (high to high) PSTRN Hold (low to high) T is the period of the internal clock (CLK). Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last. Time to the rising edge of PIDS, PODS, or PCSN, whichever occurs first. Table 39. Timing Characteristics for PIU Register Write Operations Abbreviated Reference t68 t69 Parameter PIBF (high to high) PRDY Delay (low to valid) Delay Min 1 1 Max 12 12 Unit ns ns Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first. Agere Systems Inc. 41 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.10 PIU (continued) t65 t60 t60 PSTRN t61 t62 PADD[3:0] t75 t71 t73 PD[15:0] 5-7853 (F) PSTRN is the logical OR of the PCSN input pin with the exclusive NOR of the PIDS and PODS input pins, i.e., PSTRN = PCSN | (PIDS ^ PODS). Figure 25. Host Register Read (PAH, PAL, PCON, or DSCRATCH) Timing Diagram Table 40. Timing Requirements for PIU Register Read Operations Abbreviated Reference Parameter Min Max max (2T , 15) Unit -- ns t61 PADD Setup (valid to low) 5 -- ns t62 PADD Hold Time (low to invalid) 5 -- ns -- ns t60 t65 PSTRN Pulse Width (high to low or low to high) Time PSTRN Request Period (low to low) max (5T , 30) T is the period of the internal clock (CLK). Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last. Table 41. Timing Characteristics for PIU Register Read Operations Abbreviated Reference t71 Parameter PD Activation Delay (low to low-Z) Delay t73 PD Deactivation t75 PD Delay (low to valid) (high to 3-state) Min Max Unit 1 6 ns 1 12 ns -- 16 ns Delay from the falling edge of PIDS, PODS, or PCSN, whichever occurs last. Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first. 42 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU t30 t32 t31 SICK t34 t33 SIFS t34 t33 t35 SID B0 B1 B0 B2 t36 5-8033 (F) Note: It is assumed that the SIU is configured with ICKA(SCON10[2]) = 0 for passive mode input clock, ICKK(SCON10[3]) = 0 for no inversion of SICK, IFSA(SCON10[0]) = 0 for passive mode input frame sync, IFSK(SCON10[1]) = 0 for no inversion of SIFS, IMSB(SCON0[2]) = 0 for LSB-first input, and IFSDLY[1:0](SCON1[9:8]) = 00 for no input frame sync delay. Figure 26. SIU Passive Frame and Channel Mode Input Timing Diagram Table 42. Timing Requirements for SIU Passive Frame Mode Input Abbreviated Reference t30 t31 t32 t33 t34 t35 t36 Parameter SICK Bit Clock Period (high to high) SICK Bit Clock High Time (high to low) SICK Bit Clock Low Time (low to high) SIFS Hold Time (high to low or high to high) SIFS Setup Time (low to high or high to high) SID Setup Time (valid to low) SID Hold Time (low to invalid) Min 25 10 10 10 10 5 8 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns Min 61.035 28 28 10 10 5 8 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns Table 43. Timing Requirements for SIU Passive Channel Mode Input Abbreviated Reference t30 t31 t32 t33 t34 t35 t36 Agere Systems Inc. Parameter SICK Bit Clock Period (high to high) SICK Bit Clock High Time (high to low) SICK Bit Clock Low Time (low to high) SIFS Hold Time (high to low or high to high) SIFS Setup Time (low to high or high to high) SID Setup Time (valid to low) SID Hold Time (low to invalid) 43 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU (continued) t37 t39 t38 SOCK t40 t41 SOFS SOD t40 t41 t42 B0 B0 B1 t43 5-8034 (F) Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 0 for passive mode output clock, OCKK(SCON10[7]) = 0 for no inversion of SOCK, OFSA(SCON10[4]) = 0 for passive mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS, OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 for no output frame sync delay. Figure 27. SIU Passive Frame Mode Output Timing Diagram Table 44. Timing Requirements for SIU Passive Frame Mode Output Abbreviated Reference t37 t38 t39 t40 t41 Parameter SOCK Bit Clock Period (high to high) SOCK Bit Clock High Time (high to low) SOCK Bit Clock Low Time (low to high) SOFS Hold Time (high to low or high to high) SOFS Setup Time (low to high or high to high) Min 25 10 10 10 10 Max -- -- -- -- -- Unit ns ns ns ns ns Max 16 4 Unit ns ns Table 45. Timing Characteristics for SIU Passive Frame Mode Output Abbreviated Reference t42 t43 44 Parameter SOD Delay (high to valid) SOD Hold (high to invalid) Min 1 0 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU (continued) t37 t39 t38 SOCK t40 t41 SOFS SOD t40 t41 t42 t44 B0 B0 B1 B1 t43 5-8032 (F) Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 0 for passive mode output clock, OCKK(SCON10[7]) = 0 for no inversion of SOCK, OFSA(SCON10[4]) = 0 for passive mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS, OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 0 for channel mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 for no output frame sync delay. Figure 28. SIU Passive Channel Mode Output Timing Diagram Table 46. Timing Requirements for SIU Passive Channel Mode Output Abbreviated Reference t37 t38 t39 t40 t41 Parameter SOCK Bit Clock Period (high to high) SOCK Bit Clock High Time (high to low) SOCK Bit Clock Low Time (low to high) SOFS Hold Time (high to low or high to high) SOFS Setup Time (low to high or high to high) Min 61.035 28 28 10 10 Max -- -- -- -- -- Unit ns ns ns ns ns Min 1 0 -- Max 16 4 12 Unit ns ns ns Table 47. Timing Characteristics for SIU Passive Channel Mode Output Abbreviated Reference t42 t43 t44 Agere Systems Inc. Parameter SOD Delay (high to valid) SOD Hold (high to invalid) SOD Deactivation Delay (high to 3-state) 45 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU (continued) t52 t53 t54 SCK 5-8037 (F) Figure 29. SCK External Clock Source Input Timing Diagram Table 48. Timing Requirements for SCK External Clock Source Abbreviated Reference t52 t53 t54 46 Parameter SCK Bit Clock Period (high to high) SCK Bit Clock High Time (high to low) SCK Bit Clock Low Time (low to high) Min Max Unit 25 10 10 -- -- -- ns ns ns Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU (continued) t45 t47 t46 SICK SIFS t48 t49 SID B0 B1 B0 B2 t50 5-8029 (F) Note: It is assumed that the SIU is configured with ICKA(SCON10[2]) = 1 for active mode input clock, ICKK(SCON10[3]) = 0 for no inversion of SICK, IFSA(SCON10[0]) = 1 for active mode input frame sync, IFSK(SCON10[1]) = 0 for no inversion of SIFS, IMSB(SCON0[2]) = 0 for LSB-first input, and IFSDLY[1:0](SCON1[9:8]) = 00 for no input frame sync delay. Figure 30. SIU Active Frame and Channel Mode Input Timing Diagram Table 49. Timing Requirements for SIU Active Frame Mode Input Abbreviated Reference t45 Parameter SICK Bit Clock Period (high to high) Min Max Unit 25 -- ns t49 SID Setup Time (valid to low) 9 -- ns t50 SID Hold Time (low to invalid) 8 -- ns The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). The period of SICK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (SCON11[7:0]). The application must ensure that the period of SICK is at least 25 ns. Table 50. Timing Characteristics for SIU Active Frame Mode Input Abbreviated Reference t46 t47 t48 Parameter SICK Bit Clock High Time (high to low) Min Max Unit TAGCKH - 3 TAGCKH + 3 ns SICK Bit Clock Low Time (low to high) TAGCKL - 3 SIFS Delay (high to high) TCKAG -5 ns ns TAGCKL + 3 TCKAG + 5 TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source. TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). Agere Systems Inc. 47 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU (continued) Table 51. Timing Requirements for SIU Active Channel Mode Input Abbreviated Reference Parameter Min Max Unit 61.035 -- ns t45 SICK Bit Clock Period (high to high) t49 SID Setup Time (valid to low) 9 -- ns t50 SID Hold Time (low to invalid) 8 -- ns The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). The period of SICK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (SCON11[7:0]). The application must ensure that the period of SICK is at least 61.035 ns. Table 52. Timing Characteristics for SIU Active Channel Mode Input Abbreviated Reference t46 Parameter SICK Bit Clock High Time (high to low) Min Max Unit TAGCKH - 3 TAGCKH + 3 ns t47 SICK Bit Clock Low Time (low to high) TAGCKL - 3 TAGCKL + 3 ns t48 SIFS Delay (high to high) TCKAG - 5 TCKAG + 5 ns TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source. TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). 48 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU (continued) t51 t53 t52 SOCK SOFS t54 t55 SOD B0 B1 B0 B2 t56 5-8030 (F) Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 1 for active mode output clock, OCKK(SCON10[7]) = 0 for no inversion of SOCK, OFSA(SCON10[4]) = 1 for active mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS, OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 for no output frame sync delay. Figure 31. SIU Active Frame Mode Output Timing Diagram Table 53. Timing Requirements for SIU Active Frame Mode Output Abbreviated Reference t51 Parameter Min Max Unit SOCK Bit Clock Period (high to high) 25 -- ns The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). The period of SOCK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (SCON11[7:0]). The application must ensure that the period of SOCK is at least 25 ns. Table 54. Timing Characteristics for SIU Active Frame Mode Output Abbreviated Reference t52 Parameter SOCK Bit Clock High Time (high to low) Min Max TAGCKH - 3 TAGCKH + 3 ns Unit t53 SOCK Bit Clock Low Time (low to high) TAGCKL - 3 TAGCKL + 3 ns t54 SOFS Delay (high to high) TCKAG - 5 TCKAG + 5 ns t55 SOD Data Delay (high to valid) 0 16 ns t56 SOD Data Hold (high to invalid) -3 5 ns TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source. TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). Agere Systems Inc. 49 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU (continued) t51 t53 t52 SOCK SOFS t54 t55 SOD B0 B0 B1 t56 t57 5-8028 (F) Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 1 for active mode output clock, OCKK(SCON10[7]) = 0 for no inversion of SOCK, OFSA(SCON10[4]) = 1 for active mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS, OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 for no output frame sync delay. Figure 32. SIU Active Channel Mode Output Timing Diagram Table 55. Timing Requirements for SIU Active Channel Mode Output Abbreviated Reference t51 Parameter SOCK Bit Clock Period (high to high) Min Max Unit 61.035 -- ns The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). The period of SOCK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (SCON11[7:0]). The application must ensure that the period of SOCK is at least 61.035 ns. Table 56. Timing Characteristics for SIU Active Channel Mode Output Abbreviated Reference Min Max Unit SOCK Bit Clock High Time (high to low) TAGCKH - 3 TAGCKH + 3 ns SOCK Bit Clock Low Time (low to high) TAGCKL -3 TAGCKL +3 ns t54 SOFS Delay (high to high) TCKAG -5 TCKAG +5 t55 SOD Data Delay (high to valid) 0 16 ns t56 SOD Data Hold (high to invalid) -3 5 ns t57 SOD Deactivation Delay (high to 3-state) -- 15 t52 t53 Parameter ns TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source. TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). 50 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU (continued) t80 t82 t81 SCK t84 t83 SIFS t83 SID B0 BN - 1 B2 t85 B4 t86 ICK ICK is the internal active generated bit clock shown for reference purposes only. Note: It is assumed that the SIU is configured with ICKA (SCON10[2]) = 1 for active mode input clock, I2XDLY (SCON1[11]) = 1 for extension of active input bit clock, IFSA (SCON10[0]) = 1 and AGSYNC (SCON12[14]) = 1 to configure SIFS as an input and to synchronize the active bit clocks and active frame syncs to SIFS, IFSK (SCON10[1]) = 1 for inversion of SIFS, IMSB (SCON0[2]) = 0 for LSB-first input, IFSDLY[1:0] (SCON1[9:8]) = 00 for no input frame sync delay, AGEXT (SCON12[12]) = 1 for SCK pin as active clock source, SCKK (SCON12[13]) = 1 for inversion of SCK, and AGCKLIM[7:0] (SCON11[7:0]) = 1 for an active clock divide ratio of 2. Figure 33. ST-Bus 2x Input Timing Diagram Table 57. ST-Bus 2x Input Timing Requirements Abbreviated Reference t80 t81 t82 t83 t84 t85 t86 Agere Systems Inc. Parameter SCK Clock Period SCK Clock Low Time SCK Clock High Time Input Frame Sync Hold Input Frame Sync Setup Input Data Setup Input Data Hold Min Max Unit 60 30 30 30 20 5 20 -- -- -- -- -- -- -- ns ns ns ns ns ns ns 51 Data Addendum May 2001 DSP16410C Digital Signal Processor 8 Timing Characteristics and Requirements (continued) 8.11 SIU (continued) t80 t82 t81 SCK t84 t83 SIFS t83 SOD t89 B0 BN - 1 B2 B4 t58 OCK OCK is the internal active generated bit clock shown for reference purposes only. Note: It is assumed that the SIU is configured with OCKA (SCON10[6]) = 1 for active mode output clock, IFSA(SCON10[0]) = 1 and AGSYNC (SCON12[14]) = 1 to configure SIFS as an input and to synchronize the active bit clocks and active frame syncs to SIFS, OFSA(SCON10[4]) = 1 for active output frame sync, IFSK(SCON10[1]) = 1 for inversion of SIFS, OMSB(SCON0[10]) = 0 for LSB-first input, OFSDLY[1:0](SCON2[9:8]) = 00 for no output frame sync delay, AGEXT (SCON12[12]) = 1 for SCK pin as active clock source, SCKK (SCON12[13]) = 1 for inversion of SCK, and AGCKLIM[7:0] (SCON11[7:0]) = 1 for an active clock divide ratio of 2. Figure 34. ST-Bus 2x Output Timing Diagram Table 58. ST-Bus 2x Output Timing Requirements Abbreviated Reference t80 t81 t82 t83 t84 Parameter SCK Clock Period SCK Clock Low Time SCK Clock High Time Input Frame Sync Hold Input Frame Sync Setup Min Max Unit 60 30 30 30 20 -- -- -- -- -- ns ns ns ns ns Min Max Unit 1 0 25 4 ns ns Table 59. ST-Bus 2x Output Timing Characteristics Abbreviated Reference t89 t58 52 Parameter Output Data Delay Output Data Hold Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor 9 Package Diagrams 9.1 208-Pin PBGA All dimensions are in millimeters. 17.00 0.20 +0.70 15.00 -0.05 A1 BALL IDENTIFIER ZONE +0.70 15.00 -0.05 17.00 0.20 1.91 1.56 0.21 0.80 0.05 0.61 0.06 SEATING PLANE 0.20 0.50 0.10 SOLDER BALL 15 SPACES @ 1.00 = 15.00 1.00 T R P N +0.07 0.63 -0.13 M L K J 15 SPACES @ 1.00 = 15.00 H G F E D C B A A1 BALL CORNER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 5-7809 (F).b Agere Systems Inc. 53 Data Addendum May 2001 DSP16410C Digital Signal Processor 9 Package Diagrams (continued) 9.2 256-Pin EBGA All dimensions are in millimeters. 27.00 0.20 A1 BALL IDENTIFIER ZONE 27.00 0.20 0.80/1.00 1.70 MAX SEATING PLANE 0.15 SOLDER BALL 0.60 0.10 19 SPACES @ 1.27 = 24.13 Y W V U T R P N M L K J H G F E D C B A A1 BALL CORNER 0.75 0.15 19 SPACES @ 1.27 = 24.13 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 5-5288 (F).a 54 Agere Systems Inc. Data Addendum May 2001 DSP16410C Digital Signal Processor Notes Agere Systems Inc. 55 For additional information, contact your Account Manager or the following: http://www.agere.com INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright (c) 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A. May 2001 DA01-003WINF (Replaces DA00-015WTEC and Must Accompany DS01-070WTEC)