DSP16410C Digital Signal Processor
Data Addendum
May 2001
1 Introduction
This addendum contains information specific to the
DSP16410C. The DSP16410C is pin-compatible and
functionally identical to the DSP16410B. However, the
DSP16410C provides higher speed operation and
lower power dissipation than the DSP16410B. This
document describes the differences between the
DSP16410B and the DSP16410C. It should be used
as a supplement to the DSP16410B Digital Signal Pro-
cessor Data Sheet (DS01-070WTEC).
2 Features
■High performance:
—Up to 800 million MA CS per second at 200 MHz
■Low po wer:
—1.575 V internal supply for power efficiency
—3.3 V I/O pin supply for compatibility
■Changes from the DSP16410B to the DSP16410C:
—Maximum processor speed has changed from
185 MHz to 200 MHz
—Nominal internal supply voltage changed from
1.8 V to 1.575 V
—New JTAGID register settings for both cores
3 Device Identification
The DSP16410C has different JTAG identification
numbers for each core. These identifiers are different
from those of the DSP16410B and can be accessed
through the JTAG port of each core. Table 1 lists the
JTAG identification numbers for each core of the
DSP16410C.
Table 1. Device Identifiers
Identifier DSP1641 0B DSP16410C
JTAG0 JTAG ID 0x2c814 03b 0x4c8140 3b
JTAG1 JTAG ID 0x3c814 03b 0x5c8140 3b
Table of Contents
Contents Page
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Systems Inc.2
1 Introduction ................................................................................................................................................ 1
2 Features..................................................................................................................................................... 1
3 Device Identification................................................................................................................................... 1
4 Notation Conventions................................................................................................................................. 6
5 Ball Grid Array Information......................................................................................................................... 7
5.1 208-Ball PBGA Package .................................................................................................................. 7
5.2 256-Ball EBGA Package ................................................................................................................ 10
6 Device Characteristics ............................................................................................................................. 13
6.1 Absolute Maximum Ratings............................................................................................................ 13
6.2 Handling Precautions ..................................................................................................................... 13
6.3 Recommended Operating Conditions ............................................................................................ 14
6.3.1 Package Thermal Considerations .......................................................................................... 14
7 Electrical Characteristics and Requirements ........................................................................................... 15
7.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs........................... 17
7.2 Analog Power Supply Decoupling.................................................................................................. 18
7.3 Power Dissipation........................................................................................................................... 19
7.3.1 Internal Power Dissipation...................................................................................................... 19
7.3.2 I/O Power Dissipation............................................................................................................. 20
7.4 Power Supply Sequencing Issues.................................................................................................. 21
7.4.1 Supply Sequencing Recommendations ................................................................................. 21
7.4.2 External Power Sequence Protection Circuits........................................................................ 23
8 Timing Characteristics and Requirements............................................................................................... 24
8.1 Phase-Lock Loop ........................................................................................................................... 25
8.2 Wake-Up Latency........................................................................................................................... 25
8.3 DSP Clock Generation ................................................................................................................... 26
8.4 Reset Circuit................................................................................................................................... 27
8.5 Reset Synchronization.................................................................................................................... 28
8.6 JTAG.............................................................................................................................................. 29
8.7 Interrupt and Trap........................................................................................................................... 30
8.8 Bit I/O ............................................................................................................................................. 31
8.9 System and External Memory Interface ......................................................................................... 32
8.9.1 Asynchronous Interface.......................................................................................................... 33
8.9.2 Synchronous Interface ........................................................................................................... 36
8.9.3 ERDY Interface ...................................................................................................................... 38
8.10 PIU ................................................................................................................................................. 39
8.11 SIU ................................................................................................................................................. 43
9 Package Diagrams................................................................................................................................... 53
9.1 208-Pin PBGA................................................................................................................................ 53
9.2 256-Pin EBGA................................................................................................................................ 54
List of Figures
Figure Page
Agere Systems Inc. 3
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Figure 1. 208-Ball PBGA Package Ball Grid Array Assignments (See-Through Top View)................................ 7
Figure 2. 256-Ball EBGA Package Ball Grid Array Assignments (See-Through Top View).............................. 10
Figure 3. Plot of VOH vs. IOH Under Typical Operating Conditions .................................................................... 16
Figure 4. Plot of VOL vs . IOL Under Typical Operating Conditions ..................................................................... 16
Figure 5. Analog Supply Bypass and Decoupling Capacitors........................................................................... 18
Figure 6. Power Supply Sequencing Recommendations.................................................................................. 22
Figure 7. Power Supply Example...................................................................................................................... 23
Figure 8. Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs....... 24
Figure 9. I/O Clock Timing Diagram ................................................................................................................. 26
Figure 10. Powerup and Device Reset Timing Diagram .................................................................................... 27
Figure 11. Reset Synchronization Timing............................................................................................................ 28
Figure 12. JTAG I/O Timing Diagram ................................................................................................................. 29
Figure 13. Interrupt and Trap Timing Diagram.................................................................................................... 30
Figure 14. Write Outputs Followed by Read Inputs (cbit = IMMEDIATE; a1 = sbit) Timing Characteristics...... 31
Figure 15. Enable and Write Strobe Transition Timing........................................................................................ 32
Figure 16. Timing Diagram for EREQN and EACKN........................................................................................... 33
Figure 17. Asynchronous Read Timing Diagram (RHOLD = 0 and RSETUP = 0).............................................. 34
Figure 18. Asynchronous Write Timing Diagram (WHOLD = 0, WSETUP = 0) .................................................. 35
Figure 19. Synchronous Read Timing Diagram (Read-Read-Write Sequence).................................................. 36
Figure 20. Synchronous Write Timing Diagram................................................................................................... 37
Figure 21. ERDY Pin Timing Diagram................................................................................................................. 38
Figure 22. Host Data Write to PDI Timing Diagram............................................................................................. 39
Figure 23. Host Data Read from PDO Timing Diagram ...................................................................................... 40
Figure 24. Host Register Write (PAH, PAL, PCON, or HSCRATCH) Timing Diagram........................................ 41
Figure 25. Host Register Read (PAH, PAL, PCON, or DSCRATCH) Timing Diagram........................................ 42
Figure 26. SIU Passive Frame and Channel Mode Input Timing Diagram.......................................................... 43
Figure 27. SIU Passive Frame Mode Output Timing Diagram............................................................................ 44
Figure 28. SIU Passive Channel Mode Output Timing Diagram......................................................................... 45
Figure 29. SCK External Clock Source Input Timing Diagram............................................................................ 46
Figure 30. SIU Active Frame and Channel Mode Input Timing Diagram ............................................................ 47
Figure 31. SIU Active Frame Mode Output Timing Diagram............................................................................... 49
Figure 32. SIU Active Channel Mode Output Timing Diagram............................................................................ 50
Figure 33. ST-Bus 2x Input Timing Diagram....................................................................................................... 51
Figure 34. ST-Bus 2x Output Timing Diagram .................................................................................................... 52
List of Tables
Table Page
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Systems Inc.4
Table 1. Device Identifiers.......................................................................................................................................1
Table 2. 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol.........................................................8
Table 3. 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol.......................................................11
Table 4. Absolute Maximum Ratings for Supply Pins...........................................................................................13
Table 5. Recommended Operating Conditions.....................................................................................................14
Table 6. Package Thermal Considerations...........................................................................................................14
Table 7. Electrical Characteristics and Requirements..........................................................................................15
Table 8. Internal Power Dissipation at 1.575 V.....................................................................................................19
Table 9. I/O Power Dissipation at 3.3 V ................................................................................................................20
Table 10. Power Sequencing Recommendations...................................................................................................22
Table 11. Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs.............24
Table 12. PLL Requirements..................................................................................................................................25
Table 13. Wake-Up Latency....................................................................................................................................25
Table 14. Timing Requirements for Input Clock......................................................................................................26
Table 15. Timing Characteristics for Input Clock and Output Clock........................................................................26
Table 16. Timing Requirements for Powerup and Device Reset.............................................................................27
Table 17. Timing Characteristics for Device Reset.................................................................................................27
Table 18. Timing Requirements for Reset Synchronization Timing........................................................................28
Table 19. Timing Requirements for JTAG I/O .........................................................................................................29
Table 20. Timing Characteristics for JTAG I/O........................................................................................................29
Table 21. Timing Requirements for Interrupt and Trap ...........................................................................................30
Table 22. Timing Requirements for BIO Input Read...............................................................................................31
Table 23. Timing Characteristics for BIO Output ....................................................................................................31
Table 24. Timing Characteristics for Memory Enables and ERWN ........................................................................32
Table 25. Timing Requirements for EREQN...........................................................................................................33
Table 26. Timing Characteristics for EACKN and SEMI Bus Disable.....................................................................33
Table 27. Timing Requirements f or Asynchronous Memory Read Operations.......................................................34
Table 28. Timing Characteristics for Asynchronous Memory Read Operations.....................................................34
Table 29. Timing Characteristics for Asynchronous Memory Write Operations .....................................................35
Table 30. Timing Requirements f or Synchronous Read Operations.......................................................................36
Table 31. Timing Characteristics for Synchronous Read Operations.....................................................................36
Table 32. Timing Characteristics for Synchronous Write Operations .....................................................................37
Table 33. Timing Requirements for ERDY Pin........................................................................................................38
Table 34. Timing Requir eme nts for PIU Data Wr i te Operations............... ...... ....... ...... ....... ................... ....... .. ........39
Table 35. Timing Characteristics for PIU Data Write Operations............................................................................39
Table 36. Timing Requireme nts for PIU Data Read Operation s......... ................... ...... ....... ...... ....... .......................40
Table 37. Timing Characteristics for PIU Data Read Operations............................................................................40
Table 38. Timing Requir eme nts for PIU Regist er Write Operations ... ...... ...... ....... ...... ....... ...... ....... ...... .................41
Table 39. Timing Characteristics for PIU Register Write Operations......................................................................41
Table 40. Timing Requirements for PIU Register Read Operations.......................................................................42
Table 41. Timing Characteristics for PIU Register Read Operations......................................................................42
Table 42. Timing Requirements for SIU Passive Frame Mode Input......................................................................43
Table 43. Timing Requirements f or SIU Passive Channel Mode Input...................................................................43
Table 44. Timing Requirements for SIU Passive Frame Mode Output ...................................................................44
Table 45. Timing Characteristics for SIU Passive Frame Mode Output..................................................................44
Table 46. Timing Requirements f or SIU Passive Channel Mode Output................................................................45
Table 47. Timing Characteristics for SIU Passive Channel Mode Output...............................................................45
Table 48. Timing Requirements for SCK External Clock Source............................................................................46
Table 49. Timing Requirements for SIU Active Frame Mode Input.........................................................................47
Table 50. Timing Characteristics for SIU Active Frame Mode Input .......................................................................47
Table 51. Timing Requirements f or SIU Active Channel Mode Input......................................................................48
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 5
List of Tables(continued)
Table Page
Table 52. Timing Characteristics for SIU Active Channel Mode Input ....................................................................48
Table 53. Timing Requirements for SIU Active Frame Mode Output......................................................................49
Table 54. Timing Characteristics for SIU Active Frame Mode Output.....................................................................49
Table 55. Timing Requirements for SIU Active Channel Mode Output...................................................................50
Table 56. Timing Characteristics for SIU Active Channel Mode Output .................................................................50
Table 57. ST-Bus 2x Input Timing Requirements....................................................................................................51
Table 58. ST-Bus 2x Output Timing Requirements.................................................................................................52
Table 59. ST-Bus 2x Output Timing Characteristics ...............................................................................................52
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
6
4 Notation Conventions
The following notation conventions apply to this data
addendum:
lower-case Registers that are directly writable or
readable by DSP16410 core instruc-
tions are lower-case.
UPPER-CASE Device flags, I/O pins, control re gister
fields, and registers that are not directly
writab le or readab le by DSP16410 core
instruct ion s ar e upper- ca se.
boldface Register names and DSP16410 core
instructions are printed in boldface
when used in text descriptions.
italics Doc um enta tio n varia bles that are
replaced are printed in italics.
courier DSP16410 program examples or C-lan-
guage representations are printed in
courier font.
[ ] Square brackets enclose a range of
numbers that represents multiple bits in
a single register or bus. The range of
numbers is delimited by a colon. For
example, imux[11:10] are bits 11 and
10 of the program-accessible imux reg-
ister.
〈〉 Angle brackets enclose a list of items
delimited by commas or a range of
items delimited by a dash (—), one of
which is selected i f used in an
instruction. For example, SADD〈0—3〉
represents the four memory-mapped
registers SADD0, SADD1, SADD2,
and SADD3, and the gene ral instruc-
tion aTE〈h,l〉=RB
can be replaced
with a0h = timer0.
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 7
5 Ball Grid Array Information
5.1 208-Ball PBGA Package
Figure 1 illustrates the ball assignment for the 208-ball PBGA package. This view is from the top of the package.
The ball assignment for the DSP16410C is compatible with that of the DSP16410B.
Figure 1. 208-Ball PBGA Package Ball Grid Array Assignments (See-Through Top View)
1 2 3 4 5 6 7 8 9 10111213141516
AVDD2 ED5 ED7 ED9 ED11 ED15 ED17 VSS VDD1 ED26 ED30 ERWN1 VSS EION EA1 VDD2 A
BED3 VDD1 ED6 ED8 VSS ED14 ED16 ED20 ED25 ED27 ED31 EROMN ERAMN EA0 VDD1 EA3 B
CED2 ED1 ED4 ED10 ED12 VDD1 ED18 ED21 ED24 VDD2 ED29 ERWN0 VDD2 EA2 EA4 EA5 C
DVSS ED0 VDD2 VDD1 ED13 VDD2 ED19 ED22 ED23 VSS ED28 EACKN VDD1 EA8 EA7 EA6 D
EEREQN ERDY ESIZE EXM EA11 EA10 VSS EA9 E
FTDO0 ERTYPE TRST0N TCK0 VDD2 VDD1 EA12 EA13 F
GTDI0 TMS0 VDD2 VSS VSS VSS VSS VSS EA17 EA16 EA14 EA15 G
HVDD1A CKI VSS1A RSTN VSS VSS VSS VSS ESEG1 ESEG0 EA18 VSS H
JVSS INT2 INT3 TRAP VSS VSS VSS VSS ESEG2 ESEG3 VDD1 ECKO J
KSICK0 SIFS0 INT0 INT1 VSS VSS VSS VSS VSS VDD2 TMS1 TDI1 K
LSOCK0 SOFS0 VDD1 VDD2 TCK1 TRST1N SOD1 TDO1 L
MSOD0 VSS SID0 SCK0 SID1 SCK1 SOCK1 SOFS1 M
NIO0BIT5 IO0BIT4 IO0BIT6 VDD1 PD10 PD6 VSS PD1 PD0 PRDY VDD2 PCSN VDD1 VDD2 SIFS1 VSS N
PIO0BIT3 IO0BIT2 IO0BIT0 VDD2 PD11 PD7 VDD2 PD2 POBE PINT VDD1 PADD3 PADD1 IO1BIT2 IO1BIT0 SICK1 P
RIO0BIT1 VDD1 EYMODE PD14 PD13 PD9 PD5 VDD1 PIBF PODS PRWN VSS PADD0 IO1BIT4 VDD1 IO1BIT1 R
TVDD2 VSS PD15 VSS PD12 PD8 PD4 PD3 VSS PRDYMD PIDS PADD2 IO1BIT6 IO1BIT5 IO1BIT3 VDD2 T
1 2 3 4 5 6 7 8 9 10111213141516
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
8
5 Ball Grid Array Information (continued)
5.1 208-Ball PBGA Package (continued)
Table 2 describes the PBGA ball assignments sorted by symbol for the 208-ball package. For each signal or
power/ground connection, this table lists the PBGA coordinate, the symbol name, the type (I = input, O = output,
I/O = input/output, O/Z = 3-state output, P = power, G = ground), and description. Inputs and bidirectional pins do
not maintain full CMOS levels when not driven. They must be pulled to VDD2 or VSS through the appro priate pul l
up/down resistor (refer to Section 7.1). An unused external SEMI data bus (ED[31:0]) can be statically configured
as outputs by asserting the EYMODE pin. At full CMOS levels, no significant dc current is drawn.
Table 2. 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol
Symbol 208-Ball PBGA Coordinate Type Description
CKI H2 I External Clock Input.
EA[18:0] H15, G13, G14, G16, G15, F16, F15,
E13, E14, E16, D14, D15, D16, C16,
C15, B16, C14, A15, B14
O External Address Bus, Bits 18—0.
EACKN D12 O External Devi ce Acknowledge for External Memory Inter-
face (negative assertion).
ECKO J16 O Programmable Clock Output.
ED[31:0] B11, A11, C11, D11, B10, A10, B9, C9,
D9, D8, C8, B8, D7, C7, A7, B7, A6, B6,
D5, C5, A5, C4, A4, B4, A3, B3, A2, C3,
B1, C1, C2, D2
I/O External Memory Data Bus, Bits 31—0.
EION A14 O Enable for External I/O (negative assertion).
ERAMN B13 O External RAM Enable (negative assertion).
ERDY E2 I External Memory Device Ready.
EREQN E1 I External Device Request for EMI Interface (negative
assertion).
EROMN B12 O Enable for Ex ternal ROM (negative assertion).
ERTYPE F2 I EROM Type Control:
If 0, asynchronous SRAM mode.
If 1, synchronous SRAM mode.
ERWN0 C12 O Read/Write, Bit 0 (negative assertion).
ERWN1 A12 O Read/Write, Bit 1 (negative assertion).
ESEG[3:0] J14, J13, H13, H14 O External Segment Address, Bits 3—0.
ESIZE E3 I External Memory Bus Size Control:
If 0, 16-bit external interface.
If 1, 32-bit external interface.
EXM E4 I External Boot-up Control for CORE0.
EYMODE R3 I External Data Bus Mode Configuration Pin.
INT[3:0] J3, J2, K4, K3 I External Interrupt Requests 3—0.
IO0BIT[6:0] N3, N1, N2, P1, P2, R1, P3 I/O BIO0 Status/Control, Bits 6—0.
IO1BIT[6:0] T13, T14, R14, T15, P14, R16, P15 I/O BIO1 Status/Control, Bits 6—0.
PADD[3:0] P12, T12, P13, R13 I PIU Address, Bits 3—0.
PCSN N12 I PIU Chip Select (negative assertion).
PD[15:0] T3, R4, R5, T5, P5, N5, R6, T6, P6, N6,
R7, T7, T8, P8, N8, N9 I/O PIU Data Bus, Bits 15—0.
PIBF R9 O PIU Input Buffer Full Flag.
PIDS T11 I PIU Input Data Strobe.
PINT P10 O PIU Interrupt Request to Host.
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 9
5 Ball Grid Array Information (continued)
5.1 208-Ball PBGA Package (continued)
Table 2. 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol (continued)
Symbol 208-Ball PBGA Coordinate Type Description
POBE P9 O PIU Output Buffer Empty Flag.
PODS R10 I PIU Output Data Strobe.
PRDY N10 O PIU Host Ready.
PRDYMD T10 I PRDY Mode.
PRWN R11 I PIU Read/Write (negative assertion).
RSTN H4 I Device Reset (negative assertion).
SCK0 M4 I External Clock for SIU0 Active Generator.
SCK1 M14 I External Clock for SIU1 Active Generator.
SICK0 K1 I/O SIU0 Input Clock.
SICK1 P16 I/O SIU1 Input Clock.
SID0 M3 I SIU0 Input Data.
SID1 M13 I SIU1 Input Data.
SIFS0 K2 I/O SIU0 Input Frame Sync.
SIFS1 N15 I/O SIU1 Input Frame Sync.
SOCK0 L1 I/O SIU0 Output Clock.
SOCK1 M15 I/O SIU1 Output Clock.
SOD0 M1 O/Z SIU0 Output Data.
SOD1 L15 O/Z SIU1 Output Data.
SOFS0 L2 I/O SIU0 Output Frame Sync.
SOFS1 M16 I/O SIU1 Output Frame Sync.
TCK0 F4 I JTAG Test Clock for CORE0.
TCK1 L13 I JTAG Test Clock for CORE1.
TDI0 G1 I JTAG Test Data Input for CORE0.
TDI1 K16 I JTAG Test Data Input for CORE1.
TDO0 F1 O JTAG Test Data Output for CORE0.
TDO1 L16 O JTAG Test Data Output for CORE1.
TMS0 G2 I JTAG Test Mode Select for CORE0.
TMS1 K15 I JTAG Test Mode Select for CORE1.
TRAP J4 I/O TRAP/Breakpoint Indication.
TRST0N F3 I JTAG TAP Controller Reset for CORE0 (negative asser-
tion).
TRST1N L14 I JTAG TAP Controller Reset for CORE1 (negative asser-
tion).
VDD1 A9, B2, B15, C6, D4, D13, F14, J15,
L3, N4, N13, P11, R2, R8, R15 P Power Supply for Internal Circ uitry.
VDD1A H1 P Power Supply for PLL Circuitry.
VDD2 A1, A16, C13, D3, D6, F13, G3, K14,
L4, N11, N14, P4, P7, T1, T16, C10 P Power Supply for External Circuitry (I/O).
VSS A13, A8, B5, D1, D10, E15, G7, G8,
G9, G10, G4, H7, H8, H9, H10, H16,
J1, J7, J8, J9, J10, K7, K8, K9, K10,
K13, M2, N7, N16, R12, T2, T4, T9
G Ground.
VSS1A H3 G Ground for PLL Circuitry.
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
10
5 Ball Grid Array Information (continued)
5.2 256-Ball EBGA Package
Figure 2 illustrates the ball assignment for the 256-ball EBGA package. This view is from the top of the package.
The ball assignment for the DSP16410C is compatible with that of the DSP16410B.
Figure 2. 256-Ball EBGA Package Ball Grid Array Assignments (See-Through Top View)
1234567891011121314151617181920
AVSS VDD2 EION ERWN1 VSS VSS VDD2 ED27 ED25 ED23 VDD2 VSS VSS ED15 VDD2 VSS ED9 ED5 VDD2 VSS A
BVDD2 VSS EA2 ERAMN ERWN0 ED30 NC ED28 ED26 ED22 ED20 ED18 ED17 ED14 NC ED11 ED7 VDD1 VSS VDD2 B
CEA4 EA3 VSS EA1 VDD1 EACKN VDD1 ED29 VDD1 VDD1 ED21 ED19 ED16 ED13 ED12 ED8 NC VSS ED4 ED1 C
DEA8 EA6 VDD1 NC EA0 EROMN ED31 VDD2 VDD1 ED24 VDD2 VDD1 VDD1 VDD2 ED10 ED6 NC ED3 ED0 EREQN D
EVSS EA10 EA7 EA5 ED2 VDD1 ESIZE VSS E
FVDD2 NC EA11 EA9 ERDY EXM TDO0 VSS F
GVDD1 EA13 EA12 VDD2 ERTYPE VDD1 NC VDD2 G
HVSS EA16 EA15 EA14 VDD2 TRST0N TCK0 TMS0 H
JVSS VDD1 EA18 EA17 TDI0 VDD1A CKI VSS1A J
KVDD2 ESEG0 NC VDD2 RSTN INT3 VDD1 TRAP K
LESEG2 ESEG1 VDD1 ESEG3 VDD2 INT2 INT1 VDD2 L
MECKO TDI1 VDD1 VDD1 SICK0 INT0 SIFS0 VSS M
NTMS1 TCK1 TRST1N VDD2 SOFS0 SOCK0 VDD1 VSS N
PVDD2 NC VDD1 SOD1 VDD2 SOD0 SID0 SCK0 P
RVSS TDO1 SID1 SOCK1 IO0BIT4 IO0BIT6 NC VDD2 R
TVSS SCK1 VDD1 IO1BIT0 VDD1 IO0BIT2 IO0BIT5 VSS T
USOFS1 SIFS1 IO1BIT1 NC IO1BIT4 PADD1 VDD2 VDD1 VDD1 VDD2 PD2 VDD1 VDD2 PD9 PD13 EYMODE NC NC IO0BIT1 IO0BIT3 U
VSICK1 IO1BIT2 VSS NC IO1BIT6 PADD3 PCSN PODS PRDY POBE VDD1 VDD1 PD7 VDD1 PD10 VDD1 VSS VSS NC NC V
WVDD2 VSS VDD1 IO1BIT5 PADD2 NC PRWN PRDYMD PINT PIBF PD0 PD4 PD6 NC PD8 PD11 PD14 IO0BIT0 VSS VDD2 W
YVSS VDD2 IO1BIT3 PADD0 VSS VDD2 PIDS VSS VSS VDD2 PD1 PD3 PD5 VDD2 VSS VSS PD12 PD15 VDD2 VSS Y
1234567891011121314151617181920
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 11
5 Ball Grid Array Information (continued)
5.2 256-Ball EBGA Package (continued)
Table 3 describes the EBGA ball assignments sorted by symbol for the 256-ball package. For each signal or
power/ground connection, this table lists the EBGA coordinate, the symbol name, the type (I = input, O = output,
I/O = input/output, O/Z = 3-state output, P = power, G = ground), and description. Inputs and bidirectional pins do
not maintain full CMOS levels when not driven. They must be pulled to VDD2 or VSS through the app ropriate pul l
up/down resistor (refer to Section 7.1). An unused external SEMI data bus (ED[31:0]) can be statically configured
as outputs by asserting the EYMODE pin. At full CMOS levels, no significant dc current is drawn.
Table 3. 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol
Symbol PBGA
Coordinate Type Description
CKI J19 I External Clock Input.
EA[18:0] B3, C1, C2, C4, D1, D2, D5, E2, E3, E4, F3,
F4, G2, G3, H2, H3, H4, J3, J4 O External Address Bus, Bits 18—0.
EACKN C6 O External Device Acknowledge for External Memory
Interface (negative assertion).
ECKO M1 O Programmable Clock Output.
ED[31:0] A8, A9, A10, A14, A17, A18, B6, B8, B9,
B10, B11, B12, B13, B14, B16, B17, C8,
C11, C12, C13, C14, C15, C16, C19, C20,
D7, D10, D15, D16, D18, D19, E17
I/O External Memory Data Bus, Bits 31—0.
EION A3 O Enable for External I/O (negative assertion).
ERAMN B4 O External RAM Enable (negative assertion).
ERDY F17 I External Memory Device Ready.
EREQN D20 I External Device Request for EMI Interface (negative
assertion).
EROMN D6 O Enable for External ROM (negative assertion).
ERTYPE G17 I EROM Type Control:
If 0, asynchronous SRAM mode.
If 1, synchronous SRAM mode.
ERWN0 B5 O Read/Write, Bit 0 (negative assertion).
ERWN1 A4 O Read/Write, Bit 1 (negative assertion).
ESEG[3:0] K2, L1, L2, L4 O External Segment Address, Bits 3—0.
ESIZE E19 I External Memory Bus Size Control:
If 0, 16-bit external interface.
If 1, 32-bit external interface.
EXM F18 I External Boot-up Control for CORE0.
EYMODE U16 I External Data Bus Mode Configuration Pin.
INT[3:0] K18, L18, L19, M18 I External Interrupt Requests 3—0.
IO0BIT[6:0] R17, R18, T18, T19, U19, U20, W18 I/O BIO0 Status/Control, Bits 6—0.
IO1BIT[6:0] T4, U3, U5, V2, V5, W4, Y3 I/O BIO1 Status/Control, Bits 6—0.
PADD[3:0] U6, V6, W5, Y4 I PIU Address, Bits 3—0.
PCSN V7 I PIU Chip Select (negative assertion).
PD[15:0] U11, U14, U15, V13, V15, W11, W 12, W13,
W15, W16, W17, Y11, Y12, Y13, Y17, Y18 I/O PIU Data Bus, Bits 15—0.
PIBF W10 O PIU Input Buffer Full Flag.
PIDS Y7 I PIU Input Data Strobe.
PINT W9 O PIU Interrupt Request To Host.
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
12
5 Ball Grid Array Information (continued)
5.2 256-Ball EBGA Package (continued)
Table 3. 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol (continued)
Symbol PBGA Coordinate Type Description
POBE V10 O PIU Output Buffer Empty Flag.
PODS V8 I PIU Output Data Strobe.
PRDY V9 O PIU Host Ready.
PRDYMD W8 I PRDY Mode.
PRWN W7 I PIU Read/Write (negative assertion).
RSTN K17 I Device Reset (negative assertion).
SCK0 P20 I External Clock for SIU0 Active Generator.
SCK1 T2 I External Clock for SIU1 Active Generator.
SICK0 M17 I/O SIU0 Input Clock.
SICK1 V1 I/O SIU1 Input Clock.
SID0 P19 I SIU0 Input Data.
SID1 R3 I SIU1 Input Data.
SIFS0 M19 I/O SIU0 Input Frame Sync.
SIFS1 U2 I/O SIU1 Input Frame Sync.
SOCK0 N18 I/O SIU0 Output Clock.
SOCK1 R4 I/O SIU1 Output Clock.
SOD0 P18 O/Z SIU0 Output Data.
SOD1 P4 O/Z SIU1 Output Data.
SOFS0 N17 I/O SIU0 Output Frame Sync.
SOFS1 U1 I/O SIU1 Output Frame Sync.
TCK0 H19 I JTAG Test Clock for CORE0.
TCK1 N2 I JTAG Test Clock for CORE1.
TDI0 J17 I JTAG Test Data Input for CORE0.
TDI1 M2 I JTAG Test Data Input for CORE1.
TDO0 F19 O JTAG Test Data Output for CORE0.
TDO1 R2 O JTAG Test Data Output for CORE1.
TMS0 H20 I JTAG Test Mode Select for CORE0.
TMS1 N1 I JTAG Test Mode Select for CORE1.
TRAP K20 I/O TRAP/Breakpoint Indication.
TRST0N H18 I JTAG TAP Controller Reset for CORE0 (negative
assertion).
TRST1N N3 I JTAG TAP Controller Reset for CORE1 (negative
assertion).
VDD1 B18, C5, C7, C9, C10, D3, D9, D12,
D13, E18, G1, G18, J2, K19, L3, M3, M4,
N19, P3, T3, T17, U8, U9, U12, V11,
V12, V14, V16, W3
P Power Supply for Internal Circuitry.
VDD1A J18 P Power Supply for PLL Circuitry.
VDD2 A2, A7, A11, A15, A19, B1, B20, D8,
D11, D14, F1, G4, G20, H17, K1, K4,
L17, L20, N4, P1, P17, R20, U7, U10,
U13, W1, W20, Y2, Y6, Y10, Y14, Y19
P Power Supply for External Circuitry (I/O).
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 13
5 Ball Grid Array Information (continued)
5.2 256-Ball EBGA Package (continued)
6 Device Characteristics
6.1 Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
External leads can be bonded and soldered safely at temperatures of up to 220 °C.
6.2 Handling Precautions
All MOS devices must be handled with certain precautions to avoid damage due to the accumulation of static
charge. Although input protection circuitry has been incorporated into the devices to minimize the effect of this
static buildup, proper precautions should be taken to avoid exposure to electrostatic discharge during handling and
mounting. Agere Systems Inc. employs a human-body model for ESD-susceptibility testing. Since the failure volt-
age of electronic devices is dependent on the current, voltage, and hence, the resistance and capacitance, it is
important that standard values be employed to establish a reference by which to compare test data. Values of
100 pF and 1500 Ω are the most common and are the values used in the Agere human-body model test circuit.
The breakdown voltage for the DSP16410C is greater than 1000 V.
Table 3. 256-Ball EBGA Ball Assignments Sorted Alphabetically by Symbol (continued)
Symbol PBGA Coordinate Type Description
VSS A1, A5, A6, A12, A13, A16, A20, B2, B19, C3,
C18, E1, E20, F20, H1, J1, M20, N20, R1, T1,
T20, V3, V17, V18, W 2, W19, Y1, Y 5, Y8, Y9,
Y15, Y16, Y20
G Ground.
VSS1A J20 G Ground for PLL Circuitry.
NC B7, B15, C17, D4, D17, F2, G19, K3, P2,
R19, U4, U17, U18, V4, V19, V20, W6, W14 —Not Connected. Tie externally to ground.
Table 4. Absolute Maximum Ratings for Supply Pins
Parameter Min Max Unit
Voltage on VDD1 with Respect to Ground –0.5 1.8 V
Voltage on VDD1A with Respect to Groun d –0.5 1.8 V
Voltage on VDD2 with Respect to Ground –0.5 4.0 V
Voltage Range on Any Signal Pin VSS –0.3 VDD2+0.3 V
4.0
Junction Temperature (TJ)–40 125 °C
Storage Temperature Range –40 150 °C
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
14
6 Device Characteristics (continued)
6.3 Recommended Operating Conditions
The ratio of the instruction cycle rate to the input clock frequency is 1:1 without the PLL and
((M + 2) /((D + 2) * f(OD))):1 with the PLL selected. The maximum input cloc k (CKI pin) frequenc y when the PLL
is not selected as the dev ice clock source is 50 MHz. The maximum input cloc k frequency is 40 MHz when
the PLL is selected.
6.3.1 Package Thermal Considerations
The maximum allowable ambient temperature, TAMAX, is dependent upon the device power dissipation and is deter-
mined by the following equation:
TAMAX = TJMAX – PMAX x ΘJA
Where PMAX is the maximum device power dissipation for the application, TJMAX is the maximum device junction
temperature specified in Table 6, and ΘJA is the maximum thermal resistance in still-air-ambient specified in
Table 6. See Section 7.3 for information on determining the maximum device power dissipation.
WARNING: Due to package thermal constraints, proper precautions in the user's application should be
taken to avoid exceeding the maximum junction temperature of 120 °C. Otherwise, the device
performance and reliability is adversely affected.
Table 5. Recommended Operating Conditions
Maximum
Internal Clock
(CLK) Frequency
Minimum
Internal Clock
(CLK) Period T
Junction
Temperature TJ (°C) Supply Voltage
VDD1, VDD1A (V) Supply Voltage
VDD2 (V)
Min Max Min Max Min Max
200 MHz 5.0 ns –40 120 1.5 1.65 3.0 3.6
Table 6. Package Thermal Considerations
Device Package Parameter Value Unit
208 PBGA Maximum Junction Temperature (TJMAX) 120 °C
208 PBGA Maximum Thermal Resistance in Still-Air-Ambient (ΘJA)27
°C/W
256 EBGA Maximum Junction Temperature (TJMAX) 120
°C
256 EBGA Maximum Thermal Resistance in Still-Air-Ambient (ΘJA)15
°C/W
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 15
7 Electrical Characteristics and Requirements
Electrical characteristics ref er to the behavior of the de vice under specified conditions. Electrical requirements refer
to conditions imposed on the user for proper operation of the device. The parameters in Table 7 are valid for the
conditions described in Section 6.3, on page 14.
Table 7. Electrical Characteristics and Requirements
Parameter Symbol Min Max Unit
Input Volta ge:
Low
High VIL
VIH –0.3
0.7 × VDD20.3 × VDD2
VDD2 + 0.3 V
V
Input Current (except TMS0, TMS1, TDI0,
TDI1, TRST0N, TRST1N):
Low (VIL = 0 V, VDD2 = 3.6 V)
High (VIH = 3.6 V, VDD2 = 3.6 V)
IIL
IIH –5
——
5µA
µA
Input Current (TMS0, TMS1, TDI0, TDI1,
TRST0N, TRST1N):
Low (VIL = 0 V, VDD2 = 3.6 V)
High (VIH = 3.6 V, VDD2 = 3.6 V)
IIL
IIH –100
——
5µA
µA
Output Low Voltage:
Low (IOL = 2.0 mA)
Low (IOL = 5 0 µA) VOL
VOL —
—0.4
0.2 V
V
Output High Voltage:
High (IOH = –2.0 mA)
High (IOH = –50 µA) VOH
VOH VDD2 – 0.7
VDD2 – 0.2 —
—V
V
Output 3-State Current:
Low (VDD2 = 3.6 V, VIL = 0 V)
High (VDD2 = 3.6 V, VIH = 3.6 V) IOZL
IOZH –10
——
10 µA
µA
Input Capaci tanc e CI —5pF
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
16
7 Electrical Characteristics and Requirements (continued)
Figure 3. Plot of VOH vs. IOH Under Typical Operating Conditions
Figure 4. Plot of VOL vs. IOL Under Typical Operating Conditions
5-4007(C).a
0 1.0 2.0 3.0 4.00.5 1.5 2.5 3.5 4.5 5.0
DEVICE
UNDER
TEST
IOH (mA)
VOH (V)
VDD – 0.1
VDD – 0.2
VDD – 0.3
VDD – 0.4
VDD
IOH
5-4008(C).b
DEVICE
UNDER
TEST
IOL
VOL
0.4
0.3
0.2
0.1
0
VOL (V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOL (mA)
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 17
7 Electrical Characteristics and Requirements (continued)
7.1 Maintenance of Valid Lo gic Levels for Bidirection al Signals and Unused Inp uts
The DSP16410C does not include any internal circuitry to maintain valid logic levels on input pins or on bidirec-
tional pins that are not driven. For correct device operation and low static power dissipation, valid CMOS levels
must be applied to all input and bidirectional pins. Failure to ensure full CMOS levels (VIL or VIH) on pins that are
not driven (including floating data busses) may result in high static power consumption and possible device failure.
Any unused input pin must be pulled up to the I/O pin supply (VDD2) or pulled down to VSS according to the func-
tional requirements of the pin. The pin can be pulled up or down directly or through a 10 kΩ resistor.
Any unused bidirectional pin statically configured as an input should be pulled to VDD2 or VSS through a 10 kΩ
resistor. Any bidirectional pin that is dynamically configured, such as the SEMI or PIU data busses, should be tied
to VDD2 or VSS through a pull-up/down resistor that supports the performance of the circuit. The value of the resis-
tor should be selected to avoid exceeding the dc voltage and current characteristics of any device attached to the
pin.
If the SEMI interface is unused in the system, the EYMODE pin should be connected to VDD2 to force the internal
data bus transceivers to alwa ys be in the output mode. This avoids the need to add 32 pull-up resistors to ED[31:0].
If the SEMI interface is used in the system, the EYMODE pin must be connected to VSS and pull-up or pull-down
resistors must be added to ED[31:0] as described below.
The value of the pull-up resistors used on the SEMI data bus depends on the programmed bus width, 32-bit or
16-bit, as determined by the ESIZE pin. It is recommended that any 16-bit peripheral that is connected to the e xter-
nal memory interface of the DSP16410C use the upper 16 bits of the data bus (ED[31:16]). This is required if the
e xternal memory interf ace is configured as a 16-bit interf ace . For the following configurations, 10 kΩ pull-up or pull-
down resistors can be used on the external data bus:
■32-bit SEMI with no 16-bit peripherals
■32-bit SEMI with 16-bit peripherals connected to ED[31:16]
■16-bit interface (ED[31:16] only)
If the DSP16410C’s external memory interface is configured for 32-bit operation with 16-bit peripherals on the
lower half of the external data bus (ED[15:0]), the external data bus (ED[31:0]) should hav e 2 kΩ pull-up or pull-
down resistors to meet the rise or fall time requirements of the DSP16410C*.
The different requirements for the size of the pull-up/pull-down resistors arise from the manner in which SEMI
treats 16-bit accesses if the interface is configured for 32-bit operation. If configured as a 32-bit interface and a
16-bit read is performed to a device on the upper half of the data bus, the SEMI latches the value on the upper
16 bits internally onto the lower 16 bits. This ensures that the lower half of the data bus sees valid logic levels both
in this case and also if the bus is operated as a 16-bit b us. However, if a 16-bit read operation is performed (on a
32-bit bus) to a 16-bit peripheral on the lower 16 bits, no data is latched onto the upper 16 bits, resulting in the
upper half of the bus floating. In this case the smaller pull-up resistors ensure the floating data bits transition to a
valid logic level fast enough to avoid metastability problems when the inputs are latched by the SEMI.
*The 2 k
Ω resistor value assume s a bus loading of 30 pF and also ensures IOL is not violated.
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
18
7 Electrical Characteristics and Requirements (continued)
7.2 Analog Power Supply Decoupling
Bypass and decoupling capacitors (0.01 µF, 10 µF) should be placed between the analog supply pin (VDD1A) and
analog ground (VSS1A). These capacitors should be placed as close to the VDD1A pin as possible. This minimizes
ground bounce and supply noise to ensure reliable operation. Refer to Figure 5.
Figure 5. Analog Supply Bypass and Decou pling Capacit ors
5-8896.a (F)
VSSA
VDD1A
10 µF
0.1 µF
VSS1A
DSP16410C
VDDA
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 19
7 Electrical Characteristics and Requirements (continued)
7.3 Power Dissipation
The total device power dissipation is comprised of two components:
■The contribution from the VDD1 and VDD1A supplies, referred to as internal power dissipation.
■The contribution from the VDD2 supply, referred to as I/O power dissipation.
The next two sections specify power dissipation for each component.
7.3.1 Internal Power Dissipation
Internal power dissipation is highly dependent on operating voltage, core program activity, internal peripheral activ-
ity, and CLK frequency. Table 8 lists the DSP16410C typical internal power dissipation contribution for various
conditions. The following conditions are assumed for all cases:
■VDD1 and VDD1A are both 1.575 V.
■All memory accesses by the cores and the DMAU are to internal memory.
■SIU0 and SIU1 are operating at 30 MHz in loopback mode. An external device drives the SICK〈0—1〉 and
SOCK〈0—1〉 input pins at 30 MHz, and SIU〈0—1〉 are programmed to select passive input clocks (ICKA field
(SCON10[2]) and OCKA field (SCON10[6]) are cleared) and internal loopback (SIOLB field (SCON10[8]) is set).
■The PLL is enabled and selected as the source of the internal clock, CLK. Table 8 specifies the internal power
dissipation for the following values of CLK: 185 MHz and 200 MHz.
The internal power dissipation for the low-power standby and typical operating modes described in Table 8 is repre-
sentative of actual applications. The worst-case internal power dissipation occurs under an artificial condition that
is unlikely to occur for an extended period of time in an actual application. This worst-case power should be used
for the calculation of maximum ambient operating temperature (TAMAX) defined in Section 6.3.1. This value should
also be used for worst-case system power supply design for VDD1 and VDD1A.
Table 8. Typical Internal Power Dissipation at 1.575 V
Condition Internal Power Dissipation (W)
Type Core Operation DMAU Activity 185 MHz 200 MHz
Low-power
Standby The AWAIT field (alf[15]) is set
in both cores. The DMAU is operating the
MMT4 channel to continuously
transfer data.
0.24 0.26
Typical Both cores repetitively exe-
cute a 20-tap FIR filter†.
†To optimize execution speed, the cores each execute the inner loop of the filter from cache and perform a double-word data access every
cycle from separate modules of TPRAM.
0.76 0.82
Worst Case‡
‡This is an artificial condition that is unlikely to occur for an extended period of time in an actual application because the cores are not per-
f orming any I/O servicing. In an actual application, the cores perf orm I/O servicing that changes program flow and low ers the power dissipa-
tion.
Both cores e xecute worst-case
instructions with worst-case
data patterns.
The DMAU is operating all six
channels (SWT〈0—3〉 and
MMT〈4—5〉) to continuously
transfer data.
1.37 1.48
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
20
7 Electrical Characteristics and Requirements (continued)
7.3 Power Dissipation (continued)
7.3.2 I/O Power Dissipation
I/O power dissipation is highly dependent on operating voltage, I/O loading, and I/O signal frequency. It can be
estimated as:
where CL is the load capacitance, VDD2 is the I/O supply voltage, and f is the frequency of output signal.
Table 9 lists the estimated typical I/O power dissipation contribution for each output and I/O pin for a typical applica-
tion under specific conditions. The following conditions are assumed for all cases:
■VDD2 is 3.3 V.
■The load capacitance for each output and I/O pin is 30 pF.
For applications with values of CL, VDD2, or f that differ from those assumed for Table 9, the above formula can be
used to adjust the I/O power dissipation values in the table.
Table 9. Typical I/O Power Dissipation at 3.3 V
Internal
Peripheral Pin(s) Type No. of
Pins Signal
Frequency
(MHz)
I/O Power Dissipation (mW)
185 MHz 200 MHz
SEMI†
†Assumptions: the SEMI is configured for a 32-bit external data bus (the ESIZE pin is high). The contribution from the EACKN pin is
negligible.
ED[31:0] I/O‡
‡Assumption: the pins switch from input to output at a 50% duty cycle.
32 CLK/4 242 261
ERWN[1:0] O 2 CLK/4 15 16.2
EA0 O 1 CLK/8 7.6 8.1
EA[18:1] O 18 CLK/4 273 294
ESEG[3:0] O 4 CLK/4 60 65.9
EROMN O 1 CLK/12 5.1 5.4
ERAMN O 1 CLK/12 5.1 5.4
EION O 1 CLK/12 5.1 5.4
ECKO O 1 CLK/2 30.2 32
BIO〈0—1〉IO〈0—1〉BIT[6:0] O§
§Assumption: the corresponding core has configured these pins as outputs.
14 1 4.6 4.6
PIU PD[15:0] I/O‡16 30 78.5 78.5
PINT O 1 1 0.33 0.33
PIBF O 1 30 9.8 9.8
POBE O 1 30 9.8 9.8
PRDY O 1 30 9.8 9.8
SIU〈0—1〉SICK〈0—1〉O2 8 5.2 5.2
SOCK〈0—1〉O2 8 5.2 5.2
SOD〈0—1〉O2 8 5.2 5.2
SIFS〈0—1〉O 2 0.03 0.019 0.019
SOFS〈0—1〉O 2 0.03 0.019 0.019
CLVDD22f
⋅⋅
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 21
7 Electrical Characteristic s and Requ irements (continued)
7.3 Power Dissipation (continued)
7.3.2 I/O Power Dissipation (continued)
Power dissipation due to the input buffers is highly dependent upon the input voltage level. At full CMOS le vels,
essentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the
threshold of VDD2/2, high current can flow. See Section 7.1 for more information.
WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup.
Otherwise, high currents might flow.
7.4 Power Supply Sequencing Issues
The DSP16410B requires two supply voltages. The use of dual voltages reduces internal device power consump-
tion while supporting standard 3.3 V external interfaces. The external (I/O) power supply v oltage is VDD2, the inter-
nal supply voltage is VDD1, and the internal analog supply voltage is VDD1A. VDD1 and VDD1A are typically
generated by the same power supply, with VDD1A receiving enhanced filtering near the device. In the discussion
that follows, VDD1 and VDD1A are assumed to rise and fall together, and are collectively referred to as VDD1
throughout the remainder of this section.
Power supply design is a system issue. Section 7.4.1 describes the recommended power supply sequencing spec-
ifications to av oid inducing latch-up or large currents that may reduce the long term life of the device. Section 7.4.2
discusses external power sequence protection circuits that may be used to meet the recommendations discussed
in Section 7.4.1.
7.4.1 Supply Sequencing Recommendations
Control of powerup and powerdown sequences is recommended to address the f ollo wing ke y issues. See Figure 6
and Table 10, on page 22 for definitions of the terms VSEP
, TSEPU, and TSEPD.
1. If the internal supply v oltage (VDD1) exceeds the external supply voltage (VDD2) by a specified amount, large
currents may flow through on-chip ESD structures that may reduce the long term life of the device or induce
latch-up. The difference between the internal and external supply voltages is defined as VSEP. It is recom-
mended that the value of VSEP specified in Table 10 be met during device powerup and device powerdown.
External components ma y be required to ensure this specification is met (see Section 7.4.2).
2. During powerup, if the external supply voltage (VDD2) exceeds a specified voltage (1.2 V) and the internal sup-
ply voltage (VDD1) does not reach a specified voltage (0.6 V) within a specified time interv al (TSEPU), large cur-
rents may flow through the I/O buffer transistors. This is because the I/O buffer transistors are powered by
VDD2 but their control transistors powered by VDD1 are not at valid logic levels. If the requirement for TSEPU
cannot be met, external components are recommended (see Section 7.4.2).
3. During powerdown, if the internal supply voltage (VDD1) f alls below a specified v oltage (0.6 V) and the external
supply voltage (VDD2) does not fall below a specified voltage (1.2 V) within a specified time interval (TSEPD),
large currents may flow through the I/O buffer transistors. This is because the control transistors (powered by
VDD1) for the I/O buff er transistors are no longer at valid logic le v els while the I/O buff er transistors remain pow-
ered by VDD2. If the require men t for TSEPD cannot be met, external components are recommended (see
Section 7.4.2).
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
22
7 Electrical Characteristic s and Requ irements (continued)
7.4 Power Supply Sequencing Issues (continued)
7.4.1 Supply Sequencing Recommendations (continued)
Figure 6. Power Supply Sequencing Recommendations
Tabl e 10. Power Sequencing Recommendations
Parameter Value Description
VSEP –0.6 V < VSEP Difference between VDD2 and VDD1 supplies.
VSEP = VDD2 – VDD1. VSEP constraint must be satisfied for the
entire duration of power-on and power-off supply ramp.
TSEPU 0 ≤ TSEPU < 50 ms Time after VDD2 supply reaches 1.2 V and before VDD1 supplies
reach 0.6 V.
TSEPD 0 ≤ TSEPD < 100 ms Time after VDD1 supplies reach 0.6 V and before VDD2 reache s
1.2 V.
TSEPU
VSEP
0.6 V
1 V
2 V
3 V
VDD1 (INTERNAL)
1.2 V
dc POWER SUPPLY VOLTAGE
TIME
VDD2 (EXTERNAL SUPPLY)
VSEP
TSEPD
0930 (F)
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 23
7 Electrical Characteristic s and Requ irements (continued)
7.4 Power Supply Sequencing Issues (continued)
7.4.2 External Power Sequence Protection Circuits
This section discusses external power sequence protection circuits which may be used to meet the recommenda-
tions discussed in Section 7.4.1. For the purpose of this discussion, the dual supply configuration of Figure 7 will
be used. The recommendations for this series supply system apply to parallel supply configurations where a com-
mon power bus simultaneously controls both the internal and external supplies.
1563.a(F)
Figure 7. Power Supply Example
Figure 7 illustrates a typical supply configuration. The external power regulator provides power to the internal
power regulator.
Use of schottky diode D1 to bootstrap the VDD2 supply from the VDD1 supply is recommended. D1 ensures that the
VSEP recommendation is met during device powerdown and powerup. In addition, D1 protects the DSP16410C
from damage in the event of an external power regulator failure.
Diode network D0, which may be a series of diodes or a single zener diode, bootstraps the VDD1 supply. After
VDD2 is a fixed voltage abov e VDD1 (2.4 V as determined by D0), the VDD2 supply will power VDD1 until D0 is cut
off as VDD1 achie v es its operating v oltage. If TSEPU/TSEPD recommendations are met, D0 is not required. Si nce D 0
protects the DSP16410C from damage in the event of an internal supply failure and reduces TSEPU, use of D0 is
recommended. To ensure D0 cutoff during normal system operation, D0’s forward v oltage (VF) shoul d be 2.4 V. D0
should be selected to ensure a minimum VDD1 of 0.8 V under DSP load.
EXTERNAL INTERNAL
SYSTEM
POWER BUS
VDD2
VDD1
2.4 V
D0
D1
POWER POWER
DSP1640C
REGULATOR REGULATOR
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
24
8 Timing Characteristics and Requirements
Timing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to
conditions imposed on the user for proper operation of the device. All timing data is valid for the following condi-
tions:
TJ = –40 °C to +120 °C (See Section 6.3, on page 14).
VDD2 = 3.3 V ± 0.3 V, VSS = 0 V (See Section 6.3, on page 14).
Capacitance load on outputs (CL) = 30 pF.
Output characteristics can be derated as a function of load capacitance (CL).
All outputs: 0.025 ns/pF ≤ dt/dCL ≤ 0.07 ns/pF for 10 ≤ CL ≤ 100 pF.
For e xample, if the actual load capacitance on an output pin is 20 pF instead of 30 pF, the maximum derating for a
rising edge is (20 –30) pF x 0.07 ns/pF = 0.7 ns less than the specified rise time or delay that includes a rise time.
The minimum derating for the same 20 pF load would be (20 –30) pF x 0.025 ns/pF = 0.25 ns.
Test conditions for inputs:
■Rise and fall t imes of 4 ns or less.
■Timing reference levels for CKI, RSTN, TRST0N, TRST1N, TCK0, and TCK1 are VIH and VIL.
■Timing reference level for all other inputs is VM. (See Table 11.)
■Test conditions for outputs (unless noted otherwise):
■CLOAD = 30 pF.
■Timing reference levels for ECKO ar e VOH and VOL.
■Timing reference level for all other outputs is VM.
■3-state delays measured to the high-impedance state of the output driver.
Unless otherwise noted, ECKO in the timing diagrams is the free-running CLK (ECON1[1:0] = 1).
Figure 8. Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs
Table 11. Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs
Abbreviated Reference Parameter Value Unit
VMReference Voltage Level for Timing Characteristics
and Requirements for Inputs and Outputs 1.5 V
V
M
–
5-8215 (F)
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 25
8 Timing Characteristics and Requirements (continued)
8.1 Phase-Lock Loop
8.2 Wake-Up Latency
Table 13 specifies the wake-up latency for the low-power standby mode. The wake-up latency is the delay between
exiting low-power standby mode and resumption of normal execution.
Table 12. PLL Requirements
Parameter Symbol Min Max Unit
VCO Frequency Range
(VDD1A = 1.575 V) fVCO 200 500 MHz
Input Jitter at CKI ——200 ps-rms
PLL Lock Time tL—0.5 ms
CKI Frequency with PLL Enabled fCKI 640MHz
CKI Frequency with PLL Disab led fCKI 050MHz
fCKI/(D† + 2)
†D is the PLL input divider and is defined by pllfrq[13:9].
—320MHz
Table 13. Wake-Up Latency
Condition Wake-Up Latency
(PLL Deselected† During
Normal Execution)
†The PLL is deselected if the PLLSEL field (pllcon[0]) is cleared, which is the default after reset. T he PLL is selected if the PLLSEL field
(pllcon[0]) is set.
(PLL Enabled‡ and Selected†
During Normal Execution)
Low-powe r Sta ndb y Mode
(AWAIT (alf[15]) = 1) PLL Disabled‡
During Standby
‡The PLL is disabl ed (powered down) if the PLLEN field (pllcon[1]) is cleared, which is the default after reset. The PLL is enabled (powered
up) if the PLLEN field (pllcon[1 ]) is set.
3T§
§T = CLK clock cycle (fCLK = fCKI if PLL deselected; fCLK = fCKI * ((M + 2)/((D + 2) * f(OD))) if PLL enabled and selected).
3T§ + tL††
††tL = PLL lock-in time (see Table 12).
PLL Enabl ed‡
During Standby 3T§3T§
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
26
8 Timing Characteristics and Requirements (continued)
8.3 DSP Clock Generation
Figure 9. I/O Clock Timing Diagram
Table 14. Timing Requirements for Input Clock
Abbreviated Reference Parameter Min Max Unit
t1†
†For timing requirements shown, it is assumed that CKI (not the PLL output) is selected as inter nal clock source. If
the PLL is selected as the internal clock source, the minimum required CKI period is 25 ns and the maximum
required CKI period is 167 ns.
Clock In Period (high to high) 20 —‡
‡Device is fully static, t1 is tested at 100 ns input clock option, and memory hold time is tested at 0.1 s.
ns
t2 Clock In Low Time (low to high) 10 —ns
t3 Clock In High Time (high to low) 10 —ns
Table 15. Timing Characteristics for Input Clock and Output Clock
Abbreviated Reference Parameter Min Max Unit
t4 Clock Out High Delay (lo w to low) —10 ns
t5 Clock Out Low Delay (high to high) —10 ns
t6 Clock Out Period (high to high) T†
†T = internal clock period (CLK).
—ns
5-4009(F).i
t4
t6
t1
t2
CKI
t5
ECKO
t3
VIH–
VIL–
VOH–
VOL–
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 27
8 Timing Characteristics and Requirements (continued)
8.4 Reset Circuit
The DSP16410C has three external reset pins: RSTN, TRST0N, TRST1N. At initial powerup or if any supply volt-
age (VDD1, VDD1A, or VDD2) falls below VDD MIN*, a device reset is required and RSTN, TRST0N, TRST1N must
be asserted simultaneously to initialize the device.
Note: The TRST0N and TRST1N pins must be asserted even if the JTAG controller is not used by the application.
†When both INT0 and RSTN are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a
3-state condition. With RSTN asserted and INT0 not asserted, EION, ERAMN, EROMN, EACKN, ERWN0, and ERWN1 outputs are driven
high. EA[18:0], ESEG[3:0], and ECKO are driven low.
Figure 10. Powerup and Device Reset Timing Diagram
Note: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high cur-
rents ma y flow.
* See Table 5 on page 14.
Table 16. Timing Requirements for Powerup and Device Reset
Abbreviated Reference Parameter Min Max Unit
t8 RSTN, TRST0N, and TRST1N Reset Pulse (low to high) 7T†
†T = internal clock period (CKI).
—ns
t146 VDD1, VDD1A MIN to RSTN, TRST0N, and TRST1N Low 2T†—ns
t153 RSTN, TRST0N, and TRST1N Rise (low to high) —60 ns
Table 17. Timing Characteri stics for Device Reset
Abbreviated Reference Parameter Min Max Unit
t10 RSTN Disable Time (low to 3-state) —50 ns
t11 RSTN Enable Time (high to valid) —50 ns
5-4010(F).r
VDD1,
VDD1A
RSTN,
TRST0N,
OUTPUT
PINS †
CKI
t11
VOH
VOL
VIH
VIL
t146
t10
t153
t8
VDD MIN
TRST1N
RAMP
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
28
8 Timing Characteristics and Requirements (continued)
8.5 Reset Synchronization
Note: See Sec tion 8.9 for timing characteristics of the EROMN pin.
Figure 11. Reset Synchronization Timing
Table 18. Timing Requirements for Reset Synchronization Timing
Abbreviated Reference Parameter Min Max Unit
t126 Reset Setup (high to high) 3 T/2 – 1†
†T = internal clock period (CKI).
ns
t24 CKI to Enable Valid 4T + 0.5 4T + 4 ns
5-4011(F).i
CKI
EROMN
t126
t24
RSTN
(EXM = 1)
VIH–
VIL–
VIH–
VIL–
FETCH OF FIRST
INSTR UCTION BEGINS
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 29
8 Timing Characteristics and Requirements (continued)
8.6 JTAG
Figure 12. JTAG I/O Timing Diagram
Table 19. Timing Requirements for JTAG I/O
Abbreviated Reference Parameter Min Max Unit
t12 TCK Period (high to high) 50 —ns
t13 TCK High Time (high to low) 22.5 —ns
t14 TCK Low Time (low to high) 22.5 —ns
t155 TCK Rise Transition Time (low to high) 0.6 —V/ns
t156 TCK Fall Transition Time (high to low) 0.6 —V/ns
t15 TMS Setup Time (valid to high) 7.5 —ns
t16 TMS Hold Time (high to invalid) 5 —ns
t17 TDI Setup Time (valid to high) 7.5 —ns
t18 TDI Hold Time (high to invalid) 5 —ns
Table 20. Timing Characteri stics for JTAG I/O
Abbreviated Reference Parameter Min Max Unit
t19 TDO Delay (low to valid) —15 ns
t20 TDO Hold (low to invalid) 0 —ns
5-4017(F).d
t12
t14t13
t15 t16
t17 t18
t19
t20
TCK0, TCK1
TMS0, TMS1
TDI0 , TDI1
TDO0, TD01
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
t155
t156
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
30
8 Timing Characteristics and Requirements (continued)
8.7 Interrupt and Trap
†ECKO is free-running.
‡INT is one of INT[3:0] or TRAP.
Figure 13. Interrupt and Trap Timing Diagram
Table 21. Timing Requirements for Interrupt and Trap
Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.
Abbreviated Reference Parameter Min Max Unit
t21 Interrupt Setup (high to low) 8 —ns
t22 INT/TRAP Assertion Time (high to low) 2T†
†T = internal clock period (CLK).
—ns
5-4018(F).g
INT‡
t21
t22
ECKO†VOH–
VOL–
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 31
8 Timing Characteristics and Requirements (continued)
8.8 Bit I/O
Figure 14. Write Outputs Followed by Read Inputs (cbit = IMMEDIATE; a1 = sb it) Timin g Charact eri stics
Table 22. Timing Requirements for BIO Input Read
Abbreviated Reference Parameter Min Max Unit
t27 IOBIT Input Setup Time (valid to low) 10 —ns
t28 IOBIT Input Hold Time (low to invalid) 0 —ns
Table 23. Timing Characteri stics for BIO Output
Abbreviated Reference Parameter Min Max Unit
t29 IOBIT Output Valid Time (high to valid) —9ns
t144 IOBIT Output Hold Time (high to invalid) 1 —ns
5-4019(F).c
ECKO
IOBIT
(INPUT)
t28
t27
VALID OUTPUT
VOH–
VOL–
DATA INPUT
t29
t144
IOBIT
(OUTPUT)
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
32
8 Timing Characteristics and Requirements (continued)
8.9 System and External Memor y Interfa ce
In the following timing diagrams and associated tables:
■The designation ENABLE refers to one of the follo wing pins: EROMN, ERAMN, or EION. The designation
ENABLES refers to all of the following pins: EROMN, ERAMN, and EION.
■The designation ERWN refers to the following:
—The ERWN0 pin if the external data bus is configured as 16 bits, i.e., if the ESIZE pin is logic low.
—The ERWN1 and ERWN0 pins if the external data bus is configured as 32 bits, i.e., if the ESIZE pin is logic
high.
—The ERWN1, ERWN0, and EA0 pins if the external data bus is configured as 32 bits, i.e., if the ESIZE pin is
logic high, and if the memory access is synchronous.
■The designation EA refers to the following:
—The e xternal address pins EA[18:0] and the e xternal segment address pins ESEG[3:0] if the e xternal data bus
is configured as 16 bits, i.e., if the ESIZE pin is logic low.
—The e xternal address pins EA[18:1] and the e xternal segment address pins ESEG[3:0] if the e xternal data bus
is configured as 32 bits, i.e., if the ESIZE pin is logic high.
■The designation ED refers to the following:
—The external data pins ED[31:16] if the external data bus is configured as 16 bits, i.e., if the ESIZE pin is logic
low.
—The external data pins ED[31:0] if the e xternal data bus is configured as 32 bits, i.e., if the ESIZE pin is logic
high.
■The designation ATIME refers to IATIME (ECON0[11:8]) for accesses to the EIO space, YATIME (ECON0[7:4])
for accesses to the ERAM space, or XATIME (ECON0[3:0]) for accesses to the EROM space.
†ECKO reflects CLK, i.e., ECON1[1: 0 ] = 1.
Figure 15. Enable and Write Strobe Transition Timing
Table 24. Timing Characteristics for Memory Enables and ERWN
Abbreviated
Reference Parameter Min Max Unit
t102 ECKO to ENABLE Active (high to low) 0.5 4 ns
t103 ECKO to ENABLE Inactive (high to high) 0.5 4 ns
t112 ECKO to ERWN Active (high to low) 0.5 4 ns
t113 ECKO to ERWN Inactive (high to high) 0.5 4 ns
ENABLE
t102
ERWN
t113
t112
t103
ECKO†VOH–
VOL–
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 33
8 Timing Characteristics and Requirements (continued)
8.9 System and External Memor y Interfa ce (continued)
8.9.1 Asynchronous Interface
†ECKO reflects CL K, i.e., ECON1[1:0] = 1.
Figure 16. Timing Diagram for EREQN and EACKN
Tabl e 25. Timing Requirements for EREQN
Abbreviated
Reference Parameter Min Max Unit
t122 EREQN Setup (low to high or high to high) 5 —ns
t129 EREQN Deassertion (high to low) ATIMEMAX†
†ATIMEMAX = the greatest of IATIME(ECON0[11:8]), YATIME (ECON0[7:4]), and XTIME (ECON0[3:0]}.
—ns
Table 26. Timing Characteristics for EACKN and SEMI Bus Disable
Abbreviated
Reference Parameter Min Max Unit
t123 Memory Bus Disable Delay (high to 3-state) —6ns
t124 EACKN Assertion Delay† (high to low)
†If any ENABLE is asser ted (low) when EREQN is asserted (low), then the delay occurs from the time that ENABLE is deasserted (high).
(The SEMI does not acknowledge the request by asserting EACKN until it has completed any pending memor y accesses.)
4T‡—ns
t125 EACKN Deassertion Delay (high to high) 4T‡
‡T = internal clock period (CLK).
4T‡ + 3 ns
t127 Memory Bus Enable Delay (high to active) 5 —ns
t128 EACKN Delay (high to low) —3ns
ECKO†
EREQN
ED
ENABLES
EA
VOH–
VOL–
EACKN
t122
t123
t124
t122
t125
t129
t128
t127
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
34
8 Timing Characteristics and Requirements (continued)
8.9 System and External Memor y Interfa ce (continued)
8.9.1 Asynchronous Interface (continued)
†ECKO reflects CLK, i.e., ECON1[1: 0 ] = 1.
Figure 17. Asynchronous Read Timing Diagram (RHOLD = 0 and RSETUP = 0)
Note: The external memory access time from the assertion of ENABLE can be calculated as t90 – (t91 + t92).
Table 27. Timing Requirements for Asynchronous Memory Read Operations
Abbreviated
Reference Parameter Min Max Unit
t92 Read Data Setup (valid to ENABLE high) 5 —ns
t93 Read Data Hold (ENABLE high to invalid) 0 —ns
Table 28. Timing Characteristics for Asynchronous Memory Read Operations
Abbreviated
Reference Parameter Min Max Unit
t90 ENABLE Width (low to high) (T† × ATIME) – 3
†T = internal clock period (CLK).
—ns
t91 Add ress Delay
(ENABLE low to valid) —2 – (T† × RSETUP‡)
‡RSETUP = ECON0[12].
ns
t95 ERWN Activation
(ENABLE high to ERWN low) T† × (1 + RHOLD§ +
WSETUP††) – 3
§RHOLD = ECON0[14].
††WSETUP = ECON0[13].
——
ENABLE
ED
ECKO†
EA
t91
READ ADDRESS
ATIME = 3
t90
t92 t93
READ DATA
ERWN
t95
VOH–
VOL–
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 35
8 Timing Characteristics and Requirements (continued)
8.9 System and External Memor y Interfa ce (continued)
8.9.1 Asynchronous Interface (continued)
†ECK O reflects CLK, i.e., ECON1[1 : 0 ] = 1.
‡The stall cycle is caused by the read following the write.
Figure 18. Asynchronous Write Timing Diagram (WHOLD = 0, WSETUP = 0)
Table 29. Timing Characteristics fo r Asynchronous Memory Write Operations
Abbreviated
Reference Parameter Min Max Unit
t90 ENABLE Width (low to high) (T† × ATIME) – 3
†T = internal clock period (CLK).
—ns
t96 Enable Delay (ERWN high to ENABLE low) T† × (1 + WHOLD‡ + RSETUP §) – 3
‡WHOLD = ECON0[15].
§RSETUP = ECON0[12].
—ns
t97 Write Data Setup (valid to ENABLE high) (T† × ATIME) – 3 —ns
t98 Write Data Deactivation (ERWN high to 3-state) —3ns
t99 Write Address Setup (valid to ENABLE low) T† × (1 + WS ETUP††) – 3
††WSETUP = ECON0[13].
—ns
t100 Write Data Activation (ERWN low to low-Z) T† – 2 —ns
t101 Address Hold Time (ENABLE high to invalid) T† × (1 + WHOLD‡) – 3 —ns
t114 Write Data H old Time (ENABLE high to invalid) T – 3 —ns
ECKO†
WRITE DATA READ DATA
t98
t100
ATIME = 2 ATIME = 2
t90
t97
t96
WRITE ADDRESS READ ADDRESS
ENABLE
ED
ERWN
EA
VOH–
VOL–
t99
t114
STALL‡
t101
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
36
8 Timing Characteristics and Requirements (continued)
8.9 System and External Memor y Interfa ce (continued)
8.9.2 Synchronous Interfac e
†ECKO reflects CLK/2, i.e., ECON1[1:0] = 0.
Figure 19. Synchronous Read Timing Diagram (Read-Read-Write Sequence)
Table 30. Timing Requirements for Synchronous Read Operations
Abbreviated
Reference Parameter Min Max Unit
t104 Read Data Setup (valid to high) 4 —ns
t105 Read Data Hold (high to invalid) 1 —ns
Table 31. Timing Characteristics for Synchronous Read Operations
Abbreviated
Reference Parameter Min Max Unit
t102 ECKO to ENABLE Active (high to low) 0.5 4 ns
t103 ECKO to ENABLE Inactive (high to high) 0.5 4 ns
t106 Address Delay (high to valid) —2.5 ns
t107 Address Hold (high to invalid) 0.5 —ns
t108 Write Data Active (high to low-Z) T† – 3
†T = internal clock period (CLK).
—ns
ENABLE
ED
ECKO†
EA
READ DATA
ERWN
WRITE DATA
t102
t106
t103
t104
t107
t108
t105
VOH–
VOL–
READ ADDRESS READ ADDRESS WRITE ADDRESS
READ DATA
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 37
8 Timing Characteristics and Requirements (continued)
8.9 System and External Memor y Interfa ce (continued)
8.9.2 Synchronous Interfac e (continued)
†ECKO re fl ec t s C L K/ 2 , i .e., ECON1[1:0] = 0.
Figure 20. Synchronous Write Timing Diagram
Table 32. Timing Characteristics for Synchronous Write Operations
Abbreviated
Reference Parameter Min Max Unit
t102 ECKO to ENABLE Active (high to low) 0.5 4 ns
t103 ECKO to ENABLE Inactive (high to high) 0.5 4 ns
t106 Address Delay (high to valid) —2.5 ns
t107 Address Hold (high to invalid) 0.5 —ns
t109 Write Data Delay (high to valid) —2.5 ns
t110 Write Data Hold (high to invalid) 0.5 —ns
t111 Write Data Deactivation Delay (high to 3-state) —2.5 ns
t112 ECKO to ERWN Active (high to low) 0.5 4 ns
t113 ECKO to ERWN Inactive (high to high) 0.5 4 ns
t109 t110
DATA
ADDRESS
ENABLE
ED
EA
ERWN
t102 t103
t111
t107
t106
t112 t113
ECKO†VOH–
VOL–
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
38
8 Timing Characteristics and Requirements (continued)
8.9 System and External Memor y Interfa ce (continued)
8.9.3 ERDY Interface
†ECKO reflects CLK, i.e., ECON1[1: 0 ] = 1.
‡ATIME must be programmed as greater than or equal to five CLK cyc les. Ot herwise, the SEMI ignores the state of ERDY.
§T = internal clock period (CLK). N must be greater than or equal to one, i.e., ERDY must be held low for at least one CLK cycle after the
SEMI samples ERDY.
Figure 21. ERDY Pin Timing Diagram
As indicated in the drawing, the SEMI:
■Samples the state of ERDY at 4T prior to the end of the access (unstalled). (The end of the access (unstalled)
occurs at ATIME cycles after ENABLE goes low.)
■Ignores the state of ERDY before the ERDY sample point.
■Stalls the external memory access by N × T cycles, i.e., by the number of cycles that ERDY is held low following
the ERDY sample point.
Table 33. Timing Requirements for ERDY Pin
Abbreviated
Reference Parameter Min Max Unit
t115 ERDY Setup to any ECKO (low to high or high to high) 5 —ns
t121 ERDY Setup to ECKO at End of Unstalled Access (low to high) 4T + 5 —ns
ENABLE
ERDY
t115
4T
§
t115
N × T
§
SEMI
SAMPLES
ERDY PIN
ECKO
†
VOH–
VOL–
ATIME
‡
END OF
ACCESS
(UNSTALLED)
N × T
§
t121
4T
§
END OF
ACCESS
(STALLED)
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 39
8 Timing Characteristics and Requirements (continued)
8.10 PIU
†PSTRN is the logical OR of the PCSN input pin wit h the exclusiv e NOR of the PIDS and PODS input pins, i.e., PS TRN = PCSN |(PIDS ^ PODS).
‡It is assumed that the PRDYMD pin is logic low, configuring the PRDY pin as active-low.
Figure 22. Host Data Write to PDI Timing Diagram
Table 34. Timing Requirements for PIU Data Write Operations
Abbreviated Reference Parameter Min Max Unit
t60 PSTRN Pulse Width (high to low or low to high) max (2T†, 15)
†T is the period of the inter nal clock (CLK).
—ns
t61 PADD Setup Time‡ (valid to low)
‡Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last .
5 —ns
t62 PADD Hold Time‡ (low to invalid) 5 —ns
t63 PD Setup Time§ (valid to high)
§Time to the rising edge of PIDS, PODS, or PCSN, whichev er occurs first.
6—ns
t64 PD Hold Time§ (high to invalid) 5 —ns
t65 PSTRN Request Period (low to low) max (5T†, 30) —ns
t66 PRWN Setup Time‡ (low to low) 0 —ns
t67 PRWN Hold Time§ (high to high) 0 —ns
t74 PSTRN Hold (low to high) 1 —ns
Table 35. Timing Characteristics for PIU Data Write Operations
Abbreviated Reference Parameter Min Max Unit
t68 PIBF Delay† (high to high)
†Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first.
112ns
t69 PRDY Delay (low to valid) 1 12 ns
5-7850 (F)
PSTRN†
PADD[3:0]
PRWN
PD[15:0]
PIBF
PRDY‡
t65
t60 t60
t61 t62
t74
t67
t64t63
t68
t69
t66
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
40
8 Timing Characteristics and Requirements (continued)
8.10 PIU (continued)
†PSTRN is the logical OR of the PCSN input pin wit h the exclusiv e NOR of the PIDS and PODS input pins, i.e., PS TRN = PCSN | (PIDS ^ PODS).
‡It is assumed that the PRDYMD pin is logic low, configuring the PRDY pin as active-low.
Figure 23. Host Data Read from PDO Timing Diagram
Table 36. Timing Requirements for PIU Data Read Operations
Abbreviated
Reference Parameter Min Max Unit
t60 PSTRN Pulse Width (high to low or low to high) max (2T†, 15)
†T is the period of the inter nal clock (CLK).
—ns
t61 PADD Setup Time‡ (valid to low)
‡Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last .
5 —ns
t62 PADD Hold Time‡ (low to invalid) 5 —ns
t65 PSTRN Request Period (low to low) max (5T†, 30) —ns
t74 PSTRN Hold (low to high) 1 —ns
Table 37. Timing Characteristics for PIU Data Read Operations
Abbreviated
Reference Parameter Min Max Unit
t69 PRDY Delay (low to valid) 1 12 ns
t70 POBE, PRDY Delays (valid to low) T – 3Tns
t71 PD Activation Delay† (low to low-Z)
†Delay from the falling edge of PIDS, PODS, or PCSN, whiche ver occurs last.
16ns
t72 POBE Delay‡ (high to high) 1 12 ns
t73 PD Deactivation Delay‡ (high to 3-state)
‡Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first.
112ns
5-7851 (F)
PSTRN†
PADD[3:0]
PD[15:0]
POBE
PRDY‡
t65
t60 t60
t61 t62
t73t71
t72t70
t74
t69
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 41
8 Timing Characteristics and Requirements (continued)
8.10 PIU (continued)
†PSTRN is the logical OR of the PCSN input pin wit h the exclusiv e NOR of the PIDS and PODS input pins, i.e., PS TRN = PCSN |(PIDS ^ PODS).
‡It is assumed that the PRDYMD pin is logic low, configuring the PRDY pin as active-low.
Figure 24. Host Register Write (PAH, PAL, PCON, or HSCRATCH) Timing Diagram
Table 38. Timing Requirements for PIU Register Write Operations
Abbreviated Reference Parameter Min Max Unit
t60 PSTRN Pulse Width (high to low or low to high) max (2T†, 15)
†T is the period of the inter nal clock (CLK).
—ns
t61 PADD Setup Time‡ (valid to low)
‡Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last .
5 —ns
t62 PADD Hold Time‡ (low to invalid) 5 —ns
t63 PD Setup Time§ (valid to high)
§Time to the rising edge of PIDS, PODS, or PCSN, whichev er occurs first.
6—ns
t64 PD Hold Time§ (high to invalid) 5 —ns
t65 PSTRN Request Period (low to low) max (5T†, 30) —ns
t66 PRWN Setup Time‡ (low to low) 0 —ns
t67 PRWN Hold Time§ (high to high) 0 —ns
t74 PSTRN Hold (low to high) 1 12 ns
Table 39. Timing Characteristics for PIU Register Write Operations
Abbreviated Reference Parameter Min M ax Unit
t68 PIBF Delay† (high to high)
†Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first.
112ns
t69 PRDY Delay (low to valid) 1 12 ns
5-7850 (F)
PSTRN†
PADD[3:0]
PRWN
PD[15:0]
PIBF
PRDY‡
t65
t60 t60
t61 t62
t74
t67
t64t63
t68
t69
t66
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
42
8 Timing Characteristics and Requirements (continued)
8.10 PIU (continued)
†PSTRN is the logical OR of the PCSN input pin wit h the exclusiv e NOR of the PIDS and PODS input pins, i.e., PS TRN = PCSN | (PIDS ^ PODS).
Figure 25. Host Register Read (PAH, PAL, PCON, or DSCRATCH) Timing Diagram
Table 40. Timing Requirements for PIU Register Read Operations
Abbreviated
Reference Parameter Min Max Unit
t60 PSTRN Pulse Width (high to low or low to high) max (2T†, 15)
†T is the period of the inter nal clock (CLK).
—ns
t61 PADD Setup Time‡ (valid to low)
‡Time to the falling edge of PIDS, PODS, or PCSN, whichever occurs last .
5—ns
t62 PADD Hold Time‡ (low to invalid) 5 —ns
t65 PSTRN Request Period (low to low) max (5T†, 30) —ns
Table 41. Timing Characteristics for PIU Register Read Operations
Abbreviated
Reference Parameter Min Max Unit
t71 PD Activation Delay† (low to low-Z)
†Delay from the falling edge of PIDS, PODS, or PCSN, whiche ver occurs last.
16ns
t73 PD Deactivation Delay‡ (high to 3-state)
‡Delay from the rising edge of PIDS, PODS, or PCSN, whichever occurs first.
112ns
t75 PD Delay† (low to valid) —16 ns
5-7853 (F)
PSTRN†
PADD[3:0]
PD[15:0]
t65
t60 t60
t61 t62
t73t71
t75
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 43
8 Timing Characteristics and Requirements (continued)
8.11 SIU
Note: It is assumed that the SIU is configured with ICKA( SCON10[2]) = 0 for passiv e mode input cloc k, ICKK(SCON10[3]) = 0 for no in v ersion
of SICK, IFSA(SCON10[0]) = 0 for passiv e mode input frame sync, IFSK(SCON10[1]) = 0 for no inv ersion of SIFS, IMSB(SCON0[2]) = 0
for LSB-first input, and IFSDLY[1:0](SCON1[9:8]) = 00 for no input frame sync delay.
Figure 26. SIU Passive Frame and Channel Mode Input Timing Diagram
Table 42. Timing Requirements for SIU Passive Fra me Mode Input
Abbrevia ted Refer ence Par ameter Min Max Unit
t30 SICK Bit Clock Period (high to high) 25 —ns
t31 SICK Bit Clock High Time (high to low) 10 —ns
t32 SICK Bit Clock Low Time (low to high) 10 —ns
t33 SIFS Hold Time (high to low or high to high) 10 —ns
t34 SIFS Setup Time (low to high or high to high) 10 —ns
t35 SID Setup Time (valid to low) 5 —ns
t36 SID Hold Time (low to inv alid) 8 —ns
Table 43. Timing Requirements for SIU Passive Channel Mode Input
Abbrevia ted Refer ence Par ameter Min Max Unit
t30 SICK Bit Clock Period (high to high) 61.035 —ns
t31 SICK Bit Clock High Time (high to low) 28 —ns
t32 SICK Bit Clock Low Time (low to high) 28 —ns
t33 SIFS Hold Time (high to low or high to high) 10 —ns
t34 SIFS Setup Time (low to high or high to high) 10 —ns
t35 SID Setup Time (valid to low) 5 —ns
t36 SID Hold Time (low to inv alid) 8 —ns
5-8033 (F)
t30
t31 t32
t34
SICK
SIFS
SID B0 B1 B2
t34 t33
t35
t36
t33
B0
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
44
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 0 for passive mode output clock, OCKK(SCON10[7]) = 0 for no in v er-
sion of SOCK, OFSA(SCON10[4]) = 0 for passive mode output frame sync, OFSK(SCON10[5]) = 0 for no inv ersion of SOFS,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY[ 1:0](SCON2[ 9 :8]) = 00 for
no output frame sync delay.
Figure 27. SIU Passive Frame Mode Output Timing Diagram
Table 44. Timing Requirements for SIU Passive Frame Mode Output
Abbreviated Reference Parameter Min Max Unit
t37 SOCK Bit Clock Period (high to high) 25 —ns
t38 SOCK Bit Clock High Time (high to low) 10 —ns
t39 SOCK Bit Clock Low Time (low to high) 10 —ns
t40 SOFS Hold Time (high to low or high to high) 10 —ns
t41 SOFS Setup Time (low to high or high to high) 10 —ns
Table 45. Timing Characteristics for SIU Passive Frame Mode Output
Abbreviated Reference Parameter Min Max Unit
t42 SOD Delay (high to valid) 1 16 ns
t43 SOD Hold (high to inva lid) 0 4 ns
5-8034 (F)
t37
t38 t39
t42
SOCK
SOFS
SOD B0 B1
t43
B0
t40
t41
t40
t41
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 45
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 0 for passive mode output clock, OCKK(SCON10[7]) = 0 for no in v er-
sion of SOCK, OFSA(SCON10[4]) = 0 for passive mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOFS,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7] ) = 0 for channel mode output, and OFSDLY[1:0](SCON2[9:8]) = 00 f or
no output frame sync delay.
Figure 28. SIU Passive Channel Mode Output Timing Diagram
Table 46. Timing Requirements for SIU Passive Channel Mode Output
Abbreviated Reference Parameter Min Ma x Unit
t37 SOCK Bit Clock Period (high to high) 61.035 —ns
t38 SOCK Bit Clock High Time (high to low) 28 —ns
t39 SOCK Bit Clock Low Time (low to high) 28 —ns
t40 SOFS Hold Time (high to low or high to high) 10 —ns
t41 SOFS Setup Time (low to high or high to high) 10 —ns
Table 47. Timing Characteristics for SIU Passive Channel Mode Output
Abbreviated Reference Parameter Min Max Unit
t42 SOD Delay (high to valid) 1 16 ns
t43 SOD Hold (high to inva lid) 0 4 ns
t44 SOD Deactivation Delay (high to 3-state) —12 ns
5-8032 (F)
t37
t38 t39
t42
SOCK
SOFS
SOD B0 B1
t43
B0
t40
t41
t40
t41
t44
B1
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
46
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
Figure 29. SCK External Clock Source Input Timing Diagram
Table 48. Timing Requirements for SCK External Clock Source
Abbreviated
Reference Parameter Min Max Unit
t52 SCK Bit Clock Period (high to high) 25 —ns
t53 SCK Bit Clock High Time (high to low) 10 —ns
t54 SCK Bit Clock Low Time (low to high) 10 —ns
t52
t53 t54
SCK
5-8037 (F)
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 47
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
Note: It is assumed that the SIU is configured with ICKA(SCON10[2]) = 1 for activ e mode input clock, ICKK(SCON10[3] ) = 0 f or no i nv er sion of
SICK, IFSA(SCON10[0]) = 1 for active mode input frame sync, IFSK(SCON10[1]) = 0 for no inversion of SIFS, IMSB(SCON0[2]) = 0 f or
LSB-first input, and IFSDLY[1:0](SCON1[9:8]) = 00 for no input frame sync delay.
Figure 30. SIU Active Frame and Channel Mode Input Timing Diagram
Table 49. Timing Requirements for SIU Active Frame Mode Input
Abbreviated
Reference Parameter Min Max Unit
t45 SICK Bit Clock Period (high to high) 25†
†The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the A GEXT field (SCON12[12]). The
period of SICK is dependent on the period of the active clock source and the program ming of the AGCKLIM[7:0] field (SCON11[7:0]). The
application must ensure that the period of SICK is at least 25 ns.
—ns
t49 SID Setup Time (valid to low) 9 —ns
t50 SID Hold Time (low to invalid) 8 —ns
Table 50. Timing Characteristics for SIU Active Frame Mode Input
Abbreviated
Reference Parameter Min Max Unit
t46 SICK Bit Clock High Time (high to low) TAGCKH†–3
†TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source.
TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin,
depending on the AGEXT field (SCON12[12]).
TAGCKH†+3 ns
t47 SICK Bit Clock Low Time (low to high) TAGCKL†–3T
AGCKL†+3 ns
t48 SIFS Delay (high to high) TCKAG†–5T
CKAG†+5 ns
5-8029 (F)
t45
t46 t47
t48
SICK
SIFS
SID B0 B1 B2
t49
t50
B0
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
48
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
Table 51. Timing Requirements for SIU Active Channel Mode Input
Abbreviated
Reference Parameter Min Max Unit
t45 SICK Bit Clock Period (high to high) 61.035†
†The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). The
period of SICK is dependent on the period of the active clock source and the program ming of the AGCKLIM[7:0] field (SCON11[7:0]). The
application must ensure that the period of SICK is at least 61.035 ns.
—ns
t49 SID Setup Time (valid to low) 9 —ns
t50 SID Hold Time (low to invalid) 8 —ns
Table 52. Timing Characteristics for SIU Active Channel Mode Input
Abbreviated
Reference Parameter Min Max Unit
t46 SICK Bit Clock High Time (high to low) TAGCKH†–3
†TAGCKH and TAGCKL are dependent on the programming of the A GCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source.
TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin,
depending on the AGEXT field (SCON12[12]).
TAGCKH†+3 ns
t47 SICK Bit Clock Low Time (low to high) TAGCKL†–3T
AGCKL†+3 ns
t48 SIFS Delay (high to high) TCKAG†–5T
CKAG†+5 ns
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 49
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 1 for active mode output clock, OCKK(SCON10[7]) = 0 for no inver-
sion of SOCK, OFSA(SCON10[4]) = 1 for active mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOF S,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY [1:0](SCON2[9 :8]) = 00 for
no output frame sync delay.
Figure 31. SIU Active Frame Mode Output Timing Diagram
Table 53. Timing Requirements for SIU Active Frame Mode Output
Abbreviated
Reference Parameter Min Max Unit
t51 SOCK Bit Clock Period (high to high) 25†
†The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). The
period of SOCK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (SCON11[7:0]). The
application must ensure that the period of SOCK is at least 25 ns.
—ns
Table 54. Timing Characteristics for SIU Active Frame Mode Output
Abbreviated
Reference Parameter Min Max Unit
t52 SOCK Bit Clock High Time (high to low) TAGCKH†–3
†TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source.
TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin,
depending on the AGEXT field (SCON12[12]).
TAGCKH†+3 ns
t53 SOCK Bit Clock Low Time (low to high) TAGCKL†–3T
AGCKL†+3 ns
t54 SOFS Delay (high to high) TCKAG†–5T
CKAG†+5 ns
t55 SOD Data Delay (high to valid) 0 16 ns
t56 SOD Data Hold (high to invalid) –35ns
5-8030 (F)
t51
t52 t53
t55
SOCK
SOFS
SOD B0 B1
t56
B0
t54
B2
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
50
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
Note: It is assumed that the SIU is configured with OCKA(SCON10[6]) = 1 for active mode output clock, OCKK(SCON10[7]) = 0 for no inver-
sion of SOCK, OFSA(SCON10[4]) = 1 for active mode output frame sync, OFSK(SCON10[5]) = 0 for no inversion of SOF S,
OMSB(SCON0[10]) = 0 for LSB-first output, OFRAME(SCON2[7]) = 1 for frame mode output, and OFSDLY[ 1:0](SCON2[ 9 :8]) = 00 for
no output frame sync delay.
Figure 32. SIU Active Channel Mode Output Timing Diagram
Table 55. Timing Requirements for SIU Active Channel Mode Output
Abbreviated
Reference Parameter Min Max Unit
t51 SOCK Bit Clock Period (high to high) 61.035†
†The active clock source is programmed as either the internal clock CLK or the SCK pin, depending on the AGEXT field (SCON12[12]). The
period of SOCK is dependent on the period of the active clock source and the programming of the AGCKLIM[7:0] field (SCON11[7:0]). The
application must ensure that the period of SOCK is at least 61.035 ns.
—ns
Table 56. Timing Characteristics for SIU Active Channel Mode Output
Abbreviated
Reference Parameter Min Max Unit
t52 SOCK Bit Clock High Time (high to low) TAGCKH†–3
†TAGCKH and TAGCKL are dependent on the programming of the AGCKLIM[7:0] field (SCON11[7:0]) and the period of the active clock source.
TCKAG is the period of the active clock source. The active clock source is programmed as either the internal clock CLK or the SCK pin,
depending on the AGEXT field (SCON12[12]).
TAGCKH†+3 ns
t53 SOCK Bit Clock Low Time (low to high) TAGCKL†–3T
AGCKL†+3 ns
t54 SOFS Delay (high to high) TCKAG†–5T
CKAG†+5 ns
t55 SOD Data Delay (high to valid) 0 16 ns
t56 SOD Data Hold (high to invalid) –35ns
t57 SOD Deactivation Delay (high to 3-state) —15
5-8028 (F)
t51
t52 t53
t55
SOCK
SOFS
SOD B0 B1
t56
B0
t54
t57
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 51
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
†ICK is the internal active generated bit clock shown for reference purposes only.
Note: It is assumed that the SIU is configured with ICKA (SCON10[2]) = 1 for active mode input clock, I2XDLY (SCON1[11]) = 1 for e x tension
of active input bit clock, IFSA (SCON10[0]) = 1 and AG S YNC (SCON12[14]) = 1 to configure SIFS as an input and to synchronize the
active bit clocks and active frame syncs to SIFS, IFSK (SCON10[1]) = 1 for inversion of SIFS, IMSB (SCON0[2]) = 0 for LSB-first input,
IFSDLY[1:0] (SCON1[9:8]) = 00 for no input frame sync delay, AGEXT (SCON12[12]) = 1 for SCK pin as active clock source, SCKK
(SCON12[13]) = 1 for inversion of SCK, and AGCKLIM[7:0] (SCON11[7:0]) = 1 for an active cloc k divide r atio of 2.
Figure 33. ST-Bus 2x Input Timing Diagram
Table 57. ST-Bus 2x Input Timing Requirements
Abbreviated
Reference Parameter Min Max Unit
t80 SCK Clock Period 60 —ns
t81 SCK Clock Lo w Time 30 —ns
t82 SCK Clock High Time 30 —ns
t83 Input Frame Sync Hold 30 —ns
t84 Input Frame Sync Setup 20 —ns
t85 Input Data Setup 5 —ns
t86 Input Data Hold 20 —ns
t80
t81 t82
t84
SCK
SIFS
SID B0 B2
t83
t86
t83
B4
ICK
†
B
N – 1
t85
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
52
8 Timing Characteristics and Requirements (continued)
8.11 SIU (continued)
†OCK is the internal active generated bit clock shown for reference purposes only.
Note: It is assumed that the SIU is configured with OCKA (SCON10[6]) = 1 f or active mode output clock, IFSA(SCON10[0]) = 1 and AGSYNC
(SCON12[14]) = 1 to configure SIFS as an input and to synchronize the active bit clocks and active frame syncs to SIFS,
OFSA(SCON10[4]) = 1 for active output frame sync, IFSK(SCON10[1]) = 1 for inversion of SIFS, OMSB(SCON0[10]) = 0 fo r LSB -first
input, OFSDLY[1:0](SCON2[ 9:8]) = 00 for no output frame sync delay, AGEXT (SCON12[12]) = 1 for SCK pin as active clock source,
SCKK (SCON12[13]) = 1 for inversion of SCK, and AGCKLIM[7:0] (SCON11[7:0]) = 1 for an active clock divide ratio of 2.
Figure 34. ST-Bus 2x Output Timing Diagram
Table 58. ST-Bus 2x Output Timing Requirements
Abbreviated
Reference Parameter Min Max Unit
t80 SCK Clock Period 60 —ns
t81 SCK Clock Low Time 30 —ns
t82 SCK Clock High Time 30 —ns
t83 Input Frame Sync Hold 30 —ns
t84 Input Frame Sync Setup 20 —ns
Table 59. ST-Bus 2x Output Timing Characteristics
Abbreviated
Reference Parameter Min Max Unit
t89 Output Data Delay 1 25 ns
t58 Output Data Hold 0 4 ns
t83
t80
t81 t82
t84
SCK
SIFS
SOD B0 B2
t89
t58
t83
B4
OCK
†
B
N – 1
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 53
9 Package Diagrams
9.1 208-Pin PBGA
All dimensions are in millimeters.
5-7809 (F).b
0.80 ± 0.05
SEATING PLANE
SOLDER BALL
0.50 ± 0.10 0.20
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
15 SPACES @ 1.00 = 15.00
A1 BAL L
CORNER
15 SPACES
@ 1.00 = 15.00
17.00 ± 0.20
17.00 ± 0.20
15.00 +0.70
–0.05
15.00 +0.70
–0.05
A1 BALL
IDEN TIFIER ZONE
1.56
0.61 ± 0.06 1.91 ± 0.21
234 67891011121314151615
1.00
0.63 +0.07
–0.13
Data Addendum
May 2001
DSP16410C Digital Signal Processor
Agere Sy st ems Inc.
54
9 Package Diagrams (continued)
9.2 256-Pin EBGA
All dimensions are in millimeters.
5-5288 (F).a
A1 BALL
IDENTIFIER ZONE
27.00 ± 0.20
27.00
± 0.20
A
B
C
D
E
F
G
H
J
K
L
M
Y
N
P
R
T
U
V
W
123456 78910
111213141516 1718 20
19
19 SPACES @ 1.27 = 24.13
A1 BALL
CORNER
19 SPACES
@ 1.27 = 24.13
0.75 ± 0.15
0.80/1.00 1.70 MAX
SEATING PLANE
SOLDER BALL
0.60 ± 0.10
0.15
Data Addendum
May 2001 DSP16410C Digital Signal Processor
Agere Systems Inc. 55
Notes
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
May 2001
DA01-003WINF (Replaces DA00-015WTEC and Must Accompany DS01-070WTEC)
For additional information, contact your Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@micro.lucent.com
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Tel. (65) 778 8833, FAX (65) 777 7495
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Tel. (86) 21 504 71212, FAX (86) 21 50472266
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Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
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