Ultralow Distortion,
Differential ADC Driver
Data Sheet ADA4939-1/ADA4939-2
Rev. A Document Feedback
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FEATURES
Extremely low harmonic distortion
−102 dBc HD2 at 10 MHz
−83 dBc HD2 at 70 MHz
−77 dBc HD2 at 100 MHz
−101 dBc HD3 at 10 MHz
−97 dBc HD3 at 70 MHz
−91 dBc HD3 at 100 MHz
Low input voltage noise: 2.3 nV/√Hz
High speed
−3 dB bandwidth of 1.4 GHz, G = 2
Slew rate: 6800 V/μs, 25% to 75%
Fast overdrive recovery of <1 ns
±0.5 mV typical offset voltage
Externally adjustable gain
Stable for differential gains ≥2
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
GENERAL DESCRIPTION
The ADA4939-1/ADA4939-2 are low noise, ultralow distortion,
high speed differential amplifiers. They are an ideal choice for
driving high performance ADCs with resolutions up to 16 bits
from dc to 100 MHz. The output common-mode voltage is user
adjustable by means of an internal common-mode feedback loop,
allowing the ADA4939-1/ADA4939-2 output to match the input
of the ADC. The internal feedback loop also provides exceptional
output balance as well as suppression of even-order harmonic
distortion products.
With the ADA4939-1/ADA4939-2, differential gain configurations
are easily realized with a simple external feedback network of four
resistors that determine the closed-loop gain of the amplifier.
The ADA4939-1/ADA4939-2 are fabricated using Analog Devices,
Inc., proprietary silicon-germanium (SiGe), complementary bipolar
process, enabling them to achieve very low levels of distortion with
an input voltage noise of only 2.3 nV/√Hz. e low dc oset and
excellent dynamic performance of the ADA4939-1/ADA4939-2
make them well suited for a wide variety of data acquisition and
signal processing applications.
FUNCTIONAL BLOCK DIAGRAMS
–FB
+IN
–IN
+FB
–OUT
PD
+OUT
V
OCM
0
7752-001
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
A
DA4939-1
–V
S
–V
S
–V
S
–V
S
+
V
S
+
V
S
+
V
S
+
V
S
Figure 1. ADA4939-1
–IN1
+FB1
+V
S1
+V
S1
–FB2
+IN2
–IN2
+FB2
+V
S2
V
OCM2
+OUT2
+V
S2
–V
S1
–V
S1
–FB1
+IN1
PD1
–OUT1
–V
S2
–V
S2
V
OCM1
+OUT1
ADA4939-2
PD2
–OUT2
07429-002
2
1
3
4
5
6
18
17
16
15
14
13
8
9
10
11
7
12
20
19
21
22
23
24
Figure 2. ADA4939-2
The ADA4939-1 (single) is available in a 3 mm × 3 mm, 16-lead
LFCSP, and the ADA4939-2 (dual) is available in a 4 mm × 4 mm,
24-lead LFCSP. The pinouts are optimized to facilitate printed
circuit board (PCB) layout and minimize distortion. The
ADA4939-1/ADA4939-2 are specified to operate over the
−40°C to +105°C temperature range; both operate on supplies
between 3.3 V and 5 V.
–
60
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
1 10 100
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
HD2
HD3
V
OUT, dm
= 2V p-p
07429-021
Figure 3. Harmonic Distortion vs. Frequency
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Operation ............................................................................... 3
3.3 V Operation ............................................................................ 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 15
Operational Description ................................................................ 16
Definition of Terms .................................................................... 16
Theory of Operation ...................................................................... 17
Analyzing an Application Circuit ............................................ 17
Setting the Closed-Loop Gain .................................................. 17
Stable for Gains ≥2 ..................................................................... 17
Estimating the Output Noise Voltage ...................................... 17
Impact of Mismatches in the Feedback Networks ................. 18
Calculating the Input Impedance for an Application Circuit
....................................................................................................... 19
Input Common-Mode Voltage Range ..................................... 21
Input and Output Capacitive AC Coupling ............................ 21
Minimum RG Value of 50 Ω ...................................................... 21
Setting the Output Common-Mode Voltage .......................... 21
Layout, Grounding, and Bypassing .............................................. 22
High Performance ADC Driving ................................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
5/2016—Rev. 0 to Rev. A
Changed ADA4939 to ADA4939-1/ADA4939-2, CP-16-2 to
CP-16-21, and CP-24-1 to CP-24-10 ........................... Throughout
Changes to Figure 5, Figure 6, Table 9, and Table 10 ................... 8
Changes to Figure 54 ...................................................................... 23
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
5/2008—Revision 0: Initial Version
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 3 of 24
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −V S = 0 V, V OCM = +VS/2, RF = 402 Ω, RG = 200 Ω, RT = 60.4 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 42 for signal definitions.
±DIN to VOUT, dm Performance
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 1400 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 0.1 V p-p, ADA4939-1 300 MHz
VOUT, dm = 0.1 V p-p, ADA4939-2 90 MHz
Large Signal Bandwidth VOUT, dm = 2 V p-p 1400 MHz
Slew Rate VOUT, dm = 2 V p-p, 25% to 75% 6800 V/µs
Overdrive Recovery Time VIN = 0 V to 1.5 V step, G = 3.16 <1 ns
NOISE/HARMONIC PERFORMANCE See Figure 41 for distortion test circuit
Second Harmonic
V
OUT, dm
= 2 V p-p, 10 MHz
−102
dBc
VOUT, dm = 2 V p-p, 70 MHz −83 dBc
VOUT, dm = 2 V p-p, 100 MHz −77 dBc
Third Harmonic VOUT, dm = 2 V p-p, 10 MHz −101 dBc
VOUT, dm = 2 V p-p, 70 MHz −97 dBc
VOUT, dm = 2 V p-p, 100 MHz −91 dBc
IMD f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p −95 dBc
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p −89 dBc
Voltage Noise (RTI) f = 100 kHz 2.3 nV/√Hz
Input Current Noise f = 100 kHz 6 pA/√Hz
Crosstalk f = 100 MHz, ADA4939-2 −80 dB
INPUT CHARACTERISTICS
Offset Voltage VOS, dm = VOUT, dm/2, VDIN+ = VDIN− = 2.5 V −3.4 ±0.5 +2.8 mV
TMIN to TMAX variation ±2.0 µV/°C
Input Bias Current
−26
−10
+2.2
µA
TMIN to TMAX variation ±0.5 µA/°C
Input Offset Current −11.2 +0.5 +11.2 µA
Input Resistance Differential 180 kΩ
Common mode 450 kΩ
Input Capacitance 1 pF
Input Common-Mode Voltage 1.1 3.9 V
CMRR ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −83 −77 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT; single-ended output, RF = RG = 10 kΩ 0.9 4.1 V
Linear Output Current 100 mA
Output Balance Error ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, 10 MHz,
see Figure 40 for test circuit
−64 dB
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 4 of 24
VOCM to VOUT, cm Performance
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth 670 MHz
Slew Rate VIN = 1.5 V to 3.5 V, 25% to 75% 2500 V/µs
Input Voltage Noise (RTI) f = 100 kHz 7.5 nV/√Hz
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range 1.3 3.5 V
Input Resistance 8.3 9.7 11.5 kΩ
Input Offset Voltage VOS, cm = VOUT, cm, VDIN+ = VDIN− = +VS/2 −3.7 ±0.5 +3.7 mV
VOCM CMRR ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V −90 −73 dB
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.97 0.98 0.99 V/V
General Performance
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 3.0 5.25 V
Quiescent Current per Amplifier 35.1 36.5 37.7 mA
TMIN to TMAX variation 16 µA/°C
Powered down 0.26 0.32 0.38 mA
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS, ΔVS = 1 V −90 −80 dB
POWER-DOWN (PD)
PD Input Voltage Powered down ≤1 V
Enabled ≥2 V
Turn-Off Time 500 ns
Turn-On Time 100 ns
PD Pin Bias Current per Amplifier
Enabled PD = 5 V 30 µA
Disabled PD = 0 V −200 µA
OPERATING TEMPERATURE RANGE
−40
+105
°C
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 5 of 24
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, −VS = 0 V, VOCM = +VS/2, RF = 402 Ω, RG = 200 Ω, RT = 60.4 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 42 for signal definitions.
±DIN to VOUT, dm Performance
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 1400 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 0.1 V p-p, ADA4939-1 300 MHz
VOUT, dm = 0.1 V p-p, ADA4939-2 90 MHz
Large Signal Bandwidth VOUT, dm = 2 V p-p 1400 MHz
Slew Rate VOUT, dm = 2 V p-p, 25% to 75% 5000 V/µs
Overdrive Recovery Time VIN = 0 V to 1.0 V step, G = 3.16 <1 ns
NOISE/HARMONIC PERFORMANCE See Figure 41 for distortion test circuit
Second Harmonic VOUT, dm = 2 V p-p, 10 MHz −100 dBc
VOUT, dm = 2 V p-p, 70 MHz −90 dBc
VOUT, dm = 2 V p-p, 100 MHz −83 dBc
Third Harmonic VOUT, dm = 2 V p-p, 10 MHz −94 dBc
VOUT, dm = 2 V p-p, 70 MHz −82 dBc
VOUT, dm = 2 V p-p, 100 MHz −75 dBc
IMD f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p −87 dBc
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p −70 dBc
Voltage Noise (RTI) f = 100 kHz 2.3 nV/√Hz
Input Current Noise f = 100 kHz 6 pA/√Hz
Crosstalk f = 100 MHz, ADA4939-2 −80 dB
INPUT CHARACTERISTICS
Offset Voltage VOS, dm = VOUT, dm/2, VDIN+ = VDIN− = +VS/2 −3.5 ±0.5 +3.5 mV
TMIN to TMAX variation ±2.0 µV/°C
Input Bias Current −26 −10 +2.2 µA
TMIN to TMAX variation ±0.5 µA/°C
Input Offset Current −11.2 ±0.4 +11.2
Input Resistance Differential 180 kΩ
Common mode 450 kΩ
Input Capacitance 1 pF
Input Common-Mode Voltage 0.9 2.4 V
CMRR ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −85 −75 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT, single-ended output, RF = RG = 10 kΩ 0.8 2.5 V
Linear Output Current 75 mA
Output Balance Error
∆V
OUT, cm
/∆V
OUT, dm
, ∆V
OUT, dm
= 1 V, f = 10 MHz,
see Figure 40 for test circuit
−61
dB
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 6 of 24
VOCM to VOUT, cm Performance
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth 560 MHz
Slew Rate VIN = 0.9 V to 2.4 V, 25% to 75% 1250 V/µs
Input Voltage Noise (RTI) f = 100 kHz 7.5 nV/√Hz
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range 1.3 1.9 V
Input Resistance 8.3 9.7 11.2 kΩ
Input Offset Voltage VOS, cm = VOUT, cm, VDIN+ = VDIN− = 1.67 V −3.7 ±0.5 +3.7 mV
VOCM CMRR ∆VOUT, dm/∆VOCM, ∆VOCM = ±1 V −75 −73 dB
Gain ∆VOUT, cm/∆VOCM, ∆VOCM = ±1 V 0.97 0.98 0.99 V/V
General Performance
Table 6.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 3.0 5.25 V
Quiescent Current per Amplifier 32.8 34.5 36.0 mA
T
MIN
to T
MAX
variation
16
µA/°C
Powered down 0.16 0.20 0.26 mA
Power Supply Rejection Ratio ∆VOUT, dm/∆VS, ∆VS = 1 V −84 −72 dB
POWER-DOWN (PD)
PD Input Voltage Powered down ≤1 V
Enabled ≥2 V
Turn-Off Time 500 ns
Turn-On Time
100
ns
PD Pin Bias Current per Amplifier
Enabled PD = 3.3 V 26 µA
Disabled PD = 0 V −137 µA
OPERATING TEMPERATURE RANGE −40 +105 °C
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
Supply Voltage 5.5 V
Power Dissipation See Figure 4
Input Current, +IN, −IN, PD ±5 mA
Storage Temperature Range −65°C to +125°C
Operating Temperature Range
ADA4939-1 −40°C to +105°C
ADA4939-2 −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.
Table 8. Thermal Resistance
Package Type θJA Unit
ADA4939-1, 16-Lead LFCSP (Exposed Pad) 98 °C/W
ADA4939-2, 24-Lead LFCSP (Exposed Pad) 67 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4939-1/
ADA4939-2 package is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4939-1/
ADA4939-2. Exceeding a junction temperature of 150°C for an
extended period can result in changes in the silicon devices,
potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. Calculate the power due to the load drive
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and power
planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead
LFCSP (98°C/W) and the dual 24-lead LFCSP (67°C/W) on a
JEDEC standard 4-layer board with the exposed pad soldered to
a PCB pad that is connected to a solid plane.
3.0
2.5
2.0
1.5
1.0
0.5
0
–40 100806040200–20
MAXIMUM POWER DISSIPATION (W)
AMBIENT TEMPERATURE (°C)
07429-004
ADA4939-1
ADA4939-2
Figure 4. Maximum Power Dissipation vs. Ambient Temperature for
a 4-Layer Board
ESD CAUTION
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
–FB
+IN
–IN
+FB
–OUT
PD
+OUT
VOCM
+V
S
+V
S
+V
S
+V
S
–V
S
–V
S
–V
S
–V
S
PIN 1
INDICATOR
07429-005
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
ADA4939-1
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. THE EXPOSED PAD
MUST BE CONNECTED TO GROUND.
Figure 5. ADA4939-1 Pin Configuration
–IN1
+
FB1
+V
S1
+V
S1
–
FB2
+IN2
–IN2
+FB2
+V
S2
V
OCM2
+OUT2
+V
S2
+IN1
–V
S1
–V
S1
–FB1
PD1
–OUT1
–V
S2
–V
S2
V
OCM1
+OUT1
PD2
–OUT2
07429-006
2
1
3
4
5
6
18
17
16
15
14
13
8
9
10
11
7
12
20
19
21
22
23
24
TOP VIEW
(Not to Scale)
ADA4939-2
NOTES
1. EXPOSED PAD. THE EXPOSED PAD
MUST BE CONNECTED TO GROUND.
Figure 6. ADA4939-2 Pin Configuration
Table 9. ADA4939-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 −FB Negative Output for Feedback Component Connection
2 +IN Positive Input Summing Node
3 −IN Negative Input Summing Node
4 +FB Positive Output for Feedback Component Connection
5 to 8 +VS Positive Supply Voltage
9 VOCM Output Common-Mode Voltage
10 +OUT Positive Output for Load Connection
11 −OUT Negative Output for Load Connection
12 PD Power-Down Pin
13 to 16 −VS Negative Supply Voltage
EPAD Exposed Pad. The exposed pad must be connected to ground.
Table 10. ADA4939-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN1 Negative Input Summing Node 1
2 +FB1 Positive Output Feedback 1
3, 4 +VS1 Positive Supply Voltage 1
5 −FB2 Negative Output Feedback 2
6 +IN2 Positive Input Summing Node 2
7 −IN2 Negative Input Summing Node 2
8 +FB2 Positive Output Feedback 2
9, 10 +VS2 Positive Supply Voltage 2
11 VOCM2 Output Common-Mode Voltage 2
12 +OUT2 Positive Output 2
13 −OUT2 Negative Output 2
14 PD2 Power-Down Pin 2
15, 16 −VS2 Negative Supply Voltage 2
17 VOCM1 Output Common-Mode Voltage 1
18 +OUT1 Positive Output 1
19 −OUT1 Negative Output 1
20 PD1 Power-Down Pin 1
21, 22 −VS1 Negative Supply Voltage 1
23 −FB1 Negative Output Feedback 1
24 +IN1 Positive Input Summing Node 1
EPAD Exposed Pad. The exposed pad must be connected to ground.
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS /2, RG = 200 , RF = 402 , RT = 60.4 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise noted. Refer
to Figure 39 for test setup. Refer to Figure 42 for signal definitions.
2
–14
–12
–10
–8
–6
–4
–2
0
1 10 100 1k
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
G = +2.00
G = +3.16
G = +5.00
R
G
= 200Ω, R
T
= 60.4Ω
R
G
= 127Ω, R
T
= 66.3Ω
R
G
= 80.6Ω, R
T
= 76.8Ω
V
OUT, dm
= 100mV p-p
07429-007
Figure 7. Small Signal Frequency Response for Various Gains
3
–12
–10
–8
–6
–4
–2
0
2
–11
–9
–7
–5
–3
–1
1
1 10 100 1k
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
V
S
= 3.3V
V
S
= 5.0V
07429-008
V
OUT, dm
= 100mV p-p
Figure 8. Small Signal Frequency Response for Various Supplies
3
–12
–10
–8
–6
–4
–2
0
2
–11
–9
–7
–5
–3
–1
1
1 10 100 1k
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
–40°C
+25°C
+105°C
07429-009
V
OUT, dm
= 100mV p-p
Figure 9. Small Signal Frequency Response for Various Temperatures
2
–14
–12
–10
–8
–6
–4
–2
0
1 10 100 1k
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
G = +2.00
G = +3.16
G = +5.00
07429-010
R
G
= 200Ω, R
T
= 60.4Ω
R
G
= 127Ω, R
T
= 66.3Ω
R
G
= 80.6Ω, R
T
= 76.8Ω
V
OUT, dm
= 2V p-p
Figure 10. Large Signal Frequency Response for Various Gains
2
–12
–10
–8
–6
–4
–2
0
1 10 100 1k
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
V
S
= 3.3V
V
S
= 5.0V
07429-011
V
OUT, dm
= 2V p-p
Figure 11. Large Signal Frequency Response for Various Supplies
3
–12
–10
–8
–6
–4
–2
0
2
–11
–9
–7
–5
–3
–1
1
1 10 100 1k
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
–40°C
+25°C
+105°C
07429-012
V
OUT, dm
= 2V p-p
Figure 12. Large Signal Frequency Response for Various Temperatures
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 10 of 24
3
–12
–10
–8
–6
–4
–2
0
2
–11
–9
–7
–5
–3
–1
1
1 10 100 1k
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
R
L
= 1kΩ
R
L
= 200Ω
07429-013
V
OUT, dm
= 100mV p-p
Figure 13. Small Signal Frequency Response for Various Loads
6
–9
–6
–3
3
0
1 10 100 1k
VOCM GAIN (dB)
FREQUENCY (MHz)
VOCM = 1.0V
VOCM = 3.9V
VOCM = 2.5V
07429-019
VOUT, dm = 100mV p-p
Figure 14. VOCM Small Signal Frequency Response at Various DC Levels
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
1 10 100 1k
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
RL = 1kΩ
RL = 200Ω
RL = 1kΩ OUT1
RL = 1kΩ OUT2
RL = 200Ω OUT1
RL = 200Ω OUT2
07429-020
VOUT, dm = 100mV p-p
Figure 15. 0.1 dB Flatness Small Signal Response for Various Loads
3
–12
–10
–8
–6
–4
–2
0
2
–11
–9
–7
–5
–3
–1
1
1 10 100 1k
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
RL = 1kΩ
RL = 200Ω
07429-016
VOUT, dm = 2V p-p
Figure 16. Large Signal Frequency Response for Various Loads
–55
–115
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
1 10 100
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
V
OUT, dm
= 2V p-p
HD2, G = 2
HD3, G = 2
HD2, G = 3.16
HD3, G = 3.16
HD2, G = 5
HD3, G = 5
07429-022
Figure 17. Harmonic Distortion vs. Frequency at Various Gains
–
60
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
1 10 100
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
HD2, R
L, dm
= 1kΩ
HD3, R
L, dm
= 1kΩ
HD2, R
L, dm
= 200Ω
HD3, R
L, dm
= 200Ω
V
OUT, dm
= 2V p-p
V
S
= ±2.5V
07429-023
Figure 18. Harmonic Distortion vs. Frequency at Various Loads
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 11 of 24
–
60
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
1 10 100
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
HD2, V
S
(SPLIT SUPPLY) = ±2.5V
HD3, V
S
(SPLIT SUPPLY) = ±2.5V
HD2, V
S
(SPLIT SUPPLY) = ±1.65V
HD3, V
S
(SPLIT SUPPLY) = ±1.65V
V
OUT, dm
= 2V p-p
07429-062
Figure 19. Harmonic Distortion vs. Frequency at Various Supplies
–
40
–120
–110
–100
–90
–80
–70
–60
–50
1.0 4.03.83.63.43.23.02.82.62.42.22.01.81.61.41.2
DISTORTION (dBc)
V
OCM
(V)
HD2, f = 10MHz
HD3, f = 10MHz
HD2, f = 70MHz
HD3, f = 70MHz
V
OUT, dm
= 2V p-p
07429-025
Figure 20. Harmonic Distortion vs. VOCM at Various Frequencies
–
40
–130
–120
–110
–100
–90
–80
–70
–60
–50
1.2 1.4 1.6 1.8 2.0
DISTORTION (dBc)
V
OCM
(V)
HD2, f = 10MHz
HD3, f = 10MHz
HD2, f = 70MHz
HD3, f = 70MHz
V
OUT, dm
= 2V p-p
07429-026
Figure 21. Harmonic Distortion vs. VOCM at Various Frequencies
–
40
–130
–120
–110
–100
–90
–80
–70
–60
–50
07654321
DISTORTION (dBc)
V
OUT, dm
(V p-p)
HD2, V
S
= 5.0
HD3, V
S
= 5.0
HD2, V
S
= 3.3
HD3, V
S
= 3.3
07429-024
Figure 22. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz
10
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
69.5 70.570.470.370.270.170.069.969.869.769.6
NORMALIZED SPECTRUM (dBc)
FREQUENCY (MHz)
V
OUT, dm
= 2V p-p
V
S
= ±2.5V
07429-028
Figure 23. 70 MHz Intermodulation Distortion
–
30
–35
–40
–45
–50
–55
–60
–65
–70
110 1k100
CMRR (dB)
FREQUENCY (MHz)
R
L, dm
= 200Ω
07429-029
Figure 24. CMRR vs. Frequency
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 12 of 24
–
60
–120
–110
–100
–90
–80
–70
1 10 100
HARMONIC DISTORTION (dBc)
FREQUENCY (MHz)
V
OUT, dm
=HD2, = 1V p-p
V
OUT, dm
=HD3, = 1V p-p
V
OUT, dm
=HD2, = 2V p-p
V
OUT, dm
=HD3, = 2V p-p
07429-027
V
S
= ±1.65V
Figure 25. Harmonic Distortion vs. Frequency at Various Output Voltages
–
30
–40
–50
–60
–70
–80
–90
–100
110 1k100
PSRR (dB)
FREQUENCY (MHz)
R
L, dm
= 200Ω
07429-031
Figure 26. PSRR vs. Frequency, RL = 200 Ω
0
–5
–50
–45
–40
–35
–30
–25
–20
–15
–10
1 10 100 1k
S-PARAMETERS (dB)
FREQUENCY (MHz)
R
L, dm
= 200Ω
S11
S22
07429-032
Figure 27. Return Loss (S11, S22) vs. Frequency
–
30
–35
–40
–45
–50
–55
–60
–65
–70
110 1k100
OUTPUT BALANCE (dB)
FREQUENCY (MHz)
R
L, dm
= 200Ω
07429-030
Figure 28. Output Balance vs. Frequency
70
–10
100
–350
–300
–250
–200
–150
–100
–50
0
50
0
10
20
30
40
50
60
0.01 10k1k1001010.1
GAIN (dB)
PHASE (Degrees)
FREQUENCY (MHz)
GAIN
PHASE
07429-034
Figure 29. Open-Loop Gain and Phase vs. Frequency
8
–8
–6
–4
–2
0
2
4
6
0605040302010
VOLTAGE (V)
TIME (ns)
V
IN
× 3.16V
V
OUT
07429-035
Figure 30. Overdrive Recovery, G = 3.16
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 13 of 24
–
60
–105
–100
–95
–90
–85
–80
–75
–70
–65
1 10 100
SPURIOUS-FREE DYNAMIC RANGE (dBc)
FREQUENCY (MHz)
V
OUT, dm
= 2V p-p
V
S
= ±2.5V
R
L
= 1kΩ
R
L
= 200Ω
07429-033
Figure 31. Spurious-Free Dynamic Range vs. Frequency at Various Loads
0.12
0.10
0.08
0.06
0.04
0.02
0
–0.02
010987654321
OUTPUT VOLTAGE (V)
TIME (ns)
07429-038
Figure 32. Small Signal Pulse Response
2.60
2.40
2.45
2.50
2.55
02018161412108642
OUTPUT COMMON-MODE VOLTAGE (V)
TIME (ns)
07429-039
Figure 33. VOCM Small Signal Pulse Response
–
40
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
11k10010
CROSSTALK (dB)
FREQUENCY (MHz)
R
L, dm
= 200Ω
INPUT AMP 1 TO OUTPUT AMP 2
INPUT AMP 2 TO OUTPUT AMP 1
07429-044
Figure 34. Crosstalk vs. Frequency for ADA4939-2
4
–4
–3
–2
–1
0
1
2
3
010987654321
OUTPUT VOLTAGE (V)
TIME (ns)
07429-041
Figure 35. Large Signal Pulse Response
4.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
02018161412108642
OUTPUT COMMON-MODE VOLTAGE (V)
TIME (ns)
07429-042
Figure 36. VOCM Large Signal Pulse Response
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 14 of 24
3.5
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
0 1000900800700600500400300200100
VOLTAGE (V)
TIME (ns)
VOUT, dm
RL, dm = 200Ω
PD
07429-043
Figure 37. PD Response Time
1k
1
10
100
10 10M1M100k10k1k100
INPUT VOLTAGE NOISE (nV/ Hz)
FREQUENCY (Hz)
07429-045
Figure 38. Voltage Noise Spectral Density, RTI
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 15 of 24
TEST CIRCUITS
1kΩ
5V
402Ω
200Ω50Ω
200Ω
0.1µF
0.1µF
402Ω
V
OCM
60.4Ω
V
IN
07429-046
ADA4939-1/
ADA4939-2
Figure 39. Equivalent Basic Test Circuit, G = 2
+2.5V
0.1µF
–2.5V
402Ω
200Ω50Ω
200Ω
49.9Ω
49.9Ω
NETWORK
ANALYZER
INPUT
AC-COUPLED
NETWORK
ANALYZER
OUTPUT
AC-COUPLED
50Ω
402Ω
49.9Ω
49.9Ω
V
OCM
60.4Ω
60.4Ω
V
IN
07429-047
ADA4939-1/
ADA4939-2
Figure 40. Test Circuit for Output Balance, CMRR
5V
402Ω
200Ω50Ω
200Ω
442Ω
442Ω
0.1µF
0.1µF
402Ω
V
OCM
60.4Ω261Ω
200Ω
2:1 50Ω
CT
V
IN
LOW-PASS
FILTER
0.1µF
0.1µF
DUAL
FILTER
07429-048
ADA4939-1/
ADA4939-2
Figure 41. Test Circuit for Distortion Measurements
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 16 of 24
OPERATIONAL DESCRIPTION
DEFINITION OF TERMS
+IN
–IN +OUT
–OUT
+D
IN
–
FB
+FB
–D
IN
V
OCM
R
G
R
F
R
G
V
OUT, dm
R
L, dm
R
F
07429-049
ADA4939-1/
ADA4939-2
Figure 42. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Common-Mode Voltage
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
VOUT, cm = (V+OUT + V−OUT)/2
Balance
Output balance is a measure of how close the differential signals
are to being equal in amplitude and opposite in phase. Output
balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the divider midpoint
with the magnitude of the differential signal (see Figure 39). By
this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
dmOUT
cmOUT
V
V
ErrorBalanceOutput
,
,
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 17 of 24
THEORY OF OPERATION
The ADA4939-1/ADA4939-2 differ from conventional op amps
in that they have two outputs whose voltages move in opposite
directions and an additional input, VOCM. Like op amps, they
rely on high open-loop gain and negative feedback to force
these outputs to the desired voltages. The ADA4939-1/
ADA4939-2 behave much like standard voltage feedback op
amps and facilitate single-ended-to-differential conversions,
common-mode level shifting, and amplifications of differential
signals. Like op amps, the ADA4939-1/ADA4939-2 have high
input impedance and low output impedance. Because they use
voltage feedback, the ADA4939-1/ADA4939-2 manifest a
nominally constant gain-bandwidth product.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output voltage.
The common-mode feedback controls only the common-mode
output voltage. This architecture makes it easy to set the output
common-mode level to any arbitrary value within the specified
limits. The output common-mode voltage is forced by the internal
common-mode feedback loop to be equal to the voltage applied
to the VOCM input.
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results in
differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180° apart in phase.
ANALYZING AN APPLICATION CIRCUIT
The ADA4939-1/ADA4939-2 use high open-loop gain and
negative feedback to force their differential and common-mode
output voltages in such a way as to minimize the differential
and common-mode error voltages. The differential error
voltage is defined as the voltage between the differential inputs
labeled +IN and −IN (see Figure 42). For most purposes, this
voltage is zero. Similarly, the difference between the actual
output common-mode voltage and the voltage applied to VOCM
is also zero. Starting from these two assumptions, any
application circuit can be analyzed.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 42 can be
determined by
G
F
dmIN
dmOUT
R
R
V
V
,
,
This presumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
STABLE FOR GAINS ≥2
The ADA4939-1/ADA4939-2 frequency response exhibits
excessive peaking for differential gains <2; therefore, operate the
devioce with differential gains ≥2.
ESTIMATING THE OUTPUT NOISE VOLTAGE
To estimate the differential output noise of the ADA4939-1/
ADA4939-2 use the noise model shown in Figure 43. The input-
referred noise voltage density, vnIN, is modeled as a differential
input, and the noise currents, inIN− and inIN+, appear between
each input and ground. The output voltage due to vnIN is obtained
by multiplying vnIN by the noise gain, GN (defined in the GN
equation that follows). The noise currents are uncorrelated with
the same mean-square value, and each produces an output voltage
that is equal to the noise current multiplied by the associated
feedback resistance. The noise voltage density at the VOCM/VOCMx
pin is vnCM. When the feedback networks have the same feedback
factor, as in most cases, the output noise due to vnCM is common-
mode. Each of the four resistors contributes (4kTRxx)1/2. The noise
from the feedback resistors appears directly at the output, and
the noise from the gain resistors appears at the output multiplied
by RFx/RGx. Table 11 summarizes the input noise sources, the
multiplication factors, and the output-referred noise density
terms.
+
R
F2
V
nOD
V
nCM
V
OCM
V
nIN
R
F1
R
G2
R
G1
V
nRF1
V
nRF2
V
nRG1
V
nRG2
i
nIN+
i
nIN–
07429-050
ADA4939-1/
ADA4939-2
Figure 43. Noise Model
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 18 of 24
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise Contribution Input Noise Term
Input Noise
Voltage Density
Output
Multiplication Factor
Differential Output Noise
Voltage Density Term
Differential Input vnIN v
nIN G
N v
nO1 = GN(vnIN)
Inverting Input inIN inIN × (RF2) 1 vnO2 = (inIN)(RF2)
Noninverting Input inIN inIN × (RF1) 1 vnO3 = (inIN)(RF1)
VOCM Input vnCM v
nCM 0 vnO4 = 0
Gain Resistor RG1 v
nRG1 (4kTRG1)1/2 R
F1/RG1 v
nO5 = (RF1/RG1)(4kTRG1)1/2
Gain Resistor RG2 v
nRG2 (4kTRG2)1/2 R
F2/RG2 v
nO6 = (RF2/RG2)(4kTRG2)1/2
Feedback Resistor RF1 v
nRF1 (4kTRF1)1/2 1 vnO7 = (4kTRF1)1/2
Feedback Resistor RF2 v
nRF2 (4kTRF2)1/2 1 vnO8 = (4kTRF2)1/2
Table 12. Differential Input, DC-Coupled
Nominal Gain (dB) RF (Ω) RG (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz)
6 402 200 400 9.7
10 402 127 254 12.4
14 402 80.6 161 16.6
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω
Nominal Gain (dB) RF (Ω) RG1 (Ω) RT (Ω) RIN, cm (Ω) RG2 (Ω)1 Differential Output Noise Density (nV/√Hz)
6 402 200 60.4 301 228 9.1
10 402 127 66.5 205 155 11.1
14 402 80.6 76.8 138 111 13.5
1 RG2 = RG1 + (RS||RT).
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by the appropriate output factor,
where:
21
Nββ
G
2 is the circuit noise gain.
G1
F1
G1
1RR
R
β
and
G2
F2
G2
2RR
R
β
are the feedback factors.
When the feedback factors are matched, RF1/RG1 = RF2/RG2, β1 =
β2 = β, and the noise gain becomes
G
F
NR
R
β
G 1
1
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
8
1i
2
nOinOD vv
Table 12 and Table 13 list several common gain settings,
associated resistor values, input impedance, and output noise
density for both balanced and unbalanced input configurations.
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
The gain from the VOCM/VOCMx pin to VO, dm is equal to
2(β1 − β2)/(β1 + β2)
When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the VOCM input (including
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from VOCM input
to VO, dm is either +2 or −2, depending on which loop is closed. The
feedback loops are nominally matched to within 1% in most
applications, and the output noise and offsets due to the VOCM
input are negligible. If the loops are intentionally mismatched by a
large amount, it is necessary to include the gain term from VOCM
to VO, dm and account for the extra noise. For example, if β1 = 0.5
and β2 = 0.25, the gain from VOCM to VO, dm is 0.67. If the
VOCM/VOCMx pin is set to 2.5 V, a differential offset voltage is present
at the output of (2.5 V)(0.67) = 1.67 V. The differential output noise
contribution is (7.5 nV/√Hz)(0.67) = 5 nV/√Hz. Both of these
results are undesirable in most applications; therefore, it is best
to use nominally matched feedback factors.
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 19 of 24
Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
As a practical summarization of the above issues, resistors of 1%
tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 25 mV
due to a 2.5 V VOCM input, negligible VOCM noise contribution,
and no significant degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 44, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
+V
S
+IN
–IN
R
F
R
F
+D
IN
–D
IN
V
OCM
R
G
R
G
V
OUT, dm
07429-051
ADA4939-1/
ADA4939-2
Figure 44. ADA4939-1/ADA4939-2 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 45),
the input impedance is
F
G
F
G
SEIN
RR
R
R
R
2
1
,
R
L
V
OUT, dm
+V
S
–V
S
R
G
R
G
R
F
R
F
V
OCM
R
IN
, SE
0
7429-052
ADA4939-1/
ADA4939-2
Figure 45. ADA4939-1/ADA4939-2 with Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG. The common-mode
voltage at the amplifier input terminals can be easily determined by
noting that the voltage at the inverting input is equal to the
noninverting output voltage divided down by the voltage divider
formed by RF and RG in the lower loop. This voltage is present at
both input terminals due to negative voltage feedback and is in
phase with the input signal, thus reducing the effective voltage
across RG in the upper loop and partially bootstrapping RG.
Terminating a Single-Ended Input
This section deals with how to properly terminate a single-ended
input to the ADA4939-1/ADA4939-2 with a gain of 2, RF = 400 Ω,
and RG = 200 Ω. An example using an input source with a
terminated output voltage of 1 V p-p and source resistance of 50 Ω
illustrates the four simple steps that must be followed. Note that,
because the terminated output voltage of the source is 1 V p-p,
the open circuit output voltage of the source is 2 V p-p. The
source shown in Figure 46 indicates this open-circuit voltage.
1. The input impedance must be calculated using the formula
300
)400200(2
400
1
200
)(2
1
F
G
F
G
IN
RR
R
R
R
R
S
50Ω
V
S
2V p-p
R
IN
300Ω
R
L
V
OUT, dm
+V
S
–V
S
R
G
200Ω
R
G
200Ω
R
F
400Ω
R
F
400Ω
V
OCM
07429-053
ADA4939-1/
ADA4939-2
Figure 46. Calculating Single-Ended Input Impedance RIN
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 20 of 24
2. To match the 50 Ω source resistance, the termination
resistor, RT, is calculated using RT||300 Ω = 50 Ω. The
closest standard 1% value for RT is 60.4 Ω.
R
L
V
OUT, dm
+V
S
–V
S
R
S
50Ω
R
G
200Ω
R
G
200Ω
R
F
400Ω
R
F
400Ω
V
OCM
V
S
2V p-p
R
IN
50Ω
R
T
60.4Ω
07429-054
ADA4939-1/
ADA4939-2
Figure 47. Adding Termination Resistor RT
3. Figure 47 shows that the effective RG in the upper feedback
loop is now greater than the RG in the lower loop due to the
addition of the termination resistors. To compensate for
the imbalance of the gain resistors, a correction resistor
(RTS) is added in series with RG in the lower loop. RTS is
equal to the Thevenin equivalent of the source resistance
RS and the termination resistance RT and is equal to RS||RT.
R
S
50Ω
V
S
2
V p-
p
R
T
60.4Ω
R
TH
27.4Ω
V
TH
1.09V p-p
0
7429-055
Figure 48. Calculating the Thevenin Equivalent
RTS = RTH = RS||RT = 27.4 Ω. Note that VTH is greater than
1 V p-p, which was obtained with RT = 50 Ω. The modified
circuit with the Thevenin equivalent of the terminated source
and RTS in the lower feedback loop is shown in Figure 49.
R
L
V
OUT, dm
+V
S
–V
S
R
TH
27.4Ω
R
G
200Ω
R
G
200Ω
R
F
400Ω
R
F
400Ω
V
OCM
V
TH
1.09V p-p
R
TS
27.4Ω
07429-056
ADA4939-1/
ADA4939-2
Figure 49. Thevenin Equivalent and Matched Gain Resistors
Figure 49 presents a tractable circuit with matched
feedback loops that can be easily evaluated.
It is useful to point out two effects that occur with a
terminated input. The first is that the value of RG is increased
in both loops, lowering the overall closed-loop gain. The
second is that VTH is a little larger than 1 V p-p, as it would
be if RT = 50 Ω. These two effects have opposite impacts on
the output voltage, and for large resistor values in the feedback
loops (~1 kΩ), the effects essentially cancel each other out.
For small RF and RG, however, the diminished closed-loop
gain is not canceled completely by the increased VTH. This
can be seen by evaluating Figure 49.
The desired differential output in this example is 2 V p-p
because the terminated input signal was 1 V p-p and the
closed-loop gain = 2. The actual differential output voltage,
however, is equal to (1.09 V p-p)(400/227.4) = 1.92 V p-p.
To obtain the desired output voltage of 2 V p-p, a final gain
adjustment can be made by increasing RF without modifying
any of the input circuitry (see Step 4).
4. The feedback resistor value is modified as a final gain
adjustment to obtain the desired output voltage.
To make the output voltage VOUT = 2 V p-p, calculate RF by
417
09.1
4.2272
,
PP
PP
TH
TS
G
dmOUT
F
V
V
V
RRVDesired
R
The closest standard 1 % values to 417 Ω are 412 Ω and
422 Ω. Choosing 422 Ω gives a differential output voltage
of 2.02 V p-p.
The final circuit is shown in Figure 50.
R
L
V
OUT, dm
2.02V p-p
+V
S
–V
S
R
S
50Ω
R
G
200Ω
R
G
200Ω
R
F
422Ω
R
F
422Ω
V
OCM
V
S
2V p-p
1V p-p
R
T
60.4Ω
R
TS
27.4Ω
07429-057
ADA4939-1/
ADA4939-2
Figure 50. Terminated Single-Ended-to-Differential System with G = 2
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 21 of 24
INPUT COMMON-MODE VOLTAGE RANGE
The ADA4939-1/ADA4939-2 input common-mode range is
centered between the two supply rails, in contrast to other ADC
drivers with level-shifted input ranges, such as the ADA4937-1/
ADA4937-2. The centered input common-mode range is best
suited to ac-coupled, differential-to-differential and dual supply
applications.
For 5 V single-supply operation, the input common-mode
range at the summing nodes of the amplifier is specified as
1.1 V to 3.9 V and is specified as 0.9 V to 2.4 V with a 3.3 V
supply. To avoid nonlinearities, the voltage swing at the +IN
and −IN terminals must be confined to these ranges.
INPUT AND OUTPUT CAPACITIVE AC COUPLING
Input ac coupling capacitors can be inserted between the source
and RG. This ac coupling blocks the flow of the dc common-
mode feedback current and causes the ADA4939-1/ADA4939-2
dc input common-mode voltage to equal the dc output common-
mode voltage. These ac coupling capacitors must be placed in
both loops to keep the feedback factors matched.
Output ac coupling capacitors can be placed in series between
each output and its respective load. See Figure 54 for an
example that uses input and output capacitive ac coupling.
MINIMUM RG VALUE OF 50 Ω
Due to the wide bandwidth of the ADA4939-1/ADA4939-2, the
value of RG must be greater than or equal to 50 Ω to provide
sufficient damping in the amplifier front end. In the terminated
case, RG includes the Thevenin resistance of the source and load
terminations.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM/VOCMx pin of the ADA4939-1/ADA4939-2 is internally
biased with a voltage divider comprising two 20 kΩ resistors at a
voltage approximately equal to the midsupply point, [(+VS) +
(−VS)]/2. Because of this internal divider, the VOCM/VOCMx pin
sources and sinks current, depending on the externally applied
voltage and its associated source resistance. Relying on the
internal bias results in an output common-mode voltage that is
within about 100 mV of the expected value.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source or resistor divider be used with source resistance less
than 100 Ω. The output common-mode offset listed in the
Specifications section assumes that the VOCM input is driven by
a low impedance voltage source.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM/VOCMx pin is approximately 10 kΩ. If
multiple ADA4939-1/ADA4939-2 devices share one reference
output, it is recommended that a buffer be used.
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 22 of 24
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4939-1 is sensitive to the PCB
environment in which it operates. Realizing its superior
performance requires attention to the details of high speed PCB
design. This section shows a detailed example of how the
ADA4939-1 was addressed.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4939-1 as possible.
However, the area near the feedback resistors (RF), gain resistors
(RG), and the input summing nodes (Pin 2 and Pin 3) must be
cleared of all ground and power planes (see Figure 51). Clearing
the ground and power planes minimizes any stray capacitance at
these nodes and prevents peaking of the response of the amplifier
at high frequencies.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity four-layer
circuit board, as described in EIA/JESD 51-7.
0
7429-058
Figure 51. Ground and Power Plane Voiding in Vicinity of RF and RG
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended to use two parallel bypass
capacitors (1000 pF and 0.1 μF) for each supply. Place the 1000 pF
capacitor closer to the device. Further away, provide low frequency
bypassing, using 10 μF tantalum capacitors from each supply to
ground.
Ensure that signal routing is short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a
symmetrical layout to maximize balanced performance. When
routing differential signals over a long distance, ensure that the
PCB traces are close together, and twist any differential wiring
such that the loop area is minimized which reduces radiated
energy and makes the circuit less susceptible to interference.
1.30
0.80
0.80
1.30
07429-059
Figure 52. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
0.30
PLATED
VIA HOLE
1.30
GROUND PLANE
POWER PLANE
BOTTOM METAL
TOP METAL
07429-060
Figure 53. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
Data Sheet ADA4939-1/ADA4939-2
Rev. A | Page 23 of 24
HIGH PERFORMANCE ADC DRIVING
The ADA4939-1/ADA4939-2 are ideally suited for broadband
ac-coupled and differential-to-differential applications on a
single supply.
The circuit in Figure 54 shows a front-end connection for an
ADA4939-1 driving an AD9445, 14-bit, 105 MSPS ADC, with
ac coupling on the ADA4939-1 input and output. (The AD9445
achieves its optimum performance when driven differentially.)
The ADA4939-1 eliminates the need for a transformer to drive
the ADC and perform a single-ended-to-differential conversion
and buffering of the driving signal.
The ADA4939-1 is configured with a single 5 V supply and gain
of 2 for a single-ended input to differential output. The 60.4 Ω
termination resistor, in parallel with the single-ended input
impedance of approximately 300 Ω, provides a 50 Ω termination
for the source. The additional 27.4 Ω (227.4 Ω total) at the
inverting input balances the parallel impedance of the 50 Ω
source and the termination resistor driving the noninverting input.
In this example, the signal generator has a 1 V p-p symmetric,
ground-referenced bipolar output when terminated in 50 Ω.
The VOCM pin of the ADA4939-1 is bypassed for noise reduction
and left floating such that the internal divider sets the output
common-mode voltage nominally at midsupply. Because the
inputs are ac-coupled, no dc common-mode current flows in
the feedback loops, and a nominal dc level of midsupply is
present at the amplifier input terminals. Besides placing the
amplifier inputs at their optimum levels, the ac coupling technique
lightens the load on the amplifier and dissipates less power than
applications with dc-coupled inputs. With an output common-
mode voltage of nominally 2.5 V, each ADA4939-1 output
swings between 2.0 V and 3.0 V, providing a gain of 2 and a 2 V p-p
differential signal to the ADC input.
The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.
The AD9445 is configured for a 2 V p-p full-scale input by
connecting the SENSE pin to AGND, as shown in Figure 54.
07429-061
VIN–
VIN+
47pF
30nH
30nH
24.3Ω
24.3Ω
50Ω
SIGNAL
GENERATOR
200Ω
200Ω
V
OCM
5V
+
60.4Ω
412Ω
27.4Ω
412Ω
14
BUFFER T/H
ADC
CLOCK/
TIMING REF
SENSEAGND
0.1µF0.1µF
0.1µF0.1µF 0.1µF
AD9445
3.3V (A)
AVDD1
5V (A)
AVDD2
3.3V (D)
DRVDD
ADA4939-1
Figure 54. ADA4939-1 Driving an AD9445 ADC with AC-Coupled Input and Output
ADA4939-1/ADA4939-2 Data Sheet
Rev. A | Page 24 of 24
OUTLINE DIMENSIONS
1.45
1.30 SQ
1.15
111808-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-8.
06-11-2012-A
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.20
2.10 SQ
2.00
1
24
7
12
13
18
19
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity Branding
ADA4939-1YCPZ-R2 −40°C to +105°C 16-Lead LFCSP CP-16-21 250 H1E
ADA4939-1YCPZ-RL −40°C to +105°C 16-Lead LFCSP CP-16-21 5,000 H1E
ADA4939-1YCPZ-R7 −40°C to +105°C 16-Lead LFCSP CP-16-21 1,500 H1E
ADA4939-2YCPZ-R2 −40°C to +105°C 24-Lead LFCSP CP-24-10 250
ADA4939-2YCPZ-RL −40°C to +105°C 24-Lead LFCSP CP-24-10 5,000
ADA4939-2YCPZ-R7 −40°C to +105°C 24-Lead LFCSP CP-24-10 1,500
1 Z = RoHS Compliant Part.
©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07429-0-5/16(A)
