APW7093 3A, 1MHz, Step Down DC/DC Regulator Features General Description * * * * Source/Sink 3A The APW7093 is a reversible energy flow, constant-off- Up to 1MHz Switches Frequency time, pulse-width modulated (PWM), step-down DC-DC converter. It is ideal for use in notebook and sub-note- Up to 94% Efficiency book computers that require 1.1V to 5V active termination power supplies. This device features an internal PMOS Internal PMOS/NMOS Switches power switch and internal synchronous rectifier for high efficiency and reduced component count. The internal - 70m/40m On-Resistance at VIN = 4.5V - 90m/60m On-Resistance at VIN = 3V * * * * * * * * * 90m PMOS power switch and 60m NMOS synchronous-rectifier switch easily deliver continuous load cur- 1% Output Accuracy rents up to 3A. The APW7093 accurately tracks an external reference voltage, produces an adjustable output from 1.1V to VIN Adjustable Output Voltage 3V to +5.5V Input Voltage Range 1.1V to VIN, and achieves efficiencies as high as 94%. The APW7093 uses a unique current-mode, constant- <1A Shutdown Supply Current off-time, PWM control scheme that allows the output to source or sink current. This feature allows energy to re- Programmable Constant-Off-Time Operation Thermal Shutdown turn to the input power supply that otherwise would be wasted. The programmable constant-off-time architecture Adjustable Soft-Start Inrush Current Limiting sets switching frequencies up to 1MHz, allowing the user to optimize performance trade-offs between efficiency, Output Short-Circuit Protection Lead Free and Green Devices Available output switching noise, component size, and cost. The APW7093 features an adjustable soft-start to limit surge (RoHS Compliant) currents during startup, a 100% duty-cycle mode for lowdropout operation, and a low-power shutdown mode that Applications * * * * * * * disables the power switches and reduces supply current below 1A. The APW7093 is available in a 32-pin TQFN with an exposed backside pad or a 16-pin SSOP. Motherboard Graphics Cards Cable or DSL Modems, Set Top Boxes DSP Supplies Memory Supplies 5V Input DC-DC Regulators Distributed Power Supplies ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 1 www.anpec.com.tw APW7093 N.C LX N.C LX N.C N.C N.C 32 SHDN Pin Configuration 25 SHDN 1 16 LX IN 2 15 PGND LX LX 3 14 LX LX IN 4 13 PGND 1 N.C 24 PGND IN PGND LX IN APW7093 APW7093 PGND N.C SS N.C N.C VCC EXTREF 8 N.C REF GND FB N.C N.C N.C 9 TOFF GND 17 SS 5 12 VCC EXTREF 6 11 GND TOFF 7 10 REF FB 8 9 GND 16 TQFN 5x5 - 32 SSOP - 16 Ordering and Marking Information APW7093 Package Code N : SSOP-16 QB : TQFN 5x5-32 Operating Ambient Temperature Range I : -45 to 85 oC Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code APW7093 N : APW7093 QB : APW7093 XXXXX XXXXX - Date Code APW7093 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCC (Note 1) Parameter Rating Unit -0.3 ~ +6 V IN to VCC 0.3 V GND to PGND 0.3 V -0.3 ~ VCC+0.3 V VCC to GND SHDN,SS, FB, TOFF, VREF to GND Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 2 www.anpec.com.tw APW7093 Absolute Maximum Ratings (Cont.) Symbol (Note 1) Rating Unit -0.3 ~ VIN-1.7 V Power Dissipation; Part Mount on 1in2 of 1oz copper; TQFN-32 1.6 W Power Dissipation; Part Mount on 1in2 of 1oz copper; SSOP-16 1 W LX Current -3.5 ~ +4.1 A TA Operating Temperature Range -40 ~ +85 C TJ Junction Temperature VEXTREF Parameter EXTREF to GND PD TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature,10 Seconds +150 C -65~+150 C 260 C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommend Operating Conditions Symbol VIN Range Parameter Input Voltage Range Unit Min. Typ. Max. 3 - 5.5 V VOUT Output Voltage Range (VEXTREF<= VIN-1.7V) 1.1 - VIN V COUT Output Capacitor 220 330 - F Input Capacitor (Low ESR) 22 33 - F 0.56 1 - H - - - k CIN L RTOFF Inductor Programmed Off-Time Resistance(Refer to Application section for further Information.) Electrical Characteristics (VIN=VCC=3.3V, VEXTREF=+1.1V, TA = -45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC). APW7093 Symbol VIN, VCC Parameter Input Voltage Feedback Voltage Accuracy VFB VEXTREF VREF RPMOS Test Conditions (VFB -VEXTREF) VIN=VCC=+3.0V to +5.5V, ILOAD=0,VEXTREF=1.25V (Note 2) Feedback Load Regulation Error ILOAD=-3A to +3A, VEXTREF=+1.25V External Reference Voltage Range VIN=VCC=+3.0 to +5.5V Reference Voltage Typ. Max. 3.0 - 5.5 V -12 - +12 mV - 20 - mV VREF 0.01 VIN - - 1.7 V 1.078 1.100 1.122 V - 0.3 2 mV VIN=+4.5V - 70 140 VIN=+3.0V - 90 180 Reference Load Regulation IREF= -1A to +10A PMOS Switch On-Resistance ILX=0.5A Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 Unit Min. m 3 www.anpec.com.tw APW7093 Electrical Characteristics (Cont.) (VIN=VCC=3.3V, VEXTREF=+1.1V, TA = -45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC). APW7093 Symbol RNMOS Parameter NMOS Switch On-Resistance Test Conditions Unit Min. Typ. Max. VIN=+4.5V - 50 100 VIN=+3.0V - 60 120 3.5 4.1 4.7 A MHz ILX=0.5A m ILIMIT Current Limit Threshold VIN > VLX fSW Switching Frequency (Note3) - - 1 fSW =500kHz - 1 - fSW =500kHz - 32 - Shutdown Supply Current SHDN = GND, ICC+ IIN - <1 15 A Thermal Shutdown Threshold Hysteresis =15C - 150 - C Under Voltage Lockout Threshold VCC falling, hysteresis = 90mV 2.5 2.6 2.7 V FB Input Current VFB=VEXTREF+0.1V 0 60 250 nA RTOFF=30.1k 0.40 0.44 0.48 RTOFF=110k 1.10 1.20 1.30 RTOFF=499k 4.3 4.8 5.3 ICC No Load Supply Current IIN I SHDN UVLO IFB TOFF Off-Time mA Startup Off-Time TON On-Time ISS SS Source Current ISS SS Sink Current SHDN Input Current IOUT(RMS) 0.34 - - s 4 5 6 A VSS=1V 2 - - A V SHDN =0, VCC -1 - +1 A - - 0.8 2.0 - - - - 3.1 V SHDN Logic Levels Maximum Output RMS Current VIL VIH IOUT(RMS) s 4xTOFF (Note 3) VIL VIH s SHDN Logic Levels Maximum Output RMS Current - - 0.8 2.0 - - - - 3.1 ARMS V ARMS Note 2: The output voltage will have a DC-regulation level lower than the feedback error comparator threshold by 50% of the ripple. Note 3: Recommended operating frequency, not production tested. Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 4 www.anpec.com.tw APW7093 Typical Operating Characteristics (Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68H, RTOFF=68k; for VIN=5V: L=1H, TOFF=100k. TA=25oC if not specially) Effienciency vs. Output Current No Load Supply Current vs. Input Voltage 100 50 VIN=5V, VOUT=3.3V 95 No Load Supply Current(mA) 90 Efficiency(%) 85 80 75 VIN=5V, VOUT=1.25V 70 65 VIN=5V, VOUT=2.5V 60 VIN=3.3V, VOUT=1.25V 55 50 40 30 VOUT=1.25V RTOFF=68k 20 10 45 0 40 0 1 2 0 3 1 2 3 4 5 6 500 600 Input Voltage(V) Output Current(A) OFF-TIME vs. RTOFF Switching Frequency vs. Output Current 900 6 5 700 VIN=3.3V 600 OFF-TIME(s) Switching Frequency(kHz) 800 500 400 V IN=5V 300 4 3 2 200 1 100 0 0 0 1 2 3 0 200 300 400 RTOFF(k) Output Current(A) Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 100 5 www.anpec.com.tw APW7093 Typical Operating Characteristics (Cont.) (Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68H, RTOFF=68k; for VIN=5V: L=1H, TOFF=100k. TA=25oC if not specially) Start-Up and Shut Down VREF vs. Input Voltage 1.114 SHDN=2V/DIV VREF(V) 1.113 1.112 VSS=2V/DIV 1.111 IN=1A/DIV 1.110 3.0 3.5 4.0 4.5 5.0 TIME 2ms/DIV 5.5 VIN=3.3V, VOUT=1.25V, ROUT=0.4 Input Voltage(V) Load Transient Response Load Transient Response IOUT=3A IOUT =0A 0A IOUT= IOUT=0A VOUT 100mV/DIV V OUT 100mV/DIV VOUT 100mV/DIV TIME 20s/DIV TIME 20us/DIV TIME 20s/DIV di VIN=5V, VOUT=1.25V, IOUT= 3A IOUT=3A dt = di 3A VIN=5V, VOUT=2.5V, s Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 6 dt = 3A s www.anpec.com.tw APW7093 Typical Operating Characteristics (Cont.) (Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68H, RTOFF=68k; for VIN=5V: L=1H, TOFF=100k. TA=25oC if not specially) Load Transient Response Line Transient Response IOUT=3A VIN=5.0V IOUT=0A VIN=3.0V VOUT 100mV/DIV VOUT 100mV/DIV TIME 20s/DIV VIN=3.3V, VOUT=1.25V, di dt TIME 40s/DIV = 3A s Light Load Waveform Heavy Load Waveform VLX 5V/DIV VLX 5V/DIV ILX 1A/DIV ILX 1A/DIV VOUT 50mV/DIV VOUT 50mV/DIV TIME 1s/DIV TIME 1s/DIV IOUT=100mA Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 IOUT=3A 7 www.anpec.com.tw APW7093 Typical Operating Characteristics (Cont.) (Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68H, RTOFF=68k; for VIN=5V: L=1H, TOFF=100k. TA=25oC if not specially) VREF vs. Temperature Output Voltage vs. Temperature 1.118 1.255 1.116 1.114 1.253 VIN=3.3V 1.251 1.110 V OUT(V) V REF (V) 1.112 1.108 1.106 VIN=3.3V IOUT=0A 1.249 1.104 1.247 1.102 1.100 1.245 1.098 -50 -25 0 25 50 75 100 -50 125 0 25 50 75 100 125 Temperature(C) Temperature(C) Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 -25 8 www.anpec.com.tw APW7093 Pin Description PIN FUNCTION NO. NAME TQFN 5x5-23 SSOP-16 N.C 1,5,7,9,11,13,1 6,19,25,26,28, 30,32 X IN 2,4 2,4 LX 3,21,22,27,29 3,14,16 SS 6 5 EXTREF 8 6 TOFF 10 7 FB 12 8 GND 14,17,backsid e pad, corner tabs 9 Analog Ground. Connect exposed backside pad and corner tabs to analog GND. REF 15 10 Reference Output. Bypass REF to GND with a 0.1F capacitor. GND 17 11 Tie to GND (pin 13 QFN; pin 9 SSOP) VCC 18 12 PGND 20,23,24 13,15 SHDN 31 1 Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 No Connection, Not internally connected. Supply Voltage Input for the internal PMOS Power Switch. Not internally connected. Externally connect all pins for proper operation. Inductor Connection. Connection for the drains of the PMOS power switch and NMOS synchronous-rectifier switch. Connect the inductor from this node to the output filter capacitor and load. Not internally connected. Externally connect all pins for proper operation. Soft-Start Connect a capacitor from SS to GND to limit inrush current during start-up. External Reference Input Feedback input regulates to VEXTREF. The PWM controller remains off until EXTREF is greater than REF. Off-Time Select Input. Sets the PMOS power switch constant-off-time. Connect a resistor from TOFF to GND to adjust the PMOS switch off-time. Feedback Input. Connect directly to output for fixed-voltage operation or to a resistive-divider for adjustable operating modes. Analog Supply Voltage Input. Supplies internal analog circuitry. Bypass VCC with a 10 and 1F low-pass filter. See Figure2. Power Ground. Internally connected to the internal NMOS synchronous-rectifier switch. Shutdown control Input Drive SHDN low to disable the reference, control circuitry, and internal MOSFETs. Drive high or connect to VCC for normal operation. 9 www.anpec.com.tw APW7093 Block Diagram APW7093 SS VCC VIN VIN +3.0V TO +5.5V FB IN CURRENT SENSE + _ EXTREF PWM LOGIC AND DRIVERS SHDN REF CIN REF L X L COUT TIMER GND PGND RTOFF Typical Application Circuit APW7093 VIN L 33F IN 1F VOUT LX 10 220F 15m PGND VCC 1F GND SHDN VEXTREF R2 FB EXTREF REF TOFF 20K SS 0.1F RTOFF 0.01F FOR VIN =5V : L=1H, RToff=100k FOR VIN=3.3V : L=0.68H, RToff=68k Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 10 www.anpec.com.tw APW7093 Function Description The APW7093 synchronous, current-mode, constant-offtime, PWM DC-DC converter steps down input voltages current flows through the internal body diode of the NMOS switch. of 3V to 5.5V to an adjustable output voltage from 1.1V to VIN, as set by the voltage applied at EXTREF. It sources Current Sourcing and Sinking By operating in a constant-off-time and pseudo-fixed-fre- and sinks up 3A of output current. Internal switches composed of a 90mW PMOS power switch and a 60mW NMOS quency mode, the APW7093 can both source and sink current. Depending on the output current requirement, synchronous-rectifier switch improve efficiency, reduce component count, and eliminate the need for an external the circuit operates in two modes. In the first mode, the output draws current and the APW7093 behaves as a Schottky diode across the synchronous switch. regular buck controller, sourcing current to the output from the input supply rail. However, when the output is sup- The APW7093 operates in a constant-off-time mode under all loads. A single resistor-programmable constanttradeoffs in efficiency, switching noise, component size, plied by another source, the APW7093 operates in a second mode as a synchronous boost, taking power from and cost. When power is drawn from a regulated supply, constant-off-time PWM architecture essentially provides the output and returning it to the input. constant-frequency operation. This architecture has the inherent advantage of quick response to line and load Thermal Resistance Junction-to-ambient thermal resistance, JA, is highly dependent on the amount of copper area immediately sur- transients. The APW7093's current-mode, constant-offtime PWM architecture regulates the output voltage by rounding the IC leads. The APW7093 QFN package has 1 in square of copper area and a thermal resistance of changing the PMOS switch on-time relative to the constant-off-time. 50C/W with no forced airflow. The APW7093 16-pin SSOP Constant-Off-Time Operation In the constant-off-time architecture, the FB voltage com- evaluation kit has 0.5 in square of copper area and a thermal resistance of 80C/W with no forced airflow. Air- parator turns the PMOS switch on at the end of each offtime, keeping the device in continuous-conduction mode. flow over the board significantly reduces the junction-toambient thermal resistance. For heat sinking purposes, The PMOS switch remains on until the feedback voltage exceeds the external reference voltage (VEXTREF) or the it is essential to connect the exposed backside pad of the TQFN package to a large analog ground plane. positive current limit is reached. When the PMOS switch turns off, it remains off for the programmed off-time (TOFF). Shutdown Drive SHDN to a logic-level low to place the APW7093 in To control the current under short-circuit conditions, the PMOS switch remains off for approximately 4xTOFF when low-power shutdown mode and reduce supply current less than 1 A. In shutdown, all circuitry and internal VFB<VEXTREF/4. Synchronous Rectification MOSFETs turn off, so the LX node becomes high impedance. Drive SHDN to a logic-level high or connect In a step-down regulator without synchronous rectification, to VCC for normal operation. an external Schottky diode provides a path for current to flow when the inductor is discharging. Replacing the Power Dissipation Power dissipation in APW7093 is dominated by conduction losses in the two internal power switches. Power Schottky diode with a low-resistance NMOS synchronous switch reduces conduction losses and improves dissipation due to charging and discharging the gate capacitance of the internal switches (i.e., switching losses) efficiency. The NMOS synchronous-rectifier switch turns on following a short delay (typ. 20ns) after the PMOS power is approximately: switch turns off, thus preventing cross-conduction or "shoot-through." In constant-off-time mode, the synchro- 2 PD(CAP) = C x VIN x fSW nous-rectifier switch turns off just prior to the PMOS power switch turning on. While both switches are off, inductor Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 11 www.anpec.com.tw APW7093 Function Description (Cont.) Power Dissipation (Cont.) where C = 500pF and fSW is the switching frequency. Resistive losses in the two power switches are approximated by: 2 PD(RES) = IOUT x R PMOS where RPMOS is the on-resistance of the PMOS switch. The junction-to-ambient thermal resistance required to dissipate this amount of power is calculated by: JA = (TJ,MAX - TA,MAX) / (PD(CAP) + PD(RES)) where: JA = junction-to-ambient thermal resistance TJ,MAX = maximum junction temperature TA,MAX = maximum ambient temperature Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 12 www.anpec.com.tw APW7093 Application Information For typical applications, use the recommended component values in Figure 2. For other applications, take the VOUT=VEXTREF LX following steps: 1.Select the desired PWM-mode switching frequency. APW7093 See Figure 3 for maximum operating frequency. 2. Select the constant-off-time as a function of input voltage, output voltage, and switching frequency. VEXTREF EXTREF FB 1400 1200 1.1V VEXTREF VIN - 1.7V 1000 Figure 4. Adjsting the Output Voltage using EXTREF 800 VOUT 600 LX 400 APW7093 200 0 R2 FB 2.8 3.3 3.8 4.3 4.8 5.3 EXTREF REF Figure 3. Maximum Recommended Operation Frequency R1 3. Select RTOFF as the function of off-time. 4. Select the inductor as the function of output voltage, off-time, and peak-to-peak inductor current. V R2 = R1 OUT - 1 VEXTREF Setting the Output Voltage An external voltage applied to the EXTREF pin sets the output voltage of the APW7093. This can come directly from another voltage source or external reference. When where VEXTREF = VREF = 1.1V Figure 5. Adjsting the Output Voltage using FB FB is directly tied to the output (Figure 4), the output voltage range is limited by the external reference's input volt- Programming the Switching Frequency and Off-Time and On-Time age limits. VEXTREF should be limited less than VIN-1.7V. Failure to comply can cause the part to operate abnor- The APW7093 features a programmable PWM-mode mally and may cause part damage. Alternatively, the output can be adjusted to VIN by connecting FB to a resistor- switching frequency, which is set by the input and output voltage and the value of RTOFF, connected from TOFF to the divider between the output voltage and the ground (Figure 5). Use 20k for R1. R2 is given by: R2 = R1 VOUT VEXTREF GND. RTOFF sets the PMOS power switch off-time in PWM mode. Use the following equation to select the off-time while sourcing current according to the desired switching frequency in PWM mode: - 1 TOFF = Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 13 (VIN - VOUT - VPMOS ) fSW (VIN - VPMOS + VNMOS ) www.anpec.com.tw APW7093 Application Information(Cont.) Programming the Switching Frequency and Off-Time Inductor Selection and On-Time (Cont.) The key inductor parameters must be specified: inductor value (L) and peak current (IPEAK). A lower value of inductor where: TOFF = the programmed off-time VIN = the input voltage allows smaller size but results in higher losses and ripple. A good compromise between size and losses is found at VOUT = the output voltage VPMOS = the voltage drop across the internal PMOS approximately a 25% ripple current to load current ratio (I/IOUT = 0.25). L= power switch |IOUT X RPMOS| VNMOS = the voltage drop across the internal NMOS synchronous-rectifier switch |IOUT X RNMOS| fSW = switching frequency VOUT x TOFF IOUT x 0.25 The peak inductor current at full load is calculated by: IPEAK = IOUT + Make sure that TON and TOFF are greater than 400ns when sourcing current. Select RTOFF according to the equation: VOUT x TOFF 2xL where IOUT is the maximum source or sink current. R TOFF = (TOFF - 0.18s) x (109k /1.00s) Choose an inductor with a saturation current at least as Recommended values for RTOFF range from 24k to 410k for off-times of 0.4s to 4s. Usually, the switch- high as the peak inductor current. Additionally, verify the ing frequency is set as high as possible, and the inductor value is reduced to minimize the energy transferred from ISOURCE) does not exceed the positive current limit. The peak inductor current while sourcing output current (IOUT = inductor to capacitor during load-step recovery. inductor selecting should exhibit low losses at the cho- The operating frequency of the APW7093 is determined primarily by TOFF (set by RTOFF), VIN, and VOUT shown in the sen operating frequency. Input Capacitor Selection following equation: fSW = The input filter capacitor reduces peak currents and noise (VIN - VOUT - VPMOS ) TOFF (VIN - VPMOS + VNMOS ) at the voltage source. A 22F to 47F capacitor may be required for higher power and dynamic loads. Low-ESR However, as the output current increases, the voltage drop across the NMOS and PMOS switches increases and the and low-ESL Tantalum or ceramic capacitor should be voltage across the inductor decreases. This causes the frequency to drop. Assuming RPMOS = RNMOS, the change in Output Capacitor Selection suitable. The output filter capacitor affects the output voltage ripple, frequency can be approximated with the following equation: fSW = output load-transient response, and feedback loop stability. The output filter capacitor must have low enough -IOUT x R PMOS VIN x TOFF E SR t o m e et o ut p ut r ip pl e an d l oad tr ansi en t requirements, yet have high enough ESR to satisfy sta- where RPMOS is the resistance of the internal MOSFETs (70m typ). When sinking current, the switching frequency increases due to the on-resistances of the internal switches adding bility requirements. Also, the capacitance value must high enough to guarantee stability and absorb the inductor energy going from a full-load sourcing to full load sinking condition without exceeding the maximum output to the voltage across the inductor, reducing the on-time. Calculate TON when sinking current using the equation: tolerance. In applications where the output is subject to large load transients, the output capacitor's size typically depends VOUT - VNMOS TON = TOFF VIN - VOUT + VPMOS Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 on how much ESR is needed to prevent the output from dipping too low under a load transient. 14 www.anpec.com.tw APW7093 Application Information(Cont.) Output Capacitor Selection (Cont.) SHDN R ESR VOUT /IOUT(MAX) 0 The actual microfarad capacitance value required is de- VIN fined by the physical size needed to achieve low ESR, and by the chemistry of the capacitor technology. Thus, VSS(A) the capacitor is usually selected by ESR, size and voltage rating rather than by capacitance value. When using low- 0 capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity ILIMIT(A) needed to prevent overshoot and undershoot from causing problems during load transients. Generally, once 0 1.8V 0.7V enough capacitance is added to meet the overshoot requirement, undershoot at the rising-load edge is no ILIMIT t Figure 6. Soft-Start Current Limit longer a problem. Input Source Soft-Start The output of the APW7093 can accept current due to the Soft-start allows a gradual increase of the internal cur- reversible properties of the buck and the boost converter. When voltage at the output of the APW7093 (low-voltage rent limit to reduce input surge currents at start-up and at exit from shutdown. A timing capacitor, CSS, placed from port) exceeds or equals the output set voltage the flow of energy reverses, going from the output to the input (high- SS to GND sets the rate at which the internal current limit is changed. Upon power-up, when the device comes out voltage port). If the input (high voltage port) is not connected to a low-impedance source capable of absorbing of under-voltage lockout (2.6V typ.) or after the SHDN pin is pulled high, a 4.7A constant current source charges energy, the voltage at the input will rise. This voltage can violate the absolute maximum voltage at the input of the the soft-start capacitor and the voltage on SS increases. When the voltage on SS is less than approximately 0.7V, APW7093 and destroy the part. This occurs when sinking current because the topology acts as a boost converter, the current limit is set to zero. As the voltage increases from 0.7V to approximately VIN, the current limit is adjusted pumping energy from the low-voltage side (the output), to the high-voltage side (the input). The input (high-voltage from 0V to the current-limit threshold. The voltage across the soft-start capacitor changes with time according to the side) voltage is limited only by the clamping effect of the voltage source connected there. To avoid this problem, following equation: VSS make sure the input to the APW7093 is connected to a low impedance, two quadrant supply or that the load 4.7A x t = C SS (excluding the APW7093) connected to that supply consumes more power than the amount being transferred The output current limit during soft-start varies with the voltage on the soft-start pin, SS, according to the follow- from the APW7093 output to the input. ing equation: ILIIM(SS) = Current Limit and Short Circuit Protection (VSS - 0.7V) x ILIMIT , VSS 1.8V 1.1V The APW7093 monitors sourcing and sinking current, and limits the maximum output current to prevent damaging where ILIMIT is the current-limit threshold from the Electrical Characteristics. The constant-current source stops during overload or short-circuit. charging once the voltage across the soft-start capacitor reaches 1.8V. Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 15 www.anpec.com.tw APW7093 Application Information(Cont.) Circuit Layout and Grounding Good layout is necessary to achieve the APW7093's intended output power level, high efficiency, and low noise. Good layout includes the use of ground planes, careful component placement, and correct routing of traces using appropriate trace widths. The following points are in order of decreasing importance: 1. Minimize switched-current and high-current ground loops. Connect the input capacitor's ground, the output capacitor's ground, and PGND close together. Split the ground connections. Use separate traces or planes for the PGND and GND and tie them together at a single point. 2. The output capacitor should be placed close to the output terminals to obtain better smoothing effect on the output ripple. 3. Connect the input filter capacitor less than 5mm away from IN. The connecting copper trace carries large currents and must be at least 1mm wide, preferably 2.5mm. 4.Place the LX node components as close together and as near to the device as possible. This reduces resistive and switching losses as well as noise. 5.Ground planes are essential for optimum performance. In most applications, the circuit is located on a multilayer board and full use of the four or more layers is recommended. For heat dissipation, connect the exposed backside pad of the QFN package to a large analog ground plane, preferably on a surface of the board that receives good airflow. If the ground plane is located on the top layer, use the N.C. pins adjacent to the GND to lower thermal resistance to the ground plane. If the ground is located e l s e w here, use several vias to lower thermal resistance. Typical applications use multiple ground planes to minimize thermal resistance. Avoid large AC currents through the analog ground plane. Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 16 www.anpec.com.tw APW7093 Package Information SSOP-16 D h X 45 E E1 SEE VIEW A c A 0.25 b A2 A1 GAUGE PLANE SEATING PLANE L 0 e VIEW A S Y M B O L SSOP-16 MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.24 b 0.20 0.30 0.008 0.012 c 0.15 0.25 0.006 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 0.635 BSC 0.025 BSC L 0.40 1.27 0.016 0.050 h 0.25 0.50 0.010 0.020 0 0 8 0 8 Note : 1. Follow JEDEC MO-137 AB. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 17 www.anpec.com.tw APW7093 Package Information TQFN5x5-32 A b E D D2 A1 A3 L K E2 Pin 1 Corner e S Y M B O L TQFN5x5-32 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 4.90 5.10 0.193 0.201 0.150 D2 3.50 3.80 0.138 E 4.90 5.10 0.193 0.201 E2 3.50 3.80 0.138 0.150 e 0.50 BSC L 0.35 K 0.20 0.020 BSC 0.014 0.45 0.018 0.008 Note : Followed JEDEC MO-220 WHHD-4. Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 18 www.anpec.com.tw APW7093 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 330.02.00 50 MIN. SSOP-16 P0 T1 C d P1 P2 D0 D1 4.000.10 8.000.10 2.000.05 1.5+0.10 -0.00 Application A H 330.02.00 50 MIN. TQFN5x5-32 D W E1 F 12.4+2.00 13.0+0.50 1.5 MIN. 20.2 MIN. 12.00.30 1.750.10 5.50 0.10 -0.00 -0.20 T1 C 1.5 MIN. d T A0 B0 0.6+0.00 6.400.20 5.200.20 2.10 0.20 -0.40 D W E1 12.4+2.00 13.0+0.50 1.5 MIN. 20.2 MIN. 12.00.30 1.750.10 -0.00 -0.20 P0 P1 P2 D0 D1 4.00.10 8.00.10 2.00.10 1.5+0.10 -0.00 1.5 MIN. K0 T A0 B0 F 5.50.10 K0 0.6+0.00 5.300.20 5.300.20 1.30 0.20 -0.40 (mm) Devices Per Unit Package Type Unit Quantity SSOP-16 Tape & Reel 2500 TQFN5x5-32 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 19 www.anpec.com.tw APW7093 Taping Direction Information SSOP-16 USER DIRECTION OF FEED TQFN 5x5-32 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 20 www.anpec.com.tw APW7093 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly Pb-Free Assembly 3C/second max. 3C/second max. 100C 150C 60-120 seconds 150C 200C 60-180 seconds 183C 60-150 seconds 217C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 21 www.anpec.com.tw APW7093 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures Package Thickness <2.5 mm 2.5 mm 3 Volume mm3 <350 240 +0/-5C 225 +0/-5C Volume mm 350 225 +0/-5C 225 +0/-5C Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Package Thickness Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.6 - Nov., 2008 22 www.anpec.com.tw