Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
3A, 1MHz, Step Down DC/DC Regulator
•Source/Sink 3A
•Up to 1MHz Switches Frequency
•Up to 94% Efficiency
•Internal PMOS/NMOS Switches
- 70mΩ/40mΩ On-Resistance at VIN = 4.5V
- 90mΩ/60mΩ On-Resistance at VIN = 3V
•±1% Output Accuracy
•1.1V to VIN Adjustable Output Voltage
•3V to +5.5V Input Voltage Range
•<1µA Shutdown Supply Current
•Programmable Constant-Off-Time Operation
•Thermal Shutdown
•Adjustable Soft-Start Inrush Current Limiting
•Output Short-Circuit Protection
•Lead Free and Green Devices Available
(RoHS Compliant)
Features
Applications
General Description
The APW7093 is a reversible energy flow, constant-off-
time, pulse-width modulated (PWM), step-down DC-DC
converter. It is ideal for use in notebook and sub-note-
book computers that require 1.1V to 5V active termination
power supplies. This device features an internal PMOS
power switch and internal synchronous rectifier for high
efficiency and reduced component count. The internal
90mΩ PMOS power switch and 60mΩ NMOS synchro-
nous-rectifier switch easily deliver continuous load cur-
rents up to 3A. The APW7093 accurately tracks an exter-
nal reference voltage, produces an adjustable output from
1.1V to VIN, and achieves efficiencies as high as 94%.
The APW7093 uses a unique current-mode, constant-
off-time, PWM control scheme that allows the output to
source or sink current. This feature allows energy to re-
turn to the input power supply that otherwise would be
wasted. The programmable constant-off-time architecture
sets switching frequencies up to 1MHz, allowing the user
to optimize performance trade-offs between efficiency,
output switching noise, component size, and cost. The
APW7093 features an adjustable soft-start to limit surge
currents during startup, a 100% duty-cycle mode for low-
dropout operation, and a low-power shutdown mode that
disables the power switches and reduces supply current
below 1µA. The APW7093 is available in a 32-pin TQFN
with an exposed backside pad or a 16-pin SSOP.
•Motherboard
•Graphics Cards
•Cable or DSL Modems, Set Top Boxes
•DSP Supplies
•Memory Supplies
•5V Input DC-DC Regulators
•Distributed Power Supplies
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw2
Ordering and Marking Information
Pin Configuration
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
APW7093
Handling Code
Temperature Range
Package Code
Package Code
N : SSOP-16 QB : TQFN 5x5-32
Operating Ambient Temperature Range
I : -45 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
APW7093 N : XXXXX - Date Code
Assembly Material
APW7093 QB : APW7093
XXXXX XXXXX - Date Code
APW7093
XXXXX
TQFN 5x5 -32 SSOP - 16
EXTREF
N.C
IN
LX
IN
1
8
16
9
SS
APW7093
17
24
25
N.C
N.C
N.C
N.C
N.C
LX
LX
PGND
PGND
LX
LX
VCC
GND
PGND
REF
TOFF
FB
N.C
N.C
GND
32
N.C
N.C
SHDN
N.C
N.C
N.C
PGND
PGND
IN
LX
LX
IN
LX
1
2
3
4
8
6
7
16
5
15
14
13
12
11
10
9
VCC
GND
REF
GND
SS
EXTREF
TOFF
FB
APW7093
SHDN
Symbol
Parameter Rating Unit
VCC VCC to GND -0.3 ~ +6 V
IN to VCC ±0.3 V
GND to PGND ±0.3 V
SHDN,SS, FB, TOFF, VREF to GND -0.3 ~ VCC+0.3 V
Absolute Maximum Ratings (Note 1)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw3
Symbol
Parameter Rating Unit
VEXTREF
EXTREF to GND -0.3 ~ VIN-1.7 V
Power Dissipation; Part Mount on 1in2 of 1oz copper; TQFN-32 1.6 W
PD Power Dissipation; Part Mount on 1in2 of 1oz copper; SSOP-16 1 W
LX Current -3.5 ~ +4.1 A
TA Operating Temperature Range -40 ~ +85 °C
TJ Junction Temperature +150 °C
TSTG Storage Temperature Range -65~+150 °C
TSDR Maximum Lead Soldering Temperature,10 Seconds 260 °C
Recommend Operating Conditions
Absolute Maximum Ratings (Cont.) (Note 1)
Range
Symbol
Parameter Min.
Typ.
Max.
Unit
VIN Input Voltage Range 3 - 5.5 V
VOUT Output Voltage Range (VEXTREF<= VIN-1.7V) 1.1 - VIN V
COUT Output Capacitor 220 330 - µF
CIN Input Capacitor (Low ESR) 22 33 - µF
L Inductor 0.56
1 - µH
RTOFF Programmed Off-Time Resistance(Refer to Application section for further
Information.) - - - kΩ
APW7093
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
VIN, VCC
Input Voltage 3.0 - 5.5 V
Feedback Voltage Accuracy
(VFB –VEXTREF) VIN=VCC=+3.0V to +5.5V,
ILOAD=0,VEXTREF=1.25V (Note 2) -12 - +12 mV
∆VFB Feedback Load Regulation Error ILOAD=-3A to +3A, VEXTREF=+1.25V - 20 - mV
VEXTREF External Reference Voltage Range VIN=VCC=+3.0 to +5.5V VREF -
0.01 - VIN -
1.7 V
VREF Reference Voltage 1.078
1.100
1.122
V
Reference Load Regulation IREF= -1µA to +10µA - 0.3 2 mV
VIN=+4.5V - 70 140
RPMOS PMOS Switch On-Resistance ILX=0.5A VIN=+3.0V - 90 180 mΩ
Electrical Characteristics
(VIN=VCC=3.3V, VEXTREF=+1.1V, TA = -45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC).
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw4
APW7093
Symbol
Parameter Test Conditions Min. Typ.
Max.
Unit
VIN=+4.5V - 50 100
RNMOS NMOS Switch On-Resistance ILX=0.5A VIN=+3.0V - 60 120 mΩ
ILIMIT Current Limit Threshold VIN > VLX 3.5 4.1 4.7 A
fSW Switching Frequency (Note3) - - 1 MHz
ICC fSW =500kHz - 1 -
IIN No Load Supply Current fSW =500kHz - 32 - mA
ISHDN Shutdown Supply Current SHDN = GND, ICC+ IIN - <1 15 µA
Thermal Shutdown Threshold Hysteresis =15°C - 150 - °C
UVLO Under Voltage Lockout Threshold VCC falling, hysteresis = 90mV 2.5 2.6 2.7 V
IFB FB Input Current VFB=VEXTREF+0.1V 0 60 250 nA
RTOFF=30.1kΩ 0.40 0.44 0.48
RTOFF=110kΩ 1.10 1.20 1.30
TOFF Off-Time
RTOFF=499kΩ 4.3 4.8 5.3
µs
Startup Off-Time 4×TOFF µs
TON On-Time (Note 3) 0.34 - - µs
ISS SS Source Current 4 5 6 µA
ISS SS Sink Current VSS=1V 2 - - µA
SHDN Input Current VSHDN =0, VCC -1 - +1 µA
VIL - - 0.8
VIH SHDN Logic Levels 2.0 - - V
IOUT(RMS)
Maximum Output RMS Current - - 3.1 ARMS
VIL - - 0.8
VIH SHDN Logic Levels 2.0 - - V
IOUT(RMS)
Maximum Output RMS Current - - 3.1 ARMS
Electrical Characteristics (Cont.)
(VIN=VCC=3.3V, VEXTREF=+1.1V, TA = -45 to +85oC, unless otherwise noted, Typical values are at TA =+25oC).
Note 2: The output voltage will have a DC-regulation level lower than the feedback error comparator threshold by 50% of the ripple.
Note 3: Recommended operating frequency, not production tested.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw5
40
45
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 0
10
20
30
40
50
0123456
Typical Operating Characteristics
Effienciency vs. Output Current
Output Current(A)
Efficiency(%)
VIN=5V, VOUT=3.3V
VIN=5V, VOUT=1.25V
VIN=3.3V, VOUT=1.25V
No Load Supply Current vs. Input Voltage
Input Voltage(V)
No Load Supply Current(mA)
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68µH, RTOFF=68kΩ; for VIN=5V: L=1µH, TOFF=100kΩ. TA=25oC if not
specially)
VOUT=1.25V
RTOFF=68kΩ
VIN=5V, VOUT=2.5V
0
1
2
3
4
5
6
0100 200 300 400 500 600
0
100
200
300
400
500
600
700
800
900
0 1 2 3
Switching Frequency vs. Output Current
Switching Frequency(kHz)
Output Current(A)
VIN=3.3V
VIN=5V
OFF-TIME vs. RTOFF
OFF-TIME(µs)
RTOFF(kΩ)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw6
Typical Operating Characteristics (Cont.)
1.110
1.111
1.112
1.113
1.114
3.0 3.5 4.0 4.5 5.0 5.5
VREF vs. Input Voltage
VREF(V)
Input Voltage(V)
SHDN=2V/DIV
Start-Up and Shut Down
VIN=3.3V, VOUT=1.25V, ROUT=0.4Ω
VSS=2V/DIV
IN=1A/DIV
TIME 2ms/DIV
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68µH, RTOFF=68kΩ; for VIN=5V: L=1µH, TOFF=100kΩ. TA=25oC if not
specially)
IOUT= 3A
IOUT= 0A
VOUT 100mV/DIV
TIME 20us/DIV
Load Transient Response Load Transient Response
IOUT=3A
IOUT=0A
VOUT 100mV/DIV
TIME 20µs/DIV
VIN=5V, VOUT=1.25V,s
3A
dt
di µ
=
IOUT=3A
IOUT=0A
VOUT 100mV/DIV
TIME 20µs/DIV
VIN=5V, VOUT=2.5V,s
3A
dt
di µ
=
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw7
Typical Operating Characteristics (Cont.)
Load Transient Response Line Transient Response
IOUT=3A
IOUT=0A
VOUT 100mV/DIV
TIME 20µs/DIV
VIN=3.3V, VOUT=1.25V,s
3A
dt
di µ
=
VIN=5.0V
VOUT 100mV/DIV
TIME 40µs/DIV
VIN=3.0V
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68µH, RTOFF=68kΩ; for VIN=5V: L=1µH, TOFF=100kΩ. TA=25oC if not
specially)
Light Load WaveformHeavy Load Waveform
VLX 5V/DIV
ILX 1A/DIV
VOUT 50mV/DIV
IOUT=100mA
VLX 5V/DIV
ILX 1A/DIV
VOUT 50mV/DIV
IOUT=3A
TIME 1µs/DIVTIME 1µs/DIV
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw8
Typical Operating Characteristics (Cont.)
1.245
1.247
1.249
1.251
1.253
1.255
-50 -25 025 50 75 100 125
1.098
1.100
1.102
1.104
1.106
1.108
1.110
1.112
1.114
1.116
1.118
-50 -25 025 50 75 100 125
VREF(V)
Temperature(°C)
VIN=3.3V
Temperature(°C)
VOUT(V)
VIN=3.3V
IOUT=0A
VREF vs. TemperatureOutput Voltage vs. Temperature
(Circuit of Figure2, VOUT=1.25V, for VIN=3.3V: L: 0.68µH, RTOFF=68kΩ; for VIN=5V: L=1µH, TOFF=100kΩ. TA=25oC if not
specially)
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw9
PIN
NO.
NAME TQFN 5x5-23
SSOP-16
FUNCTION
N.C 1,5,7,9,11,13,1
6,19,25,26,28,
30,32 X No Connection, Not internally connected.
IN 2,4 2,4
Supply Voltage Input for the internal PMOS Power Switch. Not internally connected.
Externally connect all pins for proper operation.
LX 3,21,22,27,29
3,14,16
Inductor Connection. Connection for the drains of the PMOS power switch and
NMOS synchronous-
rectifier switch. Connect the inductor from this node to the
output filter capacitor and load. Not internally connect
ed. Externally connect all pins
for proper operation.
SS 6 5 Soft-Start Connect a capacitor from SS to GND to limit inrush current during start-up.
EXTREF 8 6 External Reference Input Feedback input regulates to VEXTREF. The PWM
controller remains off until EXTREF is greater than REF.
TOFF 10 7 Off-Time Select Input. Sets the PMOS power switch constant-off-
time. Connect a
resistor from TOFF to GND to adjust the PMOS switch off-time.
FB 12 8 Feedback Input. Connect directly to output for fixed-voltage operation or to a
resistive-divider for adjustable operating modes.
GND 14,17,backsid
e pad, corner
tabs 9 Analog Ground. Connect exposed backside pad and corner tabs to analog GND.
REF 15 10 Reference Output. Bypass REF to GND with a 0.1µF capacitor.
GND 17 11 Tie to GND (pin 13 QFN; pin 9 SSOP)
VCC 18 12
Analog Supply Voltage Input. Supplies internal analog circuitry. Bypass VCC with a
10Ω and 1µF low-pass filter. See Figure2.
PGND 20,23,24 13,15 Power Ground. Internally connected to the internal NMOS synchronous-
rectifier
switch.
SHDN 31 1
Shutdown control Input Drive SHDN low to disable the reference, control circuitry,
and internal MOSFETs. Drive high or connect to VCC for normal operation.
Pin Description
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw10
Typical Application Circuit
FOR VIN =5V : L=1µH, RToff=100kΩ
FOR VIN=3.3V : L=0.68µH, RToff=68kΩ
LX
PGND
GND
FB
REF
SS
IN
VCC
SHDN
EXTREF
TOFF
APW7093 L
220µF
15mΩ
0.1µF
0.01µF
33µF
1µF
VEXTREF
RTOFF
10Ω
VIN VOUT
20KΩ
R2
1µF
CURRENT
SENSE
PWM
LOGIC
AND
DRIVERS
+
_
TIMERREF
SS FB
IN
EXTREF
REF
GND PGND
L
XL
APW7093
CIN
COUT
RTOFF
VIN VCC VIN
+3.0V TO +5.5V
SHDN
Block Diagram
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw11
Shutdown
Function Description
The APW7093 synchronous, current-mode, constant-off-
time, PWM DC-DC converter steps down input voltages
of 3V to 5.5V to an adjustable output voltage from 1.1V to
VIN, as set by the voltage applied at EXTREF. It sources
and sinks up 3A of output current. Internal switches com-
posed of a 90mW PMOS power switch and a 60mW NMOS
synchronous-rectifier switch improve efficiency, reduce
component count, and eliminate the need for an external
Schottky diode across the synchronous switch.
The APW7093 operates in a constant-off-time mode un-
der all loads. A single resistor-programmable constant-
tradeoffs in efficiency, switching noise, component size,
and cost. When power is drawn from a regulated supply,
constant-off-time PWM architecture essentially provides
constant-frequency operation. This architecture has the
inherent advantage of quick response to line and load
transients. The APW7093’s current-mode, constant-off-
time PWM architecture regulates the output voltage by
changing the PMOS switch on-time relative to the con-
stant-off-time.
Constant-Off-Time Operation
In the constant-off-time architecture, the FB voltage com-
parator turns the PMOS switch on at the end of each off-
time, keeping the device in continuous-conduction mode.
The PMOS switch remains on until the feedback voltage
exceeds the external reference voltage (VEXTREF) or the
positive current limit is reached. When the PMOS switch
turns off, it remains off for the programmed off-time (TOFF).
To control the current under short-circuit conditions, the
PMOS switch remains off for approximately 4xTOFF when
VFB<VEXTREF/4.
Synchronous Rectification
In a step-down regulator without synchronous rectification,
an external Schottky diode provides a path for current to
flow when the inductor is discharging. Replacing the
Schottky diode with a low-resistance NMOS synchronous
switch reduces conduction losses and improves
efficiency. The NMOS synchronous-rectifier switch turns
on following a short delay (typ. 20ns) after the PMOS power
switch turns off, thus preventing cross-conduction or
“shoot-through.” In constant-off-time mode, the synchro-
nous-rectifier switch turns off just prior to the PMOS power
switch turning on. While both switches are off, inductor
current flows through the internal body diode of the NMOS
switch.
Current Sourcing and Sinking
By operating in a constant-off-time and pseudo-fixed-fre-
quency mode, the APW7093 can both source and sink
current. Depending on the output current requirement,
the circuit operates in two modes. In the first mode, the
output draws current and the APW7093 behaves as a
regular buck controller, sourcing current to the output from
the input supply rail. However, when the output is sup-
plied by another source, the APW7093 operates in a sec-
ond mode as a synchronous boost, taking power from
the output and returning it to the input.
Thermal Resistance
Junction-to-ambient thermal resistance, θJA, is highly de-
pendent on the amount of copper area immediately sur-
rounding the IC leads. The APW7093 QFN package has 1
in square of copper area and a thermal resistance of
50°C/W with no forced airflow. The APW7093 16-pin SSOP
evaluation kit has 0.5 in square of copper area and a
thermal resistance of 80°C/W with no forced airflow. Air-
flow over the board significantly reduces the junction-to-
ambient thermal resistance. For heat sinking purposes,
it is essential to connect the exposed backside pad of the
TQFN package to a large analog ground plane.
Drive SHDN to a logic-level low to place the APW7093 in
low-power shutdown mode and reduce supply current
less than 1µA. In shutdown, all circuitry and internal
MOSFETs turn off, so the LX node becomes high
impedance. Drive SHDN to a logic-level high or connect
to VCC for normal operation.
Power Dissipation
Power dissipation in APW7093 is dominated by conduc-
tion losses in the two internal power switches. Power
dissipation due to charging and discharging the gate ca-
pacitance of the internal switches (i.e., switching losses)
is approximately:
SW
2
IND(CAP) fVCP××=
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw12
Function Description (Cont.)
Power Dissipation (Cont.)
where C = 500pF and fSW is the switching frequency.
Resistive losses in the two power switches are approxi-
mated by:
PMOS
2
OUTD(RES) RIP×=
where RPMOS is the on-resistance of the PMOS switch.
The junction-to-ambient thermal resistance required to
dissipate this amount of power is calculated by:
θJA = (TJ,MAX - TA,MAX) / (PD(CAP) + PD(RES))
where:
θJA = junction-to-ambient thermal resistance
TJ,MAX = maximum junction temperature
TA,MAX = maximum ambient temperature
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw13
Application Information
For typical applications, use the recommended compo-
nent values in Figure 2. For other applications, take the
following steps:
1.Select the desired PWM-mode switching frequency.
See Figure 3 for maximum operating frequency.
2. Select the constant-off-time as a function of input
voltage, output voltage, and switching frequency.
0
200
400
600
800
1000
1200
1400
2.8 3.3 3.8 4.3 4.8 5.3
Figure 3. Maximum Recommended Operation Frequency
3. Select RTOFF as the function of off-time.
4. Select the inductor as the function of output voltage,
off-time, and peak-to-peak inductor current.
Setting the Output Voltage
An external voltage applied to the EXTREF pin sets the
output voltage of the APW7093. This can come directly
from another voltage source or external reference. When
FB is directly tied to the output (Figure 4), the output volt-
age range is limited by the external reference’s input volt-
age limits. VEXTREF should be limited less than VIN-1.7V.
Failure to comply can cause the part to operate abnor-
mally and may cause part damage. Alternatively, the out-
put can be adjusted to VIN by connecting FB to a resistor-
divider between the output voltage and the ground (Figure
5). Use 20kΩ for R1. R2 is given by:
−⋅=1
VV
R1R2 EXTREF
OUT
APW7093
EXTREF FB
LX VOUT=VEXTREF
VEXTREF
1.7VVV1.1V INEXTREF −≤≤
Figure 4. Adjsting the Output Voltage using EXTREF
APW7093
EXTREF
FB
LX
R2
R1
VOUT
REF
where VEXTREF = VREF = 1.1V
−⋅=1
VV
1R2REXTREF
OUT
Figure 5. Adjsting the Output Voltage using FB
Programming the Switching Frequency and Off-Time
and On-Time
The APW7093 features a programmable PWM-mode
switching frequency, which is set by the input and output
voltage and the value of RTOFF, connected from TOFF to the
GND. RTOFF sets the PMOS power switch off-time in PWM
mode. Use the following equation to select the off-time
while sourcing current according to the desired switch-
ing frequency in PWM mode:
(
)
( )
NMOSPMOSINSW
PMOSOUTIN
OFF VVVfVVV
T+− −−
=
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw14
Application Information(Cont.)
where:
TOFF = the programmed off-time
VIN = the input voltage
VOUT = the output voltage
VPMOS = the voltage drop across the internal PMOS
power switch |IOUT X RPMOS|
VNMOS = the voltage drop across the internal NMOS
synchronous-rectifier switch |IOUT X RNMOS|
fSW = switching frequency
Make sure that TON and TOFF are greater than 400ns when
sourcing current. Select RTOFF according to the equation:
Recommended values for RTOFF range from 24kΩ to
410kΩ for off-times of 0.4µs to 4µs. Usually, the switch-
ing frequency is set as high as possible, and the inductor
value is reduced to minimize the energy transferred from
inductor to capacitor during load-step recovery.
However, as the output current increases, the voltage drop
across the NMOS and PMOS switches increases and the
voltage across the inductor decreases. This causes the
frequency to drop. Assuming RPMOS = RNMOS, the change in
frequency can be approximated with the following
equation:
s)/1.00(109ks)0.18(TROFFTOFF µΩ×µ−=
(
)
( )
NMOSPMOSINOFF
PMOSOUTIN
SW VVVTVVV
f+− −−
=
OFFIN
PMOSOUT
SW TVRI
f××∆−
=∆
Programming the Switching Frequency and Off-Time
and On-Time (Cont.)
The operating frequency of the APW7093 is determined
primarily by TOFF (set by RTOFF), VIN, and VOUT shown in the
following equation:
where RPMOS is the resistance of the internal MOSFETs
(70mΩ typ).
When sinking current, the switching frequency increases
due to the on-resistances of the internal switches adding
to the voltage across the inductor, reducing the on-time.
Calculate TON when sinking current using the equation:
+− −
=PMOSOUTIN
NMOSOUT
OFFON VVV VV
TT
Inductor Selection
The key inductor parameters must be specified: inductor
value (L) and peak current (IPEAK). A lower value of inductor
allows smaller size but results in higher losses and ripple.
A good compromise between size and losses is found at
approximately a 25% ripple current to load current ratio
(∆I/IOUT = 0.25).
0.25ITV
LOUT
OFFOUT ×
×
=
The peak inductor current at full load is calculated by:
L2 TV
II OFFOUT
OUTPEAK ×
×
+=
where IOUT is the maximum source or sink current.
Choose an inductor with a saturation current at least as
high as the peak inductor current. Additionally, verify the
peak inductor current while sourcing output current (IOUT =
ISOURCE) does not exceed the positive current limit. The
inductor selecting should exhibit low losses at the cho-
sen operating frequency.
Input Capacitor Selection
The input filter capacitor reduces peak currents and noise
at the voltage source. A 22µF to 47µF capacitor may be
required for higher power and dynamic loads. Low-ESR
and low-ESL Tantalum or ceramic capacitor should be
suitable.
Output Capacitor Selection
The output filter capacitor affects the output voltage ripple,
output load-transient response, and feedback loop
stability. The output filter capacitor must have low enough
ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy sta-
bility requirements. Also, the capacitance value must high
enough to guarantee stability and absorb the inductor
energy going from a full-load sourcing to full load sinking
condition without exceeding the maximum output
tolerance.
In applications where the output is subject to large load
transients, the output capacitor’s size typically depends
on how much ESR is needed to prevent the output from
dipping too low under a load transient.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw15
Application Information(Cont.)
Output Capacitor Selection (Cont.)
OUT(MAX)OUTESR I/VR∆∆≤
The actual microfarad capacitance value required is de-
fined by the physical size needed to achieve low ESR,
and by the chemistry of the capacitor technology. Thus,
the capacitor is usually selected by ESR, size and voltage
rating rather than by capacitance value. When using low-
capacity filter capacitors such as ceramic or polymer types,
capacitor size is usually determined by the capacity
needed to prevent overshoot and undershoot from caus-
ing problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising-load edge is no
longer a problem.
Soft-Start
Soft-start allows a gradual increase of the internal cur-
rent limit to reduce input surge currents at start-up and at
exit from shutdown. A timing capacitor, CSS, placed from
SS to GND sets the rate at which the internal current limit
is changed. Upon power-up, when the device comes out
of under-voltage lockout (2.6V typ.) or after the SHDN pin
is pulled high, a 4.7µA constant current source charges
the soft-start capacitor and the voltage on SS increases.
When the voltage on SS is less than approximately 0.7V,
the current limit is set to zero. As the voltage increases
from 0.7V to approximately VIN, the current limit is adjusted
from 0V to the current-limit threshold. The voltage across
the soft-start capacitor changes with time according to the
following equation:
SS
SS CtA4.7
V×µ
=
The output current limit during soft-start varies with the
voltage on the soft-start pin, SS, according to the follow-
ing equation:
1.8VV, I
1.1V
0.7V)(V
ISS
LIMIT
SS
LIIM(SS) ≤×
−
=
where ILIMIT is the current-limit threshold from the Electri-
cal Characteristics. The constant-current source stops
charging once the voltage across the soft-start capacitor
reaches 1.8V.
Figure 6. Soft-Start Current Limit
0
0
0
SHDN
VSS(A)
ILIMIT(A)
0.7V
1.8V
VIN
t
ILIMIT
Input Source
The output of the APW7093 can accept current due to the
reversible properties of the buck and the boost converter.
When voltage at the output of the APW7093 (low-voltage
port) exceeds or equals the output set voltage the flow of
energy reverses, going from the output to the input (high-
voltage port). If the input (high voltage port) is not con-
nected to a low-impedance source capable of absorbing
energy, the voltage at the input will rise. This voltage can
violate the absolute maximum voltage at the input of the
APW7093 and destroy the part. This occurs when sinking
current because the topology acts as a boost converter,
pumping energy from the low-voltage side (the output), to
the high-voltage side (the input). The input (high-voltage
side) voltage is limited only by the clamping effect of the
voltage source connected there. To avoid this problem,
make sure the input to the APW7093 is connected to a
low impedance, two quadrant supply or that the load
(excluding the APW7093) connected to that supply con-
sumes more power than the amount being transferred
from the APW7093 output to the input.
Current Limit and Short Circuit Protection
The APW7093 monitors sourcing and sinking current, and
limits the maximum output current to prevent damaging
during overload or short-circuit.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw16
Application Information(Cont.)
Circuit Layout and Grounding
Good layout is necessary to achieve the APW7093’s in-
tended output power level, high efficiency, and low noise.
Good layout includes the use of ground planes, careful
component placement, and correct routing of traces us-
ing appropriate trace widths. The following points are in
order of decreasing importance:
1. Minimize switched-current and high-current ground
loops. Connect the input capacitor’s ground, the
output capacitor’s ground, and PGND close together.
Split the ground connections. Use separate traces
or planes for the PGND and GND and tie them to-
gether at a single point.
2. The output capacitor should be placed close to the
output terminals to obtain better smoothing effect
on the output ripple.
3. Connect the input filter capacitor less than 5mm away
from IN. The connecting copper trace carries large
currents and must be at least 1mm wide, preferably
2.5mm.
4.Place the LX node components as close together and
as near to the device as possible. This reduces resis-
tive and switching losses as well as noise.
5.Ground planes are essential for optimum
performance. In most applications, the circuit is lo-
cated on a multilayer board and full use of the four or
more layers is recommended. For heat dissipation,
connect the exposed backside pad of the QFN pack-
age to a large analog ground plane, preferably on a
surface of the board that receives good airflow. If the
ground plane is located on the top layer, use the N.C.
pins adjacent to the GND to lower thermal resistance
to the ground plane. If the ground is located
elsewhere, use several vias to lower thermal
resistance. Typical applications use multiple ground
planes to minimize thermal resistance. Avoid large
AC currents through the analog ground plane.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw17
Package Information
SSOP-16
0
L
VIEW A
0.25
GAUGE PLANE
SEATING PLANE
A
A1E1
E
h X 45
c
SEE VIEW A
D
be
A2
S
Y
M
B
O
LMIN. MAX.
1.75
1.24
0.15 0.25
A
A2
c
D
E
e
L
h
MILLIMETERS
b0.20 0.30
SSOP-16
0.25 0.50
0.40 1.27
MIN. MAX.
INCHES
0.069
0.049
0.008 0.012
0.006 0.010
0.010 0.020
0.016 0.050
0
0.10A1 0.25 0.004 0.010
E1
0
°
0
°
8
°
8
°
4.80
5.80
3.80
0.635 BSC
5.00
6.20
4.00
0.189
0.228
0.150
0.025 BSC
0.197
0.244
0.157
Note : 1. Follow JEDEC MO-137 AB.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw18
Package Information
TQFN5x5-32
D
E
Note : Followed JEDEC MO-220 WHHD-4.
A
b
A1
A3
D2
E2
Pin 1
Corner
e
LK
0.020 BSC
0.20 0.008
K
4.90 5.10 0.193 0.201
4.90 5.10 0.193 0.201
S
Y
M
B
O
LMIN. MAX.
0.80
0.00
0.18 0.30
3.50 3.80
0.05
3.50
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A3 0.20 REF
TQFN5x5-32
0.35 0.45
3.80
0.008 REF
MIN. MAX.
INCHES
0.031
0.000
0.007 0.012
0.138 0.150
0.138
0.014 0.018
0.70
0.150
0.028
0.002
0.50 BSC
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw19
Carrier Tape & Reel Dimensions
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN.
12.4+2.00
-
0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.50±
0.10
P0 P1 P2 D0 D1 T A0 B0 K0
SSOP-16
4.00±
0.10
8.00±
0.10
2.00±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±
0.20
5.20±
0.20
2.10±
0.20
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN.
12.4+2.00
-
0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.5±
0.10
P0 P1 P2 D0 D1 T A0 B0 K0
TQFN5x5-32
4.0±
0.10
8.0±
0.10
2.0±
0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
5.30±
0.20
5.30±
0.20
1.30±
0.20
(mm)
Package Type Unit Quantity
SSOP-16 Tape & Reel 2500
TQFN5x5-32 Tape & Reel 2500
Devices Per Unit
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw20
Taping Direction Information
TQFN 5x5-32
SSOP-16
USER DIRECTION OF FEED
USER DIRECTION OF FEED
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw21
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B,A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA
Reflow Condition (IR/Convection or VPR Reflow)
t 25 C to Peak
tp
Ramp-up
tL
Ramp-down
ts
Preheat
Tsmax
Tsmin
TL
TP
25
Temperature
Time
Critical Zone
TL to TP
°
Reliability Test Program
Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
(TL to TP) 3°C/second max. 3°C/second max.
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
Time maintained above:
- Temperature (TL)
- Time (tL) 183°C
60-150 seconds 217°C
60-150 seconds
Peak/Classification Temperature (Tp)
See table 1 See table 2
Time within 5°C of actual
Peak Temperature (tp) 10-30 seconds 20-40 seconds
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Nov., 2008
APW7093
www.anpec.com.tw22
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Customer Service
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Classification Reflow Profiles (Cont.)
