PD - 91352B IRF530NS IRF530NL (R) HEXFET Power MOSFET l l l l l l Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Fully Avalanche Rated D VDSS = 100V RDS(on) = 90m G ID = 17A S Description Advanced HEXFET(R) Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low onresistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF530NL) is available for low-profile applications. D2Pak IRF530NS TO-262 IRF530NL Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TA = 25C PD @TC = 25C VGS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. Units 17 12 60 3.8 70 0.47 20 9.0 7.0 7.4 -55 to + 175 A W W W/C V A mJ V/ns C 300 (1.6mm from case ) Thermal Resistance Parameter RJC RJA www.irf.com Junction-to-Case Junction-to-Ambient (PCB Mounted,steady-state)** Typ. Max. Units --- --- 2.15 40 C/W 1 09/04/02 IRF530NS/IRF530NL Electrical Characteristics @ TJ = 25C (unless otherwise specified) RDS(on) VGS(th) gfs Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Min. 100 --- --- 2.0 12 --- --- --- --- --- --- --- --- --- --- --- Typ. --- 0.11 --- --- --- --- --- --- --- --- --- --- 9.2 22 35 25 IDSS Drain-to-Source Leakage Current LD Internal Drain Inductance --- 4.5 LS Internal Source Inductance --- 7.5 Ciss Coss Crss EAS Input Capacitance Output Capacitance Reverse Transfer Capacitance Single Pulse Avalanche Energy --- 920 --- 130 --- 19 --- 340 V(BR)DSS V(BR)DSS/TJ IGSS Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 90 m VGS = 10V, ID = 9.0A 4.0 V VDS = VGS, ID = 250A --- S VDS = 50V, ID = 9.0A 25 VDS = 100V, VGS = 0V A 250 VDS = 80V, VGS = 0V, TJ = 150C 100 VGS = 20V nA -100 VGS = -20V 37 ID = 9.0A 7.2 nC VDS = 80V 11 VGS = 10V, See Fig. 6 and 13 --- VDD = 50V --- ID = 9.0A ns --- RG = 12 --- VGS = 10V, See Fig. 10 Between lead, --- 6mm (0.25in.) nH G from package --- and center of die contact --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz, See Fig. 5 93 mJ IAS = 9.0A, L = 2.3mH D S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol 17 --- --- showing the A G integral reverse 60 --- --- S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 9.0A, VGS = 0V --- 93 140 ns TJ = 25C, I F = 9.0A --- 320 480 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11) Starting TJ = 25C, L = 2.3mH RG = 25, IAS = 9.0A, VGS=10V (See Figure 12) ISD 9.0A, di/dt 410A/s, VDD V(BR)DSS, TJ 175C Pulse width 400s; duty cycle 2%. 2 This is a typical value at device destruction and represents operation outside rated limits. This is a calculated value limited to TJ = 175C . Uses IRF530N data and test conditions. **When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994 www.irf.com IRF530NS/IRF530NL 100 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) TOP 4.5V 10 20s PULSE WIDTH TJ = 25 C 1 0.1 1 10 4.5V 10 1 0.1 100 Fig 1. Typical Output Characteristics RDS(on) , Drain-to-Source On Resistance (Normalized) I D , Drain-to-Source Current (A) 3.5 TJ = 25 C TJ = 175 C V DS = 50V 20s PULSE WIDTH 5.0 6.0 7.0 Fig 3. Typical Transfer Characteristics www.irf.com 10 100 Fig 2. Typical Output Characteristics 100 VGS , Gate-to-Source Voltage (V) 1 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) 10 4.0 20s PULSE WIDTH TJ = 175 C 8.0 ID = 15A 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 0 VGS = 10V 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature ( C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRF530NS/IRF530NL VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd C, Capacitance (pF) 1200 Ciss 800 Coss 400 Crss 0 1 10 20 VGS , Gate-to-Source Voltage (V) 1600 ID = 9.0A VDS = 80V VDS = 50V VDS = 20V 16 12 8 4 FOR TEST CIRCUIT SEE FIGURE 13 0 100 0 10 VDS , Drain-to-Source Voltage (V) 40 1000 100 OPERATION IN THIS AREA LIMITED BY R DS(on) ID, Drain-to-Source Current (A) ISD , Reverse Drain Current (A) 30 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage TJ = 175 C 10 1 TJ = 25 C 0.1 0.2 V GS = 0 V 0.4 0.6 0.8 1.0 1.2 VSD ,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 20 QG , Total Gate Charge (nC) 1.4 100 10 100sec 1msec 1 0.1 Tc = 25C Tj = 175C Single Pulse 1 10msec 10 100 1000 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF530NS/IRF530NL 20 VDS VGS ID , Drain Current (A) 16 D.U.T. RG 12 RD + -VDD V GS Pulse Width 1 s Duty Factor 0.1 % 8 Fig 10a. Switching Time Test Circuit 4 VDS 90% 0 25 50 75 100 125 150 175 TC , Case Temperature ( C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 0.10 0.05 0.1 0.02 0.01 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.01 0.00001 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 15V L VDS D.U.T RG IAS 20V VGS tp DRIVER + V - DD A 0.01 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS , Single Pulse Avalanche Energy (mJ) IRF530NS/IRF530NL 200 ID 3.7A 6.4A 9.0A TOP 160 BOTTOM 120 80 40 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature ( C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K QG 12V .2F .3F VGS QGS D.U.T. QGD + V - DS VGS VG 3mA IG Charge Fig 13a. Basic Gate Charge Waveform 6 ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRF530NS/IRF530NL Peak Diode Recovery dv/dt Test Circuit + D.U.T* Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + - - + RG * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test VGS * + - VDD Reverse Polarity of D.U.T for P-Channel Driver Gate Drive P.W. Period D= P.W. Period [VGS=10V ] *** D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode [VDD] Forward Drop Inductor Curent Ripple 5% [ISD ] *** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For N-channel HEXFET(R) power MOSFETs www.irf.com 7 IRF530NS/IRF530NL D2Pak Package Outline D2Pak Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN T HE AS SEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE 8 PART NUMBER F530S DAT E CODE YEAR 0 = 2000 WEEK 02 LINE L www.irf.com IRF530NS/IRF530NL TO-262 Package Outline IGBT 1- GATE 2- COLLECTOR 3- EMITTER 4- COLLECTOR TO-262 Part Marking Information EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 ASS EMBLED ON WW 19, 1997 IN THE ASS EMBLY LINE "C" INT ERNATIONAL RECTIFIER LOGO AS SEMBLY LOT CODE www.irf.com PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C 9 IRF530NS/IRF530NL D2Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) FEED DIRECTION 1.85 (.073) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) 11.60 (.457) 11.40 (.449) 1.65 (.065) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 4.72 (.136) 4.52 (.178) 16.10 (.634) 15.90 (.626) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 30.40 (1.197) MAX. 26.40 (1.039) 24.40 (.961) 3 4 Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.09/02 10 www.irf.com