HIP6005BCB - Intersil Corporation

110

TM HIP6005B

Buck Pulse-Width Modulator (PWM)

Controller and Output Voltage Monitor

The HIP6005B provides complete control and protection for

a DC-DC conver ter optimi zed for high-performance

micropro cessor appl ications. It is desi gned to drive an

N-Channel MOSFET in a standard buck t opology. The

HIP6005B integrates all of the control, output adjustment,

monitoring and prot ection functions into a singl e package.

The output voltage of the convert er i s easil y adjusted and

precisely regulated. The HIP6005B includes a fully

TTL-compatible 5-input digital-to-anal og converter (DAC)

that adjusts the output voltage from 1.3VDC to 2.05VDC in

0.05V i ncrem ents and from 2.1VDC to 3. 5VDC in 0. 1V steps.

The pr eci sion refer ence a nd v oltag e-mode regul ator hold the

selected output voltage to within ±1% over temperat ure and

li ne voltag e vari ati ons.

The HIP6005B provides simple, single feedback l oop, voltage-

mode control with fast transient response. It includes a 200kHz

free-running triangle-wave oscillator t hat is adjustable from

below 50kHz to over 1MHz. The error amplifier features a

15MHz gain-bandwidth product and 6V/µs slew rate which

enables high converter bandwidth for fast transient

performance. The resulting PWM duty ratio ranges from 0% to

100%.

The HIP6005B monitors the output voltage with a window

comparator that tracks the DAC output and issues a Power

Good signal when the out put is wit hin ±10%. The HI P6005B

protects against over- curren t and over-voltage condi tio ns by

inhibiting PWM operation. Additional built-in over-voltage

protection triggers an external SCR to crowbar the input

supply. The HIP6005B monitors the current by using the

rDS(ON) of th e upper MOSFET whi ch elimi nates t he need fo r

a current se nsing resistor.

Features

• Drives N-Channel MOSFET

• Operates from +5V or +12V Input

• Simple Si ngle-Lo op Control Desi gn

- Vol tage-M ode PWM Cont rol

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Fu ll 0% to 100 % D u ty Ratio

• Excellent Output Voltage Regulation

-±1% Over Line Volt age and Temperat ure

• TTL-Compatible 5-Bit Digital-to-Analog Output Voltage

Selection

- Wide Range . . . . . . . . . . . . . . . . . . . 1.3VDC to 3.5VDC

- 0.1V Binary Steps . . . . . . . . . . . . . . 2.1VDC to 3.5VDC

- 0.0 5 V Bin a ry S te ps . . . . . . . . . . . . 1.3 V DC to 2. 05 VDC

• Power-Good Output Volt age M onitor

• Over-Voltage and O ver-Current Fault Monitors

- Does Not Require Extra Current Sensing Element,

Uses MOSFET’s rDS(ON)

• Small Converter Si ze

- Consta nt Frequenc y Op eration

- 200kHz Free-Running Oscillator Programmable from

50kHz to over 1MHz

Applications

• Power Suppl y for Pentium®, Pent ium Pro, Pentium II,

PowerPC™, K6™, 6X86™ and Alpha™ Microprocessor s

•High-Power 5V to 3.xV DC-DC Regulators

•Low-Voltage Distributed Power Supplies

Pinout

HIP6005B

(SOIC, TSSOP)

TOP VIEW

6X86™ is a trademark of Cyrix Corporation.

Alpha Micro™ is a trademark of Digital Computer Equipment Corporation

K6™ is a trademark of Advanced Micro Devices.

Pentium® is a registered trademark of Intel Corporation.

PowerPC™ is a registered trademark of IBM.

Ordering Information

PART NUMBER TEMP.

RANGE (oC) PACKAGE PKG.

NO.

HIP6005BCB 0 to 70 20 Ld SOIC M20.3

HI P 60 05 B CV 0 to 70 20 Ld T SS OP M 20 .173

NOTE: When ordering, use the entire part number. Add the suffix T

to obtain the TSSOP variant in tape and reel, e.g., HIP6005BCV-T.

VSEN

OCSET

VID0

VID1

VID2

VID4

VID3

COMP

VCC

OVP

BOOT

UGATE

PHASE

PGOOD

GND

Data Sheet Februa ry 1999 FN4568. 2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-8 88-INTERSIL o r 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.

Typical Application

Block Diagram

+12V

+VOUT

HIP6005B

VSEN

COMP

PGOOD

GND

MONITOR AND

PROTECTION

OSC UGATE

OCSET

PHASE

BOOT

VCC VIN = +5V OR +12V

OVP

VID0

VID1

VID2

VID3 D/A

VID4

D/A

CONVERTER

(DAC)

OSCILLATOR

SOFT-

START

REFERENCE

POWER-ON

RESET (POR)

115%

110%

90%

INHIBIT

PWM

COMPARATOR

ERROR

AMP

VCC

PGOOD

PWM

OVP

RT GND

VSEN

OCSET

VID0

VID1

VID2

VID3

COMP

DACOUT

OVER-

VOLTAGE

OVER-

CURRENT

GATE

CONTROL

LOGIC

BOOT

UGATE

PHASE

200µA

10µA

VID4

HIP6005B

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V

Boot Voltage , VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . .+15V

Input, Output or I/O Voltage. . . . . . . . . . . .GND -0.3V to VCC +0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2

Ope rat i ng Condi tio ns

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

SOIC Package (with 3in2 of Copper). . . . . . . . . . . . 86

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC

(L ea d Tips Onl y)

CAUTIO N: S tresses abov e those l isted i n “ A bsolute Max imum Ra ting s” ma y cause per manen t dam age to th e de vice. This is a s tress on l y rating and ope ration of th e

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is me asured with the compon ent mou nted on a n evaluation PC board in free air.

Electrical Speci fications Recommended Operating Conditions, Unless Oth erwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC S UP PLY CURRENT

Nominal Supply ICC UGA TE Open - 5 - mA

POWER-ON RESET

Rising VCC Threshold VOCSET = 4.5V - - 10.4 V

F al lin g VCC Threshold VOCSET = 4.5V 8.2 - - V

Rising VOCSET Th res ho ld -1.26- V

OSCILLATOR

Free Running Frequency RT = Open 185 200 215 kHz

T ota l Vari atio n 6kΩ < RT to GND < 200kΩ-15 - +15 %

Ramp Amplitude ∆VOSC RT = Open - 1.9 - VP-P

REFERENCE AND DAC

DAC (VID0-VID4) Input Low Voltage --0.8V

DAC (VID0-VID4) Input High Voltage 2.0 - - V

DACOUT Voltage Accuracy -1.0 - +1.0 %

ERROR AMPLIFIER

DC Gain -88- dB

Ga in - Ban dw idt h Pr od uc t GBW - 15 - M H z

Slew Rate SR COMP = 10pF - 6 - V/µs

GATE DRIVER

Upper Gate So urce IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V 350 500 - mA

Upper Gate Si nk RUGATE -5.510 W

PROTECTION

Over-Voltage Trip (VSEN/DACOUT) -115120 %

OCSET Current Source IOCSET VOCSET = 4.5V 170 200 230 µA

OVP Sourcing Current IOVP VSEN = 5.5V; VOVP = 0V 60 - - mA

Soft Start Current ISS -10- µA

POWER GOOD

Upper Threshold (VSEN/DACOUT) VSEN Rising 106 - 111 %

Lower Threshold (VSEN/DACOUT) VSEN Falling 89 - 94 %

Hysteresis (VSEN/DAC OU T) Upp er and Lo w er T h res ho ld - 2 - %

PGOOD Voltage Low VPGOOD IPGOOD = -5mA - 0.5 - V

HIP6005B

Functional Pin Description

VSEN (Pin 1)

This pin is connected to the converter s output volt age. The

PGOOD and OVP comparator cir cui ts use this signal to

report output voltage status and for overvoltage prot ection.

OCSET (Pin 2)

Connect a resis tor (ROCSET) from this pin to the drain of the

upper MOSFET. ROCSET, an intern al 200µA current s ource

(IOCS), and the upper MOSFET on-r esistance (rDS(ON)) set

the converter over-current (OC) trip point accor ding to the

following equation:

An over-current trip cycles the soft-start functi on.

SS ( P in 3)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 10µA current source, sets the

soft-start interval of the converter.

VID0-4 (Pins 4-8)

VID0-4 are t he input pins to the 5- bit DAC. The states of

these five pins program the internal voltage reference

(DACOUT). The level of DACOUT sets t he converter output

volt age. It also sets the PGOOD and OVP thre sholds. Table

1 specifies DACOUT for the 32 combi nations of DAC inp uts.

COMP (Pin 9) and FB (Pin 10)

COMP and FB are t he available ext ernal pi ns of the error

amplifier. The FB pin is the inv erting input of the error

amplifier and the COMP pin is the error amplifier output .

These pins are used to compensate the volt age-cont rol

feedback loop of the conve rter.

GND (Pin 11)

Signal ground for the IC. All voltage levels are measu red

with respect to this pin.

PGOOD (Pin 12)

PGOOD is an open collector output used to indicate the

status of the converter output voltage. This pin is pull ed low

when the converter output is not within ±10% of t he

DACOUT refer ence voltage. Except ion to this behavi or is the

‘1111 1’ VID pin combi nati on which di sables t he convert er; in

this case PGOOD asserts a high level.

PHASE (Pin 13)

Connect the PHASE pin to the upper MOSFET sourc e. Thi s

pin is used to monitor the voltage drop across the MOSFET

for over-current protecti on. Thi s pin also provides the return

path for the upper gate driv e.

UGATE (Pin 14)

Connect UGATE to the upper MOSFET gat e. This pin

provides the gat e dri ve for the upper MOSFET.

Typical Perfo rman ce Cu rves

FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

10 100 1000

SWITCHING FREQUENCY (kHz)

RESISTANCE (kΩ)

100

1000 RT PULLUP

RT PULLDOWN TO VSS

TO +12V

100 200 300 400 500 600 700 800 900 1000

ICC (mA)

SWITCHING FREQUENCY (kHz)

CUGATE = 3300pF

CUGATE = 1000pF

CUGATE = 10pF

VSEN

OCSET

VID0

VID1

VID2

VID4

VID3

COMP

VCC

OVP

BOOT

UGATE

PHASE

PGOOD

GND

IPEAK IOCSET x ROCSET

rDS ON()

-----------------------------------------------------=

HIP6005B

BOOT (Pin 15)

This pin provi des bias voltage to the upper MOSFET driver.

A bootstrap cir cuit may be use d to cre ate a BOOT v oltag e

suitable to drive a standard N-Channel MOSFET.

NC (Pin 16)

No connection.

NC (Pin 17)

No connection.

VCC (Pin 18)

Provide a 12V bias supply for th e chip to this pin.

OVP (Pin 19)

The OVP pin can be used to drive an ext ernal SCR in the

event of an overvolta ge condition. Output rising 15% more

than the DAC-set voltage triggers a high output on this pi n

and disables PWM gate drive ci rcuitry.

RT (Pin 20)

This pin provides osc il lato r swi tching frequenc y adjustment.

By placi ng a resistor (RT) from this pin to GND, the nominal

200kHz switc hing frequency is increase d according to the

following equation:

Conversely, connecting a pull-up r esistor (RT) from th is pi n

to VCC reduces the switchi ng freq uency according to th e

following equation:

Functional Description

Initialization

The HIP6005B automatically initializes upon receipt of power.

Special sequencing of the i nput suppl ies i s not necessary. The

Power-On Reset (POR) func tion continually m onitors the i nput

supply vol tages. The POR monitors the bi as voltage at t he VCC

pin and the input voltage (VIN) on the OCSET pin. The level on

OCSET is equal to VIN less a fi xed volt age drop (see over-

current protection). The POR function ini tiates soft start

operation after both input supply voltages exceed their POR

thresholds. For operation with a single +12V power source, VIN

and VCC are equivalent and the +12V power source must

exceed the rising VCC t hreshold before POR initiat es oper ation.

Soft St a rt

The POR function initiates the soft start sequence. An internal

10µA current source char ges an external capacitor (CSS) on

the SS pin to 4V. Soft start clamps the error amplifier output

(COMP pin) and reference input (+ terminal of error amp) to

the SS pin voltage. Figure 3 shows the soft start interval with

CSS = 0.1µF. Initially the clamp on the error amplifier (COMP

pin) control s the converter’s output voltage. At t1 in Figure 3,

the SS voltage reaches the valley of the oscillator’s triangle

wave. The oscillator’s triangular waveform is compared to the

ramping error amplifier voltage. This generates PHASE

pulses of increasing width that charge the output capacitor(s).

This interval of i ncreasing pulse wi dth continue s to t2. With

sufficient output voltage, the clamp on the reference input

con t rol s th e o utp ut vo l tag e. Th i s is th e i n ter val bet we en t2 and

t3 in Figure 3. At t3 the SS voltage exceeds the DACOUT

voltage and the output voltage is in regulation. This method

provides a rapid and controlled output volt age rise. The

PGOOD signal toggles ‘ high’ when the output volt age (VSEN

pin) is within ±5% of DACOUT. The 2% hy steresi s buil t i nto

th e pow er good comparator s pre vents P GOOD osc illation due

to nominal output voltage ripple.

Ove r- Current Protect i on

The over-current function protects the conver ter from a

shorted output by using the upper MO SFET’s on-res istance,

rDS(ON) to monitor the current. This method enhances the

converte r’s efficiency and reduc es cost by eliminating a

current sensing resistor.

Fs 200kHz 5 x 106

RTkΩ()

---------------------+≈(RT to GN D )

Fs 200kHz 4 x 107

RTkΩ()

---------------------–≈(RT to 12 V)

TIME (5ms/DIV.)

SOFT-START

(1V/DIV.)

OUTPUT

(1V/DIV.)

VOLTAGE

t2t3

PGOOD

(2V/DIV.)

FIGURE 3. SOFT START INTERVAL

OUTPUT INDUCTOR SOFT-START

TIME (20ms/DIV.)

10A

15A

FIGURE 4. OVER-CURRENT OPERATION

HIP6005B

The over-current function cycles the soft-start function in a

hiccup mode to provide fault protection. A resistor (ROCSET)

programs the over-current trip level. An internal 200µA current

sink develops a voltage across ROCSET that is referenced to

VIN. When the voltage across the upper MOSFET (also

referenced to VIN) exceeds the voltage across ROCSET, the

over-current function initiates a soft-start sequence. The soft-

start function discharges CSS with a 10µA current sink and

inhibits PWM operation. The soft-start function recharges

CSS, and PWM operation resumes with the error amplifier

clamped to the SS voltage. Should an overload occur while

recharging CSS, the soft start function inhibits PWM operation

while fully charging CSS to 4V to complete its cycle. Figure 4

sho ws t his op era ti on wit h an over lo ad co ndi t io n. No t e tha t th e

inductor current increases to over 15A during the CSS

charging interval and causes an over-current trip. The

converter dissipates very little power with this method. The

measured input power for the conditions of Figure 4 is 2.5W.

The over-current function wil l trip at a peak inductor current

(IPEAK) determi ned by:

where IOCSET is the int ernal O C SET curren t source (200µA

typi cal). The OC trip point varies mainly due to the

MOSFET’s rDS(ON) vari ation s. To avoid over-cur rent

tri pping i n the normal operating l oad r ange, find t he ROCSET

resistor from the equation above with:

1. The maximum rDS(ON) at the highest junction temperature.

2. The mini m um IOCSET from the specification table.

3. Det ermine IPEAK for ,

where ∆I is the output inductor ripple cu rrent.

For an equation for the ripp le current see the section under

com ponent gui delines ti tl ed “Output Inductor Select ion.”

A small cer am ic capacitor should be placed in parallel with

ROCSET to smoot h the voltage across ROCSET in the

presence of switchi ng noise on the input volta ge.

Out put Volt age P rogram

The out put voltage of a HIP6005B converter is pr ogrammed

to disc ret e levels between 1.8VDC and 3.5VDC. The voltage

identifi cation (VID) pins progra m an internal voltage

reference (DACOUT) with a TTL-compat ible, 5- bit

digi tal-to -analog converter (DAC) . The level of DACOUT

also set s the PGOOD and OVP t hreshol ds. Ta ble 1 s peci fie s

the DACOUT volt age for the 32 dif ferent combinations of

connections on the VID pins. The output voltage should not

be adjus ted while the converter is deliver ing power. Remove

input power befor e changing the output volt age. Adjusting

the ou tpu t voltage dur ing oper ation could t oggle t he PGOOD

signal and exercise the overvoltage protection.

‘11111’ VID pin combination resulting in a 0V output setting

activates the Power-On Reset function and disables the gate

drive circuitry. For this specific VID combination, though,

PGOOD as ser ts a hi gh l eve l. Thi s unu sua l be hav ior has b een

implemented in order to allow for operation in

dual-microprocessor systems where AND-ing of the PGOOD

signals from two individual power converters is implemented.

Application Guidelines

Lay out C on s i derations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to another

can generate voltage transients across the impedances of the

interconnecting bond wires and circuit traces. These

interconnecting impedances should be minimized by usi ng

wide, short printed circuit traces. The critical component s

should be located as close together as possible using ground

plane construction or single point grounding.

IPEAK IOCSET x ROCSET

rDS ON()

-----------------------------------------------------=

IPEAK IOUT MAX()

∆I()2⁄+>

TABLE 1. OUTPUT VOLTAGE PROGRAM

PIN NAME NOMI NAL OUTP UT

VOLTAGE DACOUT PIN NAME NOMI NAL OUTPUT

VOLTAGE DACOUTVID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0

01111 1.30 11111 0

01110 1.35 11110 2.1

01101 1.40 11101 2.2

01100 1.45 11100 2.3

01011 1.50 11011 2.4

01010 1.55 11010 2.5

01001 1.60 11001 2.6

01000 1.65 11000 2.7

00111 1.70 10111 2.8

00110 1.75 10110 2.9

00101 1.80 10101 3.0

00100 1.85 10100 3.1

00011 1.90 10011 3.2

00010 1.95 10010 3.3

00001 2.00 10001 3.4

00000 2.05 10000 3.5

NOTE: 0 = connected to GND or VSS, 1 = connected to VDD thro ugh pul l-u p resistors.

HIP6005B

Figure 5 shows the critical power components of the converter.

To minimize the voltage overshoot the interconnecting wires

indicated by heavy lines should be part of ground or power

plane in a print ed cir cuit board. The components shown in

Figure 6 should be locat ed as close together as possible.

Please note that the capaci tors CIN and CO each represent

numerous physical capacitors. Locate the HIP6005B within 3

inches of the M OSFET, Q1. The ci rcuit traces for the

MOSFET’s gate and source connections from the HIP6005B

must be sized to handle up to 1A peak current.

Figure 6 shows the cir cuit traces that r equire add it ional

layout con siderati on. Use single point and ground plane

construction for the ci rcuits shown. Minimize any leakage

current pat hs on the SS PIN and l ocate the capacitor, Css

close to the SS pin because the int ernal current sou rce is

only 10µA. Provide local VCC decoupling between VCC and

GND pins. Locate the capacitor, CBOOT as close as

practical to the BOOT and PHASE pins.

Feedback Compensation

Figure 7 highl ights t he voltage-mode control loop for a buck

convert er. The output voltage (VOUT) is r egulated to the

Reference vo lt age level. The error amplifi er (Error Amp)

output (VE/A) is com pared with the oscillator (OS C)

tri angula r wave to provide a pul se-width modulat ed (PWM )

wave w i th an ampli t ude of VIN at the PHASE node. The

PWM wave is smoothed by the output filter (LO and CO).

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This funct ion is dominated by a DC

Gain and the output fi lter (LO and CO), with a double pol e

break frequency at FLC and a zero at FESR. The DC Gain of

the modul at or is simpl y the in put v oltag e (VIN) di vided by t he

peak-t o-peak oscillator voltage ∆VOSC.

Modula tor Break Fr equ ency Equations

The compensation network consists of the error amplif ier

(internal to the HIP6005B) and the impedance networks ZIN

and ZFB. The goal of the compensation network is to provide a

closed loop transfer functi on with the hi ghest 0dB crossi ng

frequency (f0dB) and adequate phase margin. Phase margin is

the difference between the closed l oop phase at f0dB and 180

degrees. The equations below relate the compensation

network’s poles, zeros and gain t o the components (R1, R2,

R3, C1, C2, and C3) in Figure 8. Use these gui delines for

locating the poles and zeros of the compensation network:

1. Pi ck Gain ( R2/R1) for desired converter bandwidth.

2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).

3. Pl ace 2ND Zero at Filter’ s Double Pole.

4. Pl ace 1ST Pole at the ESR Zero.

5. Pl ace 2ND Pole at Half the Switching Frequency.

6. Check Gain against Error Amplifier’s Open- Loop Gain.

7. Estim ate Phase Marg in - Repeat if Neces sary.

UGATE

PHASE

VIN

VOUT

RETURN

HIP6005B

CIN

LOAD

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND

PLANES O R ISLAN DS

HIP6005B

GND

VCC

BOOT D1LO

VOUT

LOAD

PHASE

FIGURE 6. PRINTED CIRCUIT BOARD SMALL S IGNAL

LA YOUT G UIDEL IN ES

+VIN

CBOOT

CVCC

CSS

+12V

VOUT

OSC

REFERENCE

ESR

VIN

∆VOSC

ERROR

AMP

PWM DRIVER

(PARASITIC)

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

ZIN

ZFB

DACOUT

R2C3

COMP

VOUT

ZFB

HIP6005B

ZIN

COMPARATOR

DETAILED COMPENSATION COMPONENTS

VE/A

-PHASE

FESR 1

2π x (ESR x CO)

------------------------------------------------=

FLC 1

2π x L O x C O

------------------------------------------=

HIP6005B

Compensa tion Break Fr equency Equ ations

Figure 8 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak due to the high Q factor of the output filter and is not

shown in Figure 8. Using the above guidelines should give a

Compensation Gain similar to the curve plotted. The open

loop error am plif ier gain bounds the co m pensation g ain.

Check the compensation gain at FP2 wi th the capa bilitie s of

the error amplifier. The Closed Loop Gai n is construc ted on

th e l og- lo g g r aph o f Fig ure 8 b y a dd ing the Mo du lat o r Gai n (i n

dB) to the Compensati on Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

com pensation transfer f unction and plotting the gain.

The com pensation gain uses external impedance networks

ZFB and ZIN to p rovide a stabl e, high ban dwidth (BW)

overal l loop. A stable control loop has a gain crossing with

-20dB/dec ade slope and a phase margin greater than 45

degrees. Include wor st case component variations when

determining phase margin.

Component Selectio n Guidelines

Output Cap acitor Selection

An output capacitor is required t o filter the output and sup ply

the l oad transient cur rent. The filtering requirements are a

function of t he switching frequency and the ripple current.

The load transient requiremen ts are a functi on of the slew

rate (di/ dt) and the magnitude of the transient load cur rent.

These requirements are generally met wi th a mix of

capacitors and careful layout.

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (Effective Series Resistance) and voltage rating

requirements rather than actual capacitance requirements.

High fr equency decoupling capacit ors should be placed as

clos e to the po wer pins o f t he load as p hysical ly pos si ble. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

comp onents. Co nsult with the ma nufacturer of the load on

specif ic decoupling requirements. For example, Intel

recommends that the high frequency decoupling for the

Pentium Pro be co mp osed of at least fort y (40) 1µF ceramic

capacitors in the 1206 surface-mount package.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor's ESR value is related to the

case size wi th lower ESR available in larger ca se sizes.

H owever, the Equ iva len t Series Inductance (ESL ) of these

capacitors increases with case size and can reduce the

use f ul ne ss of t he c a pa cit or t o h i gh sl ew -r ate t ran s ien t lo ad ing .

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

Out put Induct or S el ec tio n

The output inductor is sel ected to meet the out put voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determi nes th e

converte r’s rippl e curre nt and the ripple vo lt age is a fun cti on

of the r ipple current. The ri pple voltage and cur rent are

approximated by the following equations:

Incr easing the value of induc tan ce reduce s the r ipp le cur rent

and volt age. However, the large i nductan ce values re duce

the converter’s response tim e to a lo ad transient.

FZ2 1

2π x (R1R3

+) x C3

-------------------------------------------------------=

FP1 1

2π x R2 x C1 x C2

C1 + C2

----------------------







---------------------------------------------------------=

FP2 1

2π x R3 x C3

------------------------------------=

FZ1 1

2π x R2 x C 1

------------------------------------=

100

-20

-40

-60

FP1

FZ2

10M1M100K10K1K10010

OPEN LOOP

ERROR AMP GAIN

FZ1 FP2

FLC FESR

COMPENSATION

GAIN (dB)

FREQUENCY (Hz)

GAIN

20LOG

(VIN/∆VOSC)

MODULATOR

GAIN

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

20LOG

(R2/R1)

CLOSED LOOP

GAIN

∆IVIN VOUT

–

FS x L

-------------------------------- x VOUT

VIN

----------------= ∆VOUT ∆I x ESR=

HIP6005B

One of the parameters limiting the converter’s response to

a load transi ent is the ti me requ ired to change the i nductor

current. Gi ven a suffi ciently fast cont rol loop design, the

HIP6 005B w ill provi de eith er 0% or 100% dut y cycle i n

response to a load transient. The response time is the time

required t o slew the i nductor cur rent f rom an ini tial current

value to the tran sient curre nt level. Duri ng thi s inte rval the

differen ce between the induct or cur rent and t he tr ansient

current le vel must be supp lied by the ou tput capacit or.

Minimizing t he respo nse t ime can m inimi ze the out put

capacitance required.

The response tim e to a transient is different for the

appli cation of load and the removal of load . The fo ll owing

equation s give the approxi m ate resp onse time interval for

appli cation and removal of a tr ansient load:

w here: ITRAN is the transient load current step, tRISE is the

respons e time to the appl ication of l oad, and t FALL is the

respons e tim e to the removal of lo ad. Wit h a +5V input

source, the worst case res ponse ti me ca n be eith er at the

applicat ion or re mova l of load and dependent upon the

DACOUT setting. Be sure to check both of these equations

at the minimum and m axi mum out put l evels fo r the worst

case response time. With a +12V input, and output voltage

level equal to DACOUT, tFALL is the longest response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic capacitors

for high frequency decoupling and bulk capacitors to supply the

current needed each time Q1 turns on. Place the small ceramic

capacitors physically close to the MOSFETs and between the

drain of Q1 and the anode of Schottky diode D2.

The imp ortant parame ters for the bulk i nput capac itor ar e

the voltage r atin g and the RM S cur rent r atin g. For reliable

operation, select the bulk capaci tor wit h voltage and

current rat ings above t he m aximum input volta ge and

largest RM S cur rent re quir ed by the ci rcuit. The ca paci tor

voltage rating shoul d be at least 1.25 times greater than the

maximum input vo ltage and a voltage r ating of 1.5 time s is

a conserva tive gu ideline. The RMS curr ent rating

requireme nt for the input capacitor of a buck regu lator i s

appr oximatel y 1/2 t he DC load c urrent .

For a through hole design, several electr olytic capacitors

(Panasonic HFQ series or Nichicon PL seri es or Sanyo MV-GX

or equivalent) may be needed. For surface mount designs,

solid t antalum capacitors can be used, but caution must be

exercised with regard to the capacitor surge current rat ing.

These capacitors must be capable of handling the surge-

current at power-up. The TPS series available from AVX, and

the 593D series from Sprague are both surge cur rent t ested.

MOSFET Selectio n/Considerations

The HIP6005B requires an N-Channel power MOSFET. I t

should be selected based upon rDS(ON), gat e supp l y

requireme nts, and thermal management requirement s.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissi pation includes two loss components;

conduction loss and switching loss. The conduction losses are

the largest component of power dissipat ion for the MOSFET.

Switching losses also contribut e to t he overall M OSFET power

loss (see the equations below). These equations assume linear

voltage-current transitions and are approximations. The gate-

charge losses are dissipated by the HIP6005B and do not heat

the MOSFET. However, lar ge gate-charge increases the

switching interval, tSW, which increases the upper MOSFET

switching losses. Ensure that the MOSFET is within its

maximum junction temperature at high ambient temperature by

calculating the t emperature rise accordi ng to package t hermal-

resistance specific ations. A separate heatsink may be

necessary depending upon MOSFET power, package type,

ambient temperature and air flow.

Wher e: D is the duty cycle = VOUT/VIN,

tSW is the swi tching int erval , and

FS is the switching frequen cy

Standar d-gate MOSFETs are normally recommended for

use wi th t he HIP6005B. However , lo gic-l evel gate MO SFETs

can be used und er speci al c ir cumstanc es. The i nput vol tage,

upper gate drive level, and the MOSFETs abso lute

gate-to-sour ce voltage rating determine whether logic-level

MOSFETs ar e appropriate.

Figure 9 shows the upper gate drive (BOOT pin) supplied by

a bootstrap circuit from VCC. The boot capacitor, CBOOT,

develops a f loating supply voltage referenced to the PHASE

pin. This supply is refreshed each cycle to a volt age of VCC

less the boot diode dr op (VD) when the Schottky diode, D2,

conducts. Logic- level MOSFETs can only be used if the

MOSFETs absolute gat e-to-source volt age rating exceeds

the maximum voltage applied to VCC.

Figure 10 shows the upper gate dr ive supplied by a direct

connection to VCC. This option should only be used in

converter systems where the main input volt age is +5VDC or

less. The peak upper gate-t o-source voltage i s approximately

VCC less the input supply. For +5V main power and +12VDC

for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level

MOSFET is a good choice for Q1 under these conditions.

tRISE L x ITRAN

VIN VOUT

–

--------------------------------= tFALL L x I TRAN

VOUT

----------------------------=

PCOND = IO2 x rDS(ON) x D

PSW = 1/2 IO x VIN x tSW x FS

HIP6005B

Sch ottky Se le c tion

Rectifier D2 conducts when the upper MOSFET Q1 is o ff. The

diode should be a Schottky t ype for low power l osses. The

power dissipation in the Schottky rectifier is approxi mated by:

In addition to power dis sipation, package selection an d

heat-sink requirements are the main design tradeoffs in

choosing the schottky rectifier. Since the three factors are

interr elated, the s election process is an ite rat iv e procedure.

The maximum junction temperature of the rectifier must

remain below the manufacturer’s specified value, typically

125oC. By using the package thermal resistance specification

and the schottky power dissipation equation (shown above),

the junction temperature of the rectifier can be estimated. Be

sure to use the available airflow and ambient temperature to

determine the junction temperature rise.

+12V

HIP6005B

GND

UGATE

PHASE

BOOT

VCC

+5V OR +12

NOTE: VG-S ≈ VCC - VD.

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

(NOTE)

CBOOT

DBOOT

+ VD -

+12V

HIP6005B

GND

UGATE

PHASE

BOOT

VCC

+5V OR LESS

FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION

NOTE:

VG-S ≈ VCC -5V

PCOND = I0 x Vf x (1 - D)

Wher e: D is the duty cycle = VOUT / VIN, and

Vf is the Schottky forwa rd voltage drop.

HIP6005B

120

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Intersil Corpora ti on’s quality cert if ications can be viewed at www.intersil. com/design/quali ty

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lic ense is granted by implication or otherwise under any patent or patent ri ghts of Intersil or its subsidiaries.

For information regar ding Intersil Cor poration and its products, see www.intersil .com

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NO R TH A MER ICA

Intersil Corporation

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HIP6005B DC-DC Converter Application Circuit

Figur e 11 shows an appl ication c ircui t of a DC- DC Convert er

for an Intel Pentium Pro microprocessor. Detailed

information on the circuit, including a complete Bil l-o f-

Materials and circuit board description , can be f ound in

application note AN9706. Although the Application Note

details t he HIP6005, the sam e evaluation platform can be

used to evaluate the HIP6005B..

+12V

+VO

HIP6005B

VSEN

COMP

VID0

VID1

VID2

VID3

OVP

SS PGOOD

D/A

GND

MONITOR

OSC

VCC

L1 - 1µH

CIN

COUT

0.1µF

2x 1µF

0.1µF

2.2nF

8.2nF 20K

7µH

5x 1000µF

9x 1000µF

0.082µF

UGATE

OCSET

PHASE

BOOT

2N6394

1.1K

1000pF

VIN = +5V

+12V

AND

PROTECTION

Component Selection Notes

COUT - Each 1000µF 6.3WVDC, Sanyo MV-GX or Equivalent.

CIN - Each 330µF 25WV DC, Sanyo MV-GX or Equivalent.

L2 - Core: Micrometals T60-52; Each Winding: 14 Turns of 17AWG.

L1 - Cor e: Micrometals T50-52; Winding: 6 Turns of 18AWG.

D1 - 1N4148 or E quivalent.

D2 - 25A, 35V Schottky, Motorola MBR2535CTL or Equivalent.

Q1 - Intersil MOSFET; RFP70N03.

FIGURE 11. PENTIUM PRO DC-DC CONVERTER

VID4 8

HIP6005B