14-Bit, 250 kSPS PulSAR,
Pseudo Differential ADC in MSOP/LFCSP
Data Sheet AD7942
Rev. C Document Feedback
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FEATURES
14-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR)
SINAD: 85 dB at 20 kHz
THD: −100 dB at 20 kHz
Pseudo differential analog input range
0 V to VREF with VREF up to VDD
No pipeline delay
Single-supply 2.3 V to 5.5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Proprietary serial interface
SPI-/QSPI-/MICROWIRE-/DSP-compatible1
Daisy-chaining for multiple ADCs and busy indicator
Power dissipation
1.25 mW at 2.5 V/100 kSPS, 3.6 mW at 5 V/100 kSPS
1.25 μW at 2.5 V/100 SPS
Standby current: 1 nA
10-lead package: MSOP and 3 mm × 3 mm LFCSP
Pin-for-pin compatible with the 16-bit AD7685
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process controls
APPLICATION DIAGRAM
AD7942
REF
GND
VDD
IN+
IN–
VIO
SDI
SCK
SDO
CNV
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
0.5
V
TO 5V 2.5
V
TO 5V
0
V
TO VREF
04657-001
Figure 1.
GENERAL DESCRIPTION
The AD7942 is a 14-bit, charge redistribution, successive approxi-
mation PulSAR® ADC that operates from a single power supply,
VDD, between 2.3 V to 5.5 V. It contains a low power, high
speed, 14-bit sampling ADC with no missing codes, an internal
conversion clock, and a versatile serial interface port. The part
also contains a low noise, wide bandwidth, short aperture delay
track-and-hold circuit. On the CNV rising edge, it samples an
analog input, IN+, between 0 V to VREF with respect to a ground
sense, IN−. e reference voltage, VREF, is applied externally and
is set up to be the supply voltage. Its power scales linearly with
the throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is com-
patible with 1.8 V, 2.5 V, 3 V, or 5 V logic using a separate
supply (VIO).
The AD7942 is housed in a 10-lead MSOP or a 10-lead LFCSP
package yet fits in the same size footprint as the 8-lead MSOP
or SOT-23. Operation for the AD7942 is specified from −40°C
to +85°C.
1 Protected by U.S. Patent 6,703,961.
Table 1. MSOP, LFCSP/SOT-23, 14-/16-/18-Bit ADCs
Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver
14-Bit AD7940 AD79421 AD79461
16-Bit AD7680 AD76851 AD76861 AD79801 ADA4941-x
AD7683 AD76871 AD76881 AD79831 ADA4841-x
AD7684 AD7694 AD76931
18-Bit AD76911 AD76901 AD79821 ADA4941-x
AD79841 ADA4841-x
1 Pin-for-pin compatible to the AD7942.
AD7942 Data Sheet
Rev. C | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Application Diagram ........................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Circuit Information .................................................................... 13
Converter Operation .................................................................. 13
Typical Connection Diagram ................................................... 14
Digital Interface .......................................................................... 16
Application Hints ........................................................................... 23
Layout .......................................................................................... 23
Evaluating the Performance of AD7942 .................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
6/14—Rev. B to Rev. C
Changed QFN (LFCSP) Notation to LFCSP .............. Throughout
Added Patent Footnote .................................................................... 1
Changes to Evaluating the Performance of the AD7942 ........... 23
Changes to Ordering Guide .......................................................... 24
6/08—Rev. A to Rev. B
Changes to Features Section and General Description Section . 1
Moved Figure 2 and Figure 3 .......................................................... 6
Changes to Table 6 ............................................................................ 8
Moved Terminology Section ......................................................... 12
Changes to Figure 41 ...................................................................... 22
Changes to Ordering Guide .......................................................... 24
12/07—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................. 1
Changes to General Description Section ....................................... 1
Changes to Table 6 ............................................................................. 7
Changes to Table 7 ............................................................................. 8
Changes to Circuit Information Section ..................................... 13
Changes to Table 9 .......................................................................... 15
Changes to Figure 39 ...................................................................... 21
Changes to Figure 41 ...................................................................... 22
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
3/05—Revision 0: Initial Version
Data Sheet AD7942
Rev. C | Page 3 of 24
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 14 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 VREF V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 V
IN− −0.1 +0.1 V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current TA = 25°C, acquisition phase 1 nA
Input Impedance See the Analog Input section
ACCURACY
No Missing Codes 14 Bits
Differential Linearity Error −0.7 ±0.3 +0.7 LSB1
Integral Linearity Error −1 ±0.4 +1 LSB
Transition Noise VREF = VDD = 5 V 0.33 LSB
Gain Error2, TMIN to TMAX ±0.7 ±6 LSB
Gain Error Temperature Drift ±1 ppm/°C
Offset Error2, TMIN to TMAX VDD = 4.5 V to 5.5 V ±0.45 ±3 mV
VDD = 2.3 V to 4.5 V ±0.75 ±4.5 mV
Offset Temperature Drift ±2.5 ppm/°C
Power Supply Sensitivity VDD = 5 V ± 5% ±0.1 LSB
THROUGHPUT
Conversion Rate VDD = 4.5 V to 5.5 V 0 250 kSPS
VDD = 2.3 V to 4.5 V 0 200 kSPS
Transient Response Full-scale step 1.8 μs
AC ACCURACY
Signal-to-Noise Ratio (SNR) fIN = 20 kHz, VREF = 5 V 84.5 85 dB3
f
IN = 20 kHz, VREF = 2.5 V 84 dB
Spurious-Free Dynamic Range (SFDR) fIN = 20 kHz −100 dB
Total Harmonic Distortion (THD) fIN = 20 kHz −100 dB
Signal-to-Noise and Distortion Ratio (SINAD) fIN = 20 kHz, VREF = 5 V 83 85 dB
f
IN = 20 kHz, VREF = 5 V, −60 dB input 25 dB
f
IN = 20 kHz, VREF = 2.5 V 84 dB
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 250 kSPS, VREF = 5 V 50 μA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 2 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 μA
IIH −1 +1 μA
AD7942 Data Sheet
Rev. C | Page 4 of 24
Parameter Conditions Min Typ Max Unit
DIGITAL OUTPUTS
Data Format Serial 14 bits straight binary
Pipeline Delay Conversion results available
immediately after
completed conversion
VOL I
SINK = +500 μA 0.4 V
VOH I
SOURCE = −500 μA VIO − 0.3 V
POWER SUPPLIES
VDD Specified performance 2.3 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current4, 5 VDD and VIO = 5 V, at 25°C 1 50 nA
Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.25 μW
VDD = 2.5 V, 100 kSPS throughput 1.25 2 mW
VDD = 2.5 V, 200 kSPS throughput 2.5 4 mW
VDD = 5 V, 100 kSPS throughput 3.6 5 mW
VDD = 5 V, 250 kSPS throughput 12.5 mW
TEMPERATURE RANGE6
Specified Performance TMIN to TMAX −40 +85 °C
1 LSB means least significant bit. With a 5 V input range, 1 LSB = 305.2 μV.
2 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3 All specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4 With all digital inputs forced to VIO or GND as required.
5 During acquisition phase.
6 Contact Analog Devices, Inc., sales for an extended temperature range.
Data Sheet AD7942
Rev. C | Page 5 of 24
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V1, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 3.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Available Data tCONV 0.5 2.2 μs
Acquisition Time tACQ 1.8 μs
Time Between Conversions tCYC 4 μs
CNV Pulse Width (CS Mode) tCNVH 10 ns
SCK Period (CS Mode) tSCK 15 ns
SCK Period (Chain Mode) tSCK
VIO ≥ 4.5 V 17 ns
VIO ≥ 3 V 18 ns
VIO ≥ 2.7 V 19 ns
VIO ≥ 2.3 V 20 ns
SCK Low Time tSCKL 7 ns
SCK High Time tSCKH 7 ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data-Valid Delay tDSDO
VIO ≥ 4.5 V 14 ns
VIO ≥ 3 V 15 ns
VIO ≥ 2.7 V 16 ns
VIO ≥ 2.3 V 17 ns
CNV or SDI Low to SDO D13 MSB Valid (CS Mode) tEN
VIO ≥ 4.5 V 15 ns
VIO ≥ 2.7 V 18 ns
VIO ≥ 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 3 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns
SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI
VIO ≥ 4.5 V 15 ns
VIO ≥ 2.3 V 26 ns
1 See Figure 2 and Figure 3 for load conditions.
AD7942 Data Sheet
Rev. C | Page 6 of 24
VDD = 2.3 V to 4.5 V1, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.7 3.2 μs
Acquisition Time tACQ 1.8 μs
Time Between Conversions tCYC 5 μs
CNV Pulse Width (CS Mode) tCNVH 10 ns
SCK Period (CS Mode) tSCK 25 ns
SCK Period (Chain Mode) tSCK
VIO ≥ 3 V 29 ns
VIO ≥ 2.7 V 35 ns
VIO ≥ 2.3 V 40 ns
SCK Low Time tSCKL 12 ns
SCK High Time tSCKH 12 ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO ≥ 3 V 24 ns
VIO ≥ 2.7 V 30 ns
VIO ≥ 2.3 V 35 ns
CNV or SDI Low to SDO D13 MSB Valid (CS Mode) tEN
VIO ≥ 2.7 V 18 ns
VIO ≥ 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 5 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns
SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36 ns
1 See Figure 2 and Figure 3 for load conditions.
Timing Diagrams
500µA I
OL
500µA I
OH
1.4V
TO SDO
C
L
50pF
04657-002
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
NOTES
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
04657-003
Figure 3. Voltage Reference Levels for Timing
Data Sheet AD7942
Rev. C | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
IN+1, IN−1 GND − 0.3 V to VDD + 0.3 V
or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD and VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
10-Lead MSOP 200°C/W
10-Lead LFCSP_WD 48.7°C/W
θJC Thermal Impedance
10-Lead MSOP 44°C/W
10-Lead LFCSP_WD 2.96°C/W
Lead Temperature
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7942 Data Sheet
Rev. C | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04657-004
AD7942
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
NOTES
1. PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 REF AI
Reference Input Voltage. The VREF range is from 0.5 V to VDD. REF is referred to the GND pin. Decouple REF
as closely as possible to a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI
Analog Input. IN+ is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V
to VREF.
4 IN− AI Analog Input Ground Sense. Connect IN− to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input pin has multiple functions. On its leading edge, CNV initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, CNV enables the SDO pin
when low. In chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
1 AI = analog input, DI = digital input, DO = digital output, and P = power.
Data Sheet AD7942
Rev. C | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
POSITIVE INL = +0.22LSB
NEGATIVE INL = –0.34LSB
1.00
0.75
0.50
0.25
0
–0.50
–0.75
–1.00
–0.25
INL (LSB)
0 4096 8192 12,288 16,384
CODE
04657-005
Figure 5. Integral Nonlinearity vs. Code
129,941
150,000
100,000
50,000
0
COUNTS
0 0 915 216 0 0
1FFD 1FFE 1FFF 2000 2001 2002 2003
CODE IN HEX
VDD = V
REF
= 2.5V
04657-006
Figure 6. Histogram of a DC Input at the Code Center
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
AMPLITUDE (dB of Full Scale)
0 25 50 75 100 125
FREQUENCY (kHz)
16,384 POINT FFT
VDD = V
REF
= 5V
f
S
= 250kSPS
f
IN
= 20.43kHz
SNR = 85.1dB
THD = –105dB
SFDR = –105.9dB
04657-007
Figure 7. FFT Plot
POSITIVE DNL = +0.24LSB
NEGATIVE DNL = –0.12LSB
1.00
0.75
0.50
0.25
0
–0.50
–0.75
–1.00
–0.25
DNL (LSB)
0 4096 8192 12,288 16,384
CODE
04657-008
Figure 8. Differential Nonlinearity vs. Code
150,000
100,000
50,000
0
COUNTS
000 0 00
1FFD 1FFE 1FFF 2000 2001 2002 2003
CODE IN HEX
VDD = V
REF
= 5V
131,072
04657-009
Figure 9. Histogram of a DC Input at the Code Center
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
AMPLITUDE (dB of Full Scale)
0 25 50 75 100 125
FREQUENCY (kHz)
16,384 POINT FFT
VDD = V
REF
= 2.5V
f
S
= 250kSPS
f
IN
= 20.43kHz
SNR = 84.2dB
THD = –101.7dB
SFDR = –104.3dB
04657-010
Figure 10. FFT Plot
AD7942 Data Sheet
Rev. C | Page 10 of 24
SNR
SINAD
ENOB
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
REFERENCE VOLTAGE (V)
15.0
14.5
14.0
13.5
13.0
ENOB (Bits)
86
85
84
83
82
SNR, SINAD (dB)
04657-011
Figure 11. SNR, SINAD, and ENOB vs. Reference Voltage
90
85
80
75
70
SINAD (dB)
0 50 100 150 200
FREQUENCY (kHz)
V
REF
= 2.5V, –1dB
V
REF
= 5V, –1dB
V
REF
= 5V, –10dB
04657-012
Figure 12. SINAD vs. Frequency
SNR (dB)
75
80
85
90
95
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
04657-013
V
REF
= 5V
V
REF
= 2.5V
Figure 13. SNR vs. Temperature
–
80
–85
–90
–95
–100
–105
–110
–115
0 40 80 120 160 200
FREQUENCY (kHz)
THD (dB)
V
REF
= 2.5V, –1dB
V
REF
= 5V, –1dB
04657-014
Figure 14. THD vs. Frequency
THD (dB)
–120
–110
–100
–
90
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
04657-015
V
REF
= 5V
V
REF
= 2.5V
Figure 15. THD vs. Temperature
VDD
VIO
f
S
= 100kSPS
1000
750
500
250
0
OPER
A
TING CURRENTS (μA)
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY (V)
04657-016
Figure 16. Operating Currents vs. Supply
Data Sheet AD7942
Rev. C | Page 11 of 24
VDD + VIO
1000
750
500
250
0
POWER-DOWN CURRENTS (nA)
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
04657-017
Figure 17. Power-Down Currents vs. Temperature
VIO
VDD = 5V
VDD = 2.5V
f
S
= 100kSPS
1000
900
800
700
600
500
400
300
200
100
0
OPERATING CURRENTS (µA)
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
04657-018
Figure 18. Operating Currents vs. Temperature
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
OFFSET AND GAIN ERROR (LSB)
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
OFFSET ERROR
GAIN ERROR
04657-019
Figure 19. Offset Error and Gain Error vs. Temperature
04657-020
SDO CAPACITIVE LOAD (pF)
1200 20406080100
t
DSDO
DELAY (ns)
25
20
15
10
5
0
VDD = 2.5V, 85°C
VDD = 3.3V, 25°C
VDD = 3.3V, 85°C
VDD = 5V, 85°C
VDD = 5V, 25°C
VDD = 2.5V, 25°C
Figure 20. tDSDO Delay vs. SDO Capacitance Load and Supply
AD7942 Data Sheet
Rev. C | Page 12 of 24
TERMINOLOGY
Linearity Error or Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (152.6 μV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111...10 to 111...11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999542 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the
ideal level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels, between the rms amplitude of the
input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula and is
expressed in bits as follows:
ENOB = (SINADdB − 1.76)/6.02
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Resp onse
The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.
Data Sheet AD7942
Rev. C | Page 13 of 24
THEORY OF OPERATION
SW+MSB
4096C
IN
+
LSB
COMP CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN–
4C 2C C C8192C
SW–MSB
4096C
LSB
4C 2C C C8192C
04657-021
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7942 is a fast, low power, single-supply, precise 14-bit
ADC using successive approximation architecture.
The AD7942 is capable of converting 250,000 samples per
second (250 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it consumes typically
1.25 μW with a 2.5 V power supply, which is ideal for battery-
powered applications.
The AD7942 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7942 is specified from 2.3 V to 5.5 V and can be inter-
faced to a 1.8 V, 2.5 V, 3.3 V, or 5 V digital logic. It is housed in
a 10-lead MSOP or a tiny 10-lead LFCSP that is space saving,
yet allows flexible configurations. It is pin-for-pin-compatible
with the 16-bit ADC AD7685.
CONVERTER OPERATION
The AD7942 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase starts, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs (IN+ and IN−) captured at the end of the
acquisition phase, is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4 ... VREF/16,384). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase and the control logic
generates the ADC output code and a busy signal indicator.
Because the AD7942 has an on-board conversion clock, the
serial clock is not required for the conversion process.
AD7942 Data Sheet
Rev. C | Page 14 of 24
AD7942
REF
GND
VDD
IN–
IN+
VIO
SDI
SCK
SDO
CNV
3- OR 4-WIRE INTERFACE (NOTE 5)
100nF
100nF
5V
10µF
(NOTE 2)
1.8V TO VDD
REF
0V TO V
REF
33Ω
2.7nF
(NOTE 3)
(NOTE 4)
(NOTE 1)
NOTE 1: SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
NOTE 2: C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
04657-022
Figure 22. Typical Application Diagram
Transfer Functions
The ideal transfer characteristic for the AD7942 is shown in
Figure 23 and Table 7.
000...000
000...001
000...010
111. ..101
111. ..110
111. ..111
ADC CODE (STRAIGHT BIN
A
R
Y)
ANALOG INPUT
+FS – 1.5 LSB
+
FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
04657-023
Figure 23. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V
Digital Output Code
Hexadecimal
FSR – 1 LSB 4.999695 V 0x3FFF1
Midscale + 1 LSB 2.500305 V 0x2001
Midscale 2.5 V 0x2000
Midscale – 1 LSB 2.499695 V 0x1FFF
–FSR + 1 LSB 305.2 μV 0x0001
–FSR 0 V 0x00002
1 This is also the code for an overranged analog input (VIN+ – VIN− > VREF – VGND).
2 This is also the code for an underranged analog input (VIN+ – VIN− < VGND).
TYPICAL CONNECTION DIAGRAM
Figure 22 shows an example of the recommended connection
diagram for the AD7942 when multiple supplies are available.
Analog Input
Figure 24 shows an equivalent circuit of the input structure of
the AD7942.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to become forward-
biased and to start conducting current. However, these diodes
can handle a forward-biased current of 130 mA maximum. For
instance, these conditions could eventually occur when the
input buffer (U1) supplies are different from VDD. In such a
case, an input buffer with a short-circuit current limitation can
be used to protect the part.
C
IN
R
IN
D1
D2
C
PIN
IN+
OR IN–
GND
V
DD
04657-024
Figure 24. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the diffe-
rential signal between IN+ and IN−. By using this differential
input, small signals common to both inputs are rejected, as
shown in Figure 25, which represents the typical CMRR over
frequency. For instance, by using IN− to sense a remote signal
ground, ground potential differences between the sensor and
the local ADC ground are eliminated.
Data Sheet AD7942
Rev. C | Page 15 of 24
CMRR (dB)
40
50
60
70
80
FREQUENCY (kHz)
101 100 1000 10000
VDD = 5V
04657-025
Figure 25. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
input, IN+, can be modeled as a parallel combination of the
Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typi-
cally 3 kΩ and is a lumped component made up of some serial
resistors and the on resistance of the switches. CIN is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, when the switches are opened, the input imped-
ance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter
that reduces undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7942 can be driven directly. Large source impedances sig-
nificantly affect the ac performance, especially total harmonic
distortion (THD). The dc performances are less sensitive to the
input impedance. The maximum source impedance depends on
the amount of THD that can be tolerated. The THD degrades as
a function of the source impedance and the maximum input
frequency, as shown in Figure 26.
–115
–110
–105
–100
–95
–90
–85
–80
–75
–
70
THD (dB)
FREQUENCY (kHz)
250 50 75 100
04657-026
R
S
= 15Ω
R
S
= 50Ω
R
S
= 100Ω
R
S
= 250Ω
R
S
= 500Ω
R
S
= 1kΩ
Figure 26. THD vs. Analog Input Frequency and Source Resistance
Driver Amplifier Choice
Although the AD7942 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7942. Note that the AD7942
produces much less noise than most other 14-bit ADCs
and therefore can be driven by a noisier op amp while
preserving the same or better system performance. The
noise coming from the driver is filtered by the AD7942
analog input circuit, 1-pole, low-pass filter made by RIN
and CIN or by the external filter, if one is used.
For ac applications, the driver needs to have a THD
performance suitable to that of the AD7942. Figure 14
gives the THD vs. frequency that the driver should exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7942 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
14-bit level (0.006%). In the amplifier data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 14-bit level
and should be verified prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841 Very low noise, small, and low power
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single supply, low power
AD8519 Small, low power, and low frequency
AD8031 High frequency and low power
Voltage Reference Input
The AD7942 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for example,
a reference buffer using the AD8031 or the AD8605), a 10 μF
(X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance, using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values
≥ 2.2 μF can be used with a minimal impact on performance,
especially on DNL.
AD7942 Data Sheet
Rev. C | Page 16 of 24
Power Supply
The AD7942 is specified over a wide operating range from
2.3 V to 5.5 V. It has, unlike other low voltage converters, a
noise low enough to design a low supply (2.5 V) 14-bit resolu-
tion system with respectable performance. It uses two power
supply pins: a core supply, VDD, and a digital input/output
interface supply, VIO. VIO allows direct interface with any
logic between 1.8 V and VDD. To reduce the supplies needed,
the VIO and VDD can be tied together. The AD7942 is indepen-
dent of power supply sequencing between VIO and VDD.
Additionally, it is insensitive to power supply variations over
a wide frequency range, as shown in Figure 27.
55
60
65
70
75
80
85
90
PSRR (dB)
FREQUENCY (kHz)
10 1000100 10000
04657-027
VDD = 5V
Figure 27. PSRR vs. Frequency
The AD7942 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 28. This makes the part
ideal for low sampling rates (even rates of a few hertz) and low
battery-powered applications.
VDD = 5V VDD = 2.5V
VIO
0
1000
10
0.1
0.001
OPER
A
TING CURRENT (µA)
10 100 1000 10000 100000 1000000
SAMPLING RATE (SPS)
04657-028
Figure 28. Operating Current vs. Sampling Rate
Supplying the ADC from the Reference
For simplified applications, the AD7942, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 29. The reference line can be driven by either
The system power supply directly,
A reference voltage with enough current output capability,
such as the ADR43x, or
A reference buffer, such as the AD8031, that can also filter
the system power supply (see Figure 29).
AD8031
AD7942
VIOREF VDD
10µF
10Ω
10kΩ
5V
5V
5V
(NOTE 1)
1µF
04657-029
NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER.
1µF
Figure 29. Example of Application Circuit
DIGITAL INTERFACE
Although the AD7942 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7942 is compatible with SPI, QSPI,
digital hosts, and DSPs (for example, Blackfin® ADSP-BF53x or
ADSP-219x). A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections, which is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
conversions, to be independent of the readback timing (SDI).
This is useful in low jitter sampling or simultaneous sampling
applications.
When in chain mode, the AD7942 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on
a single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either mode, the AD7942 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior
to readback.
The busy indicator feature is enabled as follows:
In the CS mode, if CNV or SDI is low when the ADC
conversion ends (see Figure 33 and Figure 37).
In the chain mode, if SCK is high during the CNV rising
edge (see Figure 41).
Data Sheet AD7942
Rev. C | Page 17 of 24
CS Mode 3-Wire Without Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 30 and the corresponding timing
diagram is shown in Figure 31.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the CS mode, and forces SDO to high impedance.
When a conversion is initiated, it continues to completion irres-
pective of the state of CNV. For instance, it is useful to bring
CNV low to select other SPI devices, such as analog
multiplexers. However, CNV must be returned high before the
minimum conversion time and held high until the maximum
conversion time to avoid generating the busy signal indicator.
When the conversion is complete the AD7942 enters the acqui-
sition phase and powers down. When CNV goes low, the MSB
is output onto SDO. The remaining data bits are then clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
14th SCK falling edge or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
CNV
SCK
SDOSDI DATA IN
CLK
CONVERT
IO
DIGITAL HOST
AD7942
04657-030
Figure 30. CS Mode 3-Wire Without Busy Indicator
Connection Diagram (SDI High)
SDO D13 D12 D11 D1 D0
tDIS
SCK 123 121314
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSIONACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
04657-031
Figure 31. CS Mode 3-Wire Without Busy Indicator, Serial Interface Timing (SDI High)
AD7942 Data Sheet
Rev. C | Page 18 of 24
CS Mode 3-Wire with Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input. The connection diagram is shown in Figure 32 and the
corresponding timing diagram is shown in Figure 33.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the CS mode, and forces SDO to high impedance.
SDO is maintained in high impedance until the completion of
the conversion irrespective of the state of CNV. Prior to the
minimum conversion time, CNV can be used to select other
SPI devices, such as analog multiplexers. However, CNV must
be returned low before the minimum conversion time and held
low until the maximum conversion time to guarantee the
generation of the busy signal indicator. When the conversion
is complete, SDO goes from high impedance to low impedance.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7942 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After
the optional 15th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDOSDI DATA IN
IRQ
CLK
CONVERT
IO
VIO DIGITAL HOST
AD7942
04657-032
47kΩ
Figure 32. CS Mode 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDO D13 D12 D1 D0
t
DIS
SCK 123 131415
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
CNVH
t
ACQ
ACQUISITION
S
DI = 1
04657-033
Figure 33. CS Mode 3-Wire with Busy Indicator, Serial Interface Timing (SDI High)
Data Sheet AD7942
Rev. C | Page 19 of 24
CS Mode 4-Wire Without Busy Indicator
This mode is most often used when multiple AD7942s are
connected to an SPI-compatible digital host. A connection
diagram using two AD7942s is shown in Figure 34 and the
corresponding timing diagram is given in Figure 35.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers.
However, SDI must be returned high before the minimum
conversion time elapses and held high until the maximum
conversion time is completed to avoid generating the busy
signal indicator. When the conversion is complete, the AD7942
enters the acquisition phase and powers down. Each ADC result
can be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK driving edges. The data is valid on
both SCK edges. Although the nondriving edge can be used to
capture the data, a digital host also using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14th SCK falling edge or when SDI goes high,
whichever is earlier, SDO returns to high impedance and
another AD7942 can be read.
If multiple AD7942s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
CNV
SCK
SDOSDI
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
AD7942
CNV
SCK
SDOSDI
AD7942
04657-034
Figure 34. CS Mode 4-Wire Without Busy Indicator Connection Diagram
SDO D13 D12 D11 D1 D0
t
DIS
SCK 123 262728
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI (CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
12 13
t
SCK
t
SCKL
t
SCKH
D0 D13 D12
15 1614
SDI (CS2)
04657-035
Figure 35. CS Mode 4-Wire Without Busy Indicator, Serial Interface Timing
AD7942 Data Sheet
Rev. C | Page 20 of 24
CS Mode 4-Wire with Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input and to keep CNV (which is used to sample the analog
input) independent of the signal used to select the data reading.
This requirement is particularly important in applications where
low jitter on CNV is desired. The connection diagram is shown
in Figure 36 and the corresponding timing diagram is given in
Figure 37.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and held low until the maximum conversion time
is completed to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low. With a pull-up on the SDO line this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7942 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK driving edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host also using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 15th SCK falling edge
or SDI going high, whichever is earlier, the SDO returns to high
impedance.
CNV
SCK
SDOSDI DATA IN
IRQ
CLK
CONVERT
CS1
VIO DIGITAL HOST
AD7942
04657-036
47Ω
Figure 36. CS Mode 4-Wire with Busy Indicator Connection Diagram
SDO D13 D12 D1 D0
tDIS
SCK 1 2 3 131415
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
A
CQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
04657-037
Figure 37. CS Mode 4-Wire with Busy Indicator, Serial Interface Timing
Data Sheet AD7942
Rev. C | Page 21 of 24
Chain Mode Without Busy Indicator
This mode can be used to daisy-chain multiple AD7942s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register. A connection diagram example using
two AD7942s is shown in Figure 38 and the corresponding
timing diagram is given in Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, selects the
chain mode, and disables the busy indicator. In this mode, CNV
is held high during the conversion phase and the subsequent
data readback. When the conversion is complete, the MSB is
output onto SDO and the AD7942 enters the acquisition phase
and powers down. The remaining data bits stored in the inter-
nal shift register are then clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first and 14 × N clocks are
required to readback the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture
the data, a digital host also using the SCK falling edge allows
a faster reading rate and consequently more AD7942s in the
chain, provided the digital host has an acceptable hold time.
The maximum conversion rate may be reduced due to the total
readback time. For instance, with a 5 ns digital host setup time
and 3 V interface, up to eight AD7942s running at a conversion
rate of 220 kSPS can be daisy-chained on a 3-wire port.
CNV
SCK
SDOSDI
CLK
CONVERT
DATA IN
DIGITAL HOST
AD7942
B
CNV
SCK
SDOSDI
AD7942
A
04657-038
Figure 38. Chain Mode Without Busy Indicator Connection Diagram
SDO
A
= SDI
B
D
A
13 D
A
12 D
A
11
SCK 1 2 3 262728
t
SSDISCK
t
HSDISCK
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV
D
A
1
12 13
t
SCK
t
SCKL
t
SCKH
D
A
0
15 1614
SDI
A
= 0
SDO
B
D
B
13 D
B
12 D
B
11 D
A
1D
B
1D
B
0D
A
13 D
A
12
t
HSDO
t
DSDO
t
SSCKCNV
t
HSCKCNV
D
A
0
04657-039
Figure 39. Chain Mode Without Busy Indicator, Serial Interface Timing
AD7942 Data Sheet
Rev. C | Page 22 of 24
Chain Mode with Busy Indicator
This mode can also be used to daisy-chain multiple AD7942s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applica-
tions or for systems with a limited interfacing capacity. Data
readback is analogous to clocking a shift register. A connection
diagram example using three AD7942s is shown in Figure 40
and the corresponding timing diagram is given in Figure 41.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, SDO in the near end ADC
(ADC C in Figure 40) is driven high. This transition on SDO
can be used as a busy indicator to trigger the data readback
controlled by the digital host. The AD7942 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 14 × N + 1
clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host also
using the SCK falling edge allows a faster reading rate and
consequently more AD7942s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 5 ns digital
host setup time and a 3 V interface, up to eight AD7942s
running at a conversion rate of 220 kSPS can be daisy-chained
to a single 3-wire port.
CNV
SCK
SDOSDI
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
AD7942
C
CNV
SCK
SDOSDI
AD7942
B
04657-040
CNV
SCK
SDOSDI
AD7942
A
Figure 40. Chain Mode with Busy Indicator Connection Diagram
04657-041
SDO
A
= SDI
B
D
A
13 D
A
12 D
A
11
SCK 123 35 41 42
t
EN
CONVERSION
A
CQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV = SDI
A
D
A
1
413
t
SCK
t
SCKH
t
SCKL
D
A
0
15 3114
SDO
B
= SDI
C
D
B
13 D
B
12 D
B
11 D
A
1D
B
1D
B
0D
A
13 D
A
12
43
t
SSDISCK
t
HSDISCK
t
HSDO
t
DSDO
SDO
C
D
C
13 D
C
12 D
C
11 D
A
1D
A
0D
C
1D
C
0D
A
12
17 27 2816 29
D
B
1D
B
0D
A
13D
B
13 D
B
12
t
DSDOSDI
t
SSCKCNV
t
HSCKCNV
D
A
0
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
Figure 41. Chain Mode with Busy Indicator, Serial Interface Timing
Data Sheet AD7942
Rev. C | Page 23 of 24
APPLICATION HINTS
LAYOUT
Design the PCB that houses the AD7942 so that the analog and
digital sections are separated and confined to certain areas of
the board. The pinout of the AD7942, with all its analog signals
on the left side and all its digital signals on the right side, eases
this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7942 is used as a shield. Fast switching signals, such as
CNV or clocks, should never run near analog signal paths.
Avoid crossover of digital and analog signals.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the case of being
split, the ground plane should be joined underneath the AD7942.
The AD7942 voltage reference input, REF, has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is accomplished by placing the reference
decoupling ceramic capacitor close to, and ideally right up
against, the REF and GND pins. Connect these pins with wide,
low impedance traces.
Finally, decouple the power supply of the AD7942, VDD and
VIO, with ceramic capacitors, typically 100 nF, placed close to
the AD7942. Connect the capacitors using short and large
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines. An example of layout
following these rules is shown in Figure 42 and Figure 43.
EVALUATING THE PERFORMANCE OF AD7942
Other recommended layouts for the AD7942 are outlined in
the evaluation board for the AD7942 (EVAL-AD7942SDZ). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-SDP-CB1Z.
04657-042
Figure 42. Layout Example (Top Layer)
04657-043
Figure 43. Layout Example (Bottom Layer)
AD7942 Data Sheet
Rev. C | Page 24 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.23
0.08
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
PIN 1
COPLANARITY
0.10
3.10
3.00
2.90
3.10
3.00
2.90
5.15
4.90
4.65
Figure 44. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
031208-B
TOP VIEW
10
1
6
5
0.30
0.23
0.18
*EXPOSED
PAD
(BOTTOM VIEW)
PIN 1 INDEX
AREA
3.00
BSC SQ
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.05 MAX
0.02 NOM
0.80 MAX
0.55 NOM
1.74
1.64
1.49
2.48
2.38
2.23
0.50
0.40
0.30
0.50 BSC
PIN 1
INDICATOR
(R 0.20)
*PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES.
Figure 45. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very, Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Ordering Quantity Package Option Branding
AD7942BRMZ –40°C to +85°C 10-Lead MSOP Tube, 50 RM-10 C4S
AD7942BRMZ-RL7 –40°C to +85°C 10-Lead MSOP Reel, 1,000 RM-10 C4S
AD7942BCPZRL –40°C to +85°C 10-Lead LFCSP_WD Reel, 5,000 CP-10-9 C4S
AD7942BCPZRL7 –40°C to +85°C 10-Lead LFCSP_WD Reel, 1,500 CP-10-9 C4S
EVAL-AD7942SDZ Evaluation Board
EVAL-SDP-CB1Z Controller Board
1 Z = RoHS Compliant Part.
2 The EVAL-AD7942SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3 The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.
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registered trademarks are the property of their respective owners.
D04657-0-6/14(C)
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