RTRT
RTRT
RTRT
RTRT
Line Card in SLOT 1
Z0
Z0
Z0
Z0
BACKPLANE
DS91M040
Line Card in SLOT N-1
M-LVDS Receivers
RT = ZLOADED
Line Card in SLOT N
M-LVDS Receivers
DS91M040
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DS91M040 125 MHz Quad M-LVDS Transceiver
Check for Samples: DS91M040
1FEATURES DESCRIPTION
The DS91M040 is a quad M-LVDS transceiver
2• DC - 125 MHz / 250 Mbps Low Jitter, Low designed for driving / receiving clock or data signals
Skew, Low Power Operation to / from up to four multipoint networks.
• Wide Input Common Mode Voltage Range M-LVDS (Multipoint LVDS) is a new family of bus
Allows up to ±1V of GND Noise interface devices based on LVDS technology
• Conforms to TIA/EIA-899 M-LVDS Standard specifically designed for multipoint and multidrop
• Pin Selectable M-LVDS Receiver Type (1 or 2) cable and backplane applications. It differs from
standard LVDS in providing increased drive current to
• Controlled Transition Times (2.0 ns typ) handle double terminations that are required in multi-
Minimize Reflections point applications. Controlled transition times
• 8 kV ESD on M-LVDS I/O pins protects minimize reflections that are common in multipoint
adjoining components configurations due to unterminated stubs. M-LVDS
• Flow-Through Pinout Simplifies PCB Layout devices also have a very large input common mode
voltage range for additional noise margin in heavily
• Small 5 mm x 5 mm WQFN-32 Space Saving loaded and noisy backplane environments.
Package A single DS91M040 channel is a half-duplex
APPLICATIONS transceiver that accepts LVTTL/LVCMOS signals at
the driver inputs and converts them to differential M-
• Multidrop / Multipoint Clock and Data LVDS signal levels. The receiver inputs accept low
Distribution voltage differential signals (LVDS, BLVDS, M-LVDS,
• High-Speed, Low Power, Short-Reach LVPECL and CML) and convert them to 3V LVCMOS
Alternative to TIA/EIA-485/422 signals. The DS91M040 supports both M-LVDS type
1 and type 2 receiver inputs.
• Clock Distribution in AdvancedTCA (ATCA)
and MicroTCA (μTCA, uTCA) Backplanes
System Diagram
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DE0
RO0
B0
A0
DI0
RE0
DE1
RO1
B1
A1
DI1
RE1
DE2
RO2
B2
A2
DI2
RE2
DE3
RO3
B3
A3
DI3
RE3
FSEN2
FSEN1
MDE
RO0
DI0
RO1
DI1
B0
A0
B1
A1
1
2
3
4
24
22
21
23
(GND)
DAP
RO2
DI2
RO3
DI3
B2
A2
B3
A3
5
6
7
8
20
18
17
19
FSEN2
MDE
VDD
VDD
9
10
11
12
RE2
DE2
RE3
DE3
13
14
15
16
FSEN1
GND
VDD
VDD
32
30
29
31
RE1
DE1
RE0
DE0
28
26
25
27
DS91M040
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Connection Diagram
Logic Diagram
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xxx
xxx
xxx
High High
Low Low
0 V
2.4 V
-2.4 V
50 mV
-50 mV
150 mV
Transition Region
Type 1 Type 2
VID
DS91M040
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SNLS283M –FEBRUARY 2008–REVISED APRIL 2013
PIN DESCRIPTIONS
Number Name I/O, Type Description
1, 3, 5, 7 RO O, LVCMOS Receiver output pin.
26, 28, 13, 15 RE I, LVCMOS Receiver enable pin: When RE is high, the receiver is disabled. When RE is
low, the receiver is enabled. There is a 300 kΩpullup resistor on this pin.
25, 27, 14, 16 DE I, LVCMOS Driver enable pin: When DE is low, the driver is disabled. When DE is high, the
driver is enabled. There is a 300 kΩpulldown resistor on this pin.
2, 4, 6, 8 DI I, LVCMOS Driver input pin.
31, DAP GND Power Ground pin and pad.
17, 19, 21, 23 A I/O, M-LVDS Non-inverting driver output pin/Non-inverting receiver input pin
18, 20, 22, 24 B I/O, M-LVDS Inverting driver output pin/Inverting receiver input pin
11, 12, 29, 30 VDD Power Power supply pin, +3.3V ± 0.3V
32 FSEN1 I, LVCMOS Failsafe enable pin with a 300 kΩpullup resistor. This pin enables Type 2
receiver on inputs 0 and 2.
FSEN1 = L --> Type 1 receiver inputs
FSEN1 = H --> Type 2 receiver inputs
9 FSEN2 I, LVCMOS Failsafe enable pin with a 300 kΩpullup resistor. This pin enables Type 2
receiver on inputs 1 and 3.
FSEN2 = L --> Type 1 receiver inputs
FSEN2 = H --> Type 2 receiver inputs
10 MDE I, LVCMOS Master enable pin. When MDE is H, the device is powered up. When MDE is L,
the device overrides all other control and powers down.
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built
in offset that is 100mV greater then VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
Figure 1. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
Power Supply Voltage −0.3V to +4V
LVCMOS Input Voltage −0.3V to (VDD + 0.3V)
LVCMOS Output Voltage −0.3V to (VDD + 0.3V)
M-LVDS I/O Voltage −1.9V to +5.5V
M-LVDS Output Short Circuit Current Duration Continuous
Junction Temperature +140°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range Soldering (4 sec.) +260°C
Maximum Package Power Dissipation @ +25°C RTV Package 3.91W
Derate RTV Package 34 mW/°C above +25°C
Package Thermal Resistance (4-Layer, 2 oz. Cu, θJA +29.4°C/W
JEDEC) θJC +2.8°C/W
ESD Susceptibility HBM(3) ≥8 kV
MM(4) ≥250V
CDM(5) ≥1250V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions Min Typ Max Units
Supply Voltage, VDD 3.0 3.3 3.6 V
Voltage at Any Bus Terminal (Separate or Common-Mode) −1.4 +3.8 V
Differential Input Voltage VID 2.4 V
LVTTL Input Voltage High VIH 2.0 VDD V
LVTTL Input Voltage Low VIL 0 0.8 V
Operating Free Air Temperature TA−40 +25 +85 °C
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DC Electrical Characteristics(1)(2)(3)(4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
M-LVDS Driver
|VAB| Differential output voltage magnitude RL= 50Ω, CL= 5 pF 480 650 mV
ΔVAB Change in differential output voltage magnitude Figure 2 −50 0 +50 mV
between logic states Figure 4
VOS(SS) Steady-state common-mode output voltage RL= 50Ω, CL= 5 pF 0.3 1.6 2.1 V
|ΔVOS(SS)| Change in steady-state common-mode output voltage Figure 2 0 +50 mV
between logic states Figure 3
VA(OC) Maximum steady-state open-circuit output voltage Figure 5 0 2.4 V
VB(OC) Maximum steady-state open-circuit output voltage 0 2.4 V
VP(H) Voltage overshoot, low-to-high level output(5) RL= 50Ω, CL= 5pF,CD= 0.5 pF 1.2VSS V
Figure 7
VP(L) Voltage overshoot, high-to-low level output(5) −0.2V V
Figure 8 SS
IIH High-level input current (LVTTL inputs) VIH = 3.6V -15 15 μA
IIL Low-level input current (LVTTL inputs) VIL = 0.0V -15 15 μA
VCL Input Clamp Voltage (LVTTL inputs) IIN = -18 mA -1.5 V
IOS Differential short-circuit output current(6) Figure 6 -43 43 mA
M-LVDS Receiver
VIT+ Positive-going differential input voltage threshold See Truth Tables Type 1 16 50 mV
Type 2 100 150 mV
VIT−Negative-going differential input voltage threshold See Truth Tables Type 1 −50 20 mV
Type 2 50 94 mV
VOH High-level output voltage (LVTTL output) IOH =−8mA 2.4 2.7 V
VOL Low-level output voltage (LVTTL output) IOL = 8mA 0.28 0.4 V
IOZ TRI-STATE output current VO= 0V or 3.6V −10 10 μA
IOSR Short-circuit receiver output current (LVTTL output) VO= 0V -50 -90 mA
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
(3) Typical values represent most likely parametric norms for VDD = +3.3V and TA= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not specified.
(4) CLincludes fixture capacitance and CDincludes probe capacitance.
(5) Specification is ensured by characterization and is not tested in production.
(6) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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DC Electrical Characteristics(1)(2)(3)(4) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
M-LVDS Bus (Input and Output) Pins
IATransceiver input/output current VA= 3.8V, VB= 1.2V 32 µA
VA= 0V or 2.4V, VB= 1.2V −20 +20 µA
VA=−1.4V, VB= 1.2V −32 µA
IBTransceiver input/output current VB= 3.8V, VA= 1.2V 32 µA
VB= 0V or 2.4V, VA= 1.2V −20 +20 µA
VB=−1.4V, VA= 1.2V −32 µA
IAB Transceiver input/output differential current (IA−IB) VA= VB,−1.4V ≤V≤3.8V −4 +4 µA
IA(OFF) Transceiver input/output power-off current VA= 3.8V, VB= 1.2V,
DE = 0V 32 µA
0V ≤VDD ≤1.5V
VA= 0V or 2.4V, VB= 1.2V,
DE = 0V −20 +20 µA
0V ≤VDD ≤1.5V
VA=−1.4V, VB= 1.2V,
DE = 0V −32 µA
0V ≤VDD ≤1.5V
IB(OFF) Transceiver input/output power-off current VB= 3.8V, VA= 1.2V,
DE = 0V 32 µA
0V ≤VDD ≤1.5V
VB= 0V or 2.4V, VA= 1.2V,
DE = 0V −20 +20 µA
0V ≤VDD ≤1.5V
VB=−1.4V, VA= 1.2V,
DE = 0V −32 µA
0V ≤VDD ≤1.5V
IAB(OFF) Transceiver input/output power-off differential current VA= VB,−1.4V ≤V≤3.8V,
(IA(OFF) −IB(OFF)) DE = 0V −4 +4 µA
0V ≤VDD ≤1.5V
CATransceiver input/output capacitance VDD = OPEN 7.8 pF
CBTransceiver input/output capacitance 7.8 pF
CAB Transceiver input/output differential capacitance 3 pF
CA/B Transceiver input/output capacitance balance (CA/CB) 1
SUPPLY CURRENT (VCC)
ICCD Driver Supply Current RL= 50Ω, DE = H, RE = H 67 75 mA
ICCZ TRI-STATE Supply Current DE = L, RE = H 22 26 mA
ICCR Receiver Supply Current DE = L, RE = L 32 38 mA
ICCPD Power Down Supply Current MDE = L 3 5 mA
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Switching Characteristics(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
DRIVER AC SPECIFICATIONS
tPLH Differential Propagation Delay Low to High RL= 50Ω, CL= 5 pF, 1.5 3.3 5.5 ns
tPHL Differential Propagation Delay High to Low CD= 0.5 pF 1.5 3.3 5.5 ns
tSKD1 Pulse Skew(4)(5) Figure 7 30 125 ps
Figure 8
tSKD2 Channel-to-Channel Skew(4)(6) 100 200 ps
tSKD3 Part-to-Part Skew(4)(7) 0.8 1.6 ns
tSKD4 Part-to-Part Skew(4)(8) 4 ns
tTLH Rise Time(4) 1.2 2.0 3.0 ns
tTHL Fall Time(4) 1.2 2.0 3.0 ns
tPZH Enable Time (Z to Active High) RL= 50Ω, CL= 5 pF, 7.5 11.5 ns
tPZL Enable Time (Z to Active Low ) CD= 0.5 pF 8.0 11.5 ns
tPLZ Disable Time (Active Low to Z) Figure 9 7.0 11.5 ns
Figure 10
tPHZ Disable Time (Active High to Z) 7.0 11.5 ns
RECEIVER AC SPECIFICATIONS
tPLH Propagation Delay Low to High CL= 15 pF 1.5 3.0 4.5 ns
tPHL Propagation Delay High to Low Figure 11 1.5 3.1 4.5 ns
Figure 12
Figure 13
tSKD1A Pulse Skew (Receiver Type 1)(4)(5) 55 325 ps
tSKD1B Pulse Skew (Receiver Type 2)(4)(5) 475 800 ps
tSKD2 Channel-to-Channel Skew(4)(6) 60 300 ps
tSKD3 Part-to-Part Skew(4)(7) 0.6 1.2 ns
tSKD4 Part-to-Part Skew(8) 3 ns
tTLH Rise Time(4) 0.3 1.1 1.6 ns
tTHL Fall Time(4) 0.3 0.65 1.6 ns
tPZH Enable Time (Z to Active High) RL= 500Ω, CL= 15 pF 3 5.5 ns
tPZL Enable Time (Z to Active Low) Figure 14 3 5.5 ns
Figure 15
tPLZ Disable Time (Active Low to Z) 3.5 5.5 ns
tPHZ Disable Time (Active High to Z) 3.5 5.5 ns
GENERIC AC SPECIFICATIONS
tWKUP Wake Up Time(4) 500 ms
(Master Device Enable (MDE) time)
fMAX Maximum Operating Frequency(4) 125 MHz
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms for VDD = +3.3V and TA= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not specified.
(3) CLincludes fixture capacitance and CDincludes probe capacitance.
(4) Specification is ensured by characterization and is not tested in production.
(5) tSKD1, |tPLHD −tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(6) tSKD2, Channel-to-Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels.
(7) tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
(8) tSKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max −Min|
differential propagation delay.
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A
B
~ 1.9V
~ 1.3V
'VOS(SS)
VOS(PP)
VOS
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Test Circuits and Waveforms
Figure 2. Differential Driver Test Circuit
Figure 3. Differential Driver Waveforms
Figure 4. Differential Driver Full Load Test Circuit
Figure 5. Differential Driver DC Open Test Circuit
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Figure 6. Differential Driver Short-Circuit Test Circuit
Figure 7. Driver Propagation Delay and Transition Time Test Circuit
Figure 8. Driver Propagation Delays and Transition Time Waveforms
Figure 9. Driver TRI-STATE Delay Test Circuit
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Figure 10. Driver TRI-STATE Delay Waveforms
Figure 11. Receiver Propagation Delay and Transition Time Test Circuit
Figure 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms
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Figure 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms
Figure 14. Receiver TRI-STATE Delay Test Circuit
Figure 15. Receiver TRI-STATE Delay Waveforms
TRUTH TABLES
DS91M040 Transmitting(1)
Inputs Outputs
RE DE DI B A
X H H L H
X H L H L
X L X Z Z
(1) X — Don't care condition
Z — High impedance state
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DS91M040 as Type 1 Receiving(1)
Inputs Output
FSEN RE DE A −B RO
L L X ≥+0.05V H
L L X ≤ −0.05V L
L L X −0.05V Undefined
≤A-B ≤+0.05V
L H X X Z
(1) X — Don't care condition
Z — High impedance state DS91M040 as Type 2 Receiving(1)
Inputs Output
FSEN RE DE A −B RO
H L X ≥+0.15V H
H L X ≤+0.05V L
H L X +0.05V Undefined
≤A-B ≤+0.15V
H H X X Z
(1) X — Don't care condition
Z — High impedance state
DS91M040 Type 1 Receiver Input Threshold Test Voltages(1)
Applied Voltages Resulting Differential Input Voltage Resulting Common-Mode Input Receiver Output
Voltage
VIA VIB VID VICM R
2.400V 0.000V 2.400V 1.200V H
0.000V 2.400V −2.400V 1.200V L
3.800V 3.750V 0.050V 3.775V H
3.750V 3.800V −0.050V 3.775V L
−1.350V −1.400V 0.050V −1.375V H
−1.400V −1.350V −0.050V −1.375V L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
DS91M040 Type 2 Receiver Input Threshold Test Voltages(1)
Applied Voltages Resulting Differential Input Voltage Resulting Common-Mode Input Receiver Output
Voltage
VIA VIB VID VIC R
2.400V 0.000V 2.400V 1.200V H
0.000V 2.400V −2.400V 1.200V L
3.800V 3.650V 0.150V 3.725V H
3.800V 3.750V 0.050V 3.775V L
−1.250V −1.400V 0.150V −1.325V H
−1.350V −1.400V 0.050V −1.375V L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
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4.5
4.0
3.5
3.0
2.5
2.0
1.5-50 -10 30 70 110 150
f = 125 MHz
DRIVER PROPAGATION DELAY (tPHLD) (ns)
TEMPERATURE (°C)
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
180
150
120
90
60
30
00 25 50 75 100 125
f = 125 MHz
VCC = 3.3V
TA = 25°C
RL = 50:On all CH)
DE0,1,2,3 = H
RE*0,1,2,3 = H
DRIVER POWER SUPPLY CURRENT (mA)
FREQUENCY (MHz)
900
750
600
450
300
150
00 25 50 75 100 125
f = 1 MHz
VCC = 3.3V
TA = 25°C
VOD - DRIVER OUTPUT AMPLITUDE (mV)
RESISTIVE LOAD (:)
4.5
4.0
3.5
3.0
2.5
2.0
1.5-50 -10 30 70 110 150
f = 125 MHz
DRIVER PROPAGATION DELAY (tPLHD) (ns)
TEMPERATURE (°C)
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
2.8
2.5
2.2
1.9
1.6
1.3
1.0-50 -10 30 70 110 150
f = 125 MHz
DRIVER RISE TIME (10-90%) (ns)
TEMPERATURE (°C)
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
2.8
2.5
2.2
1.9
1.6
1.3
1.0-50 -10 30 70 110 150
f = 125 MHz
DRIVER FALL TIME (10-90%) (ns)
TEMPERATURE (°C)
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
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Typical Performance Characteristics
Figure 16. Driver Rise Time as a Function of Temperature Figure 17. Driver Fall Time as a Function of Temperature
Figure 18. Driver Output Signal Amplitude as a Function of Figure 19. Driver Propagation Delay (tPLHD) as a Function
Resistive Load of Temperature
Figure 20. Driver Propagation Delay (tPHLD) as a Function Figure 21. Driver Power Supply Current as a Function of
of Temperature Frequency
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3.8
3.5
3.2
2.9
2.6
2.3
2.0
-4.0 -2.4 -0.8 0.8 2.4 4.0
f = 125 MHz
VCC = 3.3V
TA = 25°C
VID = 200 mV
RECEIVER PROPAGATION DELAY (tPHLD) (ns)
INPUT COMMON MODE VOLTAGE (V)
TYPE 2
TYPE 1
90
75
60
45
30
15
00 25 50 75 100 125
f = 125 MHz
VCC = 3.3V
TA = 25°C
DE0,1,2,3 = L
RE*0,1,2,3 = L
RECEIVER POWER SUPPLY CURRENT (mA)
FREQUENCY (MHz)
3.8
3.5
3.2
2.9
2.6
2.3
2.0
-4.0 -2.4 -0.8 0.8 2.4 4.0
f = 125 MHz
VCC = 3.3V
TA = 25°C
VID = 200 mV
RECEIVER PROPAGATION DELAY (tPLHD) (ns)
INPUT COMMON MODE VOLTAGE (V)
TYPE 2
TYPE 1
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Typical Performance Characteristics (continued)
Figure 22. Receiver Power Supply Current as a Function of Figure 23. Receiver Propagation Delay (tPLHD) as a
Frequency Function of Input Common Mode Voltage
Figure 24. Receiver Propagation Delay (tPHLD) as a Function of Input Common Mode Voltage
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REVISION HISTORY
Changes from Revision L (April 2013) to Revision M Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS91M040TSQ/NOPB WQFN RTV 32 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
DS91M040TSQE/NOPB WQFN RTV 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
DS91M040TSQX/NOPB WQFN RTV 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS91M040TSQ/NOPB WQFN RTV 32 1000 210.0 185.0 35.0
DS91M040TSQE/NOPB WQFN RTV 32 250 210.0 185.0 35.0
DS91M040TSQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-May-2017
Pack Materials-Page 2
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PACKAGE OUTLINE
C
5.15
4.85
5.15
4.85
0.8
0.7
0.05
0.00
2X 3.5
28X 0.5
2X 3.5
32X 0.5
0.3
32X 0.30
0.18
3.1 0.1
(0.1) TYP
WQFN - 0.8 mm max heightRTV0032A
PLASTIC QUAD FLATPACK - NO LEAD
4224386/B 04/2019
0.08 C
0.1 C A B
0.05
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
PIN 1 INDEX AREA
SEATING PLANE
PIN 1 ID
SYMM
EXPOSED
THERMAL PAD
SYMM
1
8
916
17
24
25
32
33
SCALE 2.500
A
B
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EXAMPLE BOARD LAYOUT
28X (0.5)
(1.3)
(1.3)
(R0.05) TYP
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
32X (0.6)
32X (0.24)
(4.8)
(4.8)
(3.1)
(3.1)
( 0.2) TYP
VIA
WQFN - 0.8 mm max heightRTV0032A
PLASTIC QUAD FLATPACK - NO LEAD
4224386/B 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SYMM
SYMM
SEE SOLDER MASK
DETAIL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
1
8
916
17
24
25
32
33
METAL EDGE
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED) SOLDER MASK DEFINED
SOLDER MASK DETAILS
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EXAMPLE STENCIL DESIGN
32X (0.6)
32X (0.24)
28X (0.5)
(4.8)
(4.8)
(0.775) TYP
(0.775) TYP
4X (1.35)
4X (1.35)
(R0.05) TYP
WQFN - 0.8 mm max heightRTV0032A
PLASTIC QUAD FLATPACK - NO LEAD
4224386/B 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SYMM
SYMM
1
8
916
17
24
25
32
33
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