ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
Austin Semiconductor, Inc.
32Mx72 DDR SDRAM
iNTEGRA TED Plastic Encapsulated Microcircuit
FEATURES
DDR SDRAM Data Rate = 200, 250, 266, 333Mbps
Package:
•219 Plastic Ball Grid Array (PBGA), 32 x 25mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture
(one per byte)
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Industrial, Enhanced and Military Temperature
Ranges
Organized as 32M x 72/80
Weight: AS4DDR32M72PBG </= 3.10 grams typical
* This product and or it’s specifications is subject to change without notice.
BENEFITS
40% SP ACE SA VINGS
Reduced part count
Reduced I/O count
•34% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
O
P
T
I
O
N
S
Area
I/O
Count
11.9
Monolithic Solution
11.911.911.9
5 x 265mm2 = 1328mm2 Plus
5 x 66 pins = 320 pins
11.9
32
25
Integrated MCP Solution
S
A
V
I
N
G
S
22.3
800mm2 40+%
219 Balls 34 %
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
Austin Semiconductor, Inc.
SDRAM-DDR PINOUT TOP VIEW
DQ0 DQ14 DQ15 VSS VSS A9 A10 A11 A8 VCCQ VCCQ DQ16 DQ17 DQ31 VSS
DQ1 DQ2 DQ12 DQ13 VSS VSS A0 A7 A6 A1 VCC VCC DQ18 DQ19 DQ29 DQ30
DQ3 DQ4 DQ10 DQ11 VCC VCC A2 A5 A4 A3 VSS VSS DQ20 DQ21 DQ27 DQ28
DQ6 DQ5 DQ8 DQ9 VCCQ VSSQ A12 DNU DNU DNU VSS VSS DQ22 DQ23 DQ26 DQ25
DQ7 DQML0 VCC DQMH0 DQSH3 DQSL0 DQSH0 BA0 BA1 DQSL1 DQSH1 VREF DQML1 VSS NC DQ24
CA S0\ WE0\ VCC CLK0 DQSL3 RAS1\ WE1\ VSS DQMH1 CLK1
CS0\ RAS0\ VCC CKE0 CLKO\ CAS1\ CS1\ VSS CLK1\ CKE1
VSS VSS VCC VCCQ VSS VCC VSS VSS VCCQ VCC
VSS VSS VCC VCCQ VSS VCC VSS VSS VCCQ VCC
CLK3\ CKE3 VCC CS3\ DQSL4 CLK2\ CKE2 VSS RAS2\ CS2\
NC CLK3 VCC CAS3\ RAS3\ DQSL2 CLK2 VSS WE2\ CAS2\
DQ56 DQMH3 VCC WE3\ DQML3 CKE4 DQMH4 CLK4 CAS4\ WE4\ RAS4\ CS4\ DQMH2 VSS DQML2 DQ39
DQ57 DQ58 DQ55 DQ54 DQSH4 CLK4\ DQ73 DQ72 DQ71 DQ70 DQML4 DQSH2\ DQ41 DQ40 DQ37 DQ38
DQ60 DQ59 DQ53 DQ52 VSS VSS DQ75 DQ74 DQ69 DQ68 VCC VCC DQ43 DQ42 DQ36 DQ35
DQ62 DQ61 DQ51 DQ50 VCC VCC DQ77 DQ76 DQ67 DQ66 VSS VSS DQ45 DQ44 DQ34 DQ33
VSS DQ63 DQ49 DQ48 VCCQ VCCQ DQ79 DQ78 DQ65 DQ64 VSS VSS DQ47 DQ46 DQ32 VCC
Ground Array Power D/Q Power Address Data IO
CNTRL Address/DNU UNPOPULATED
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
CLK1
CLK1\
CKE1
CS1\
WE1\
RAS1\
CAS1\
DQML1
DQMH1
DQSL1
DQSH1
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
CLK0
CLK0\
CKE0
CS0\
WE0\
RAS0\
CAS0\
DQML0
DQMH0
DQSL0
DQSH0
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
CLK2
CLK2\
CKE2
CS2\
WE2\
RAS2\
CAS1\
DQML2
DQMH2
DQSL2
DQSH2
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
CLK3
CLK3\
CKE3
CS3\
WE3\
RAS3\
CAS3\
DQML3
DQMH3
DQSL3
DQSH3
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
CLK4
CLK4\
CKE4
CS4\
WE4\
RAS4\
CAS4\
DQML4
DQMH4
DQSL4
DQSH4
DDR
SDRAM
X16
2.5v Core
2.5v IO
SSTL-2
BA0
BA1
VRef
VCC
VCCQ
VSS
DQ0-15 DQ32-47
DQ16-
31
DQ48-63 DQ64-79
ADDR
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
BGA Locations SYMBOL
E12 VREF SSTL-2 Reference Voltage
A11, A12, D5, D6, H4, H15,
J4, J15, T5, T6 VCCQ I/O Power Supply
A5, A6, A16, B5, B6, C11,
C12, D11, D12, E14, F14,
G14, H1, H2, H5, H13,
H14, J1, J2, J5, J13, J14,
K14, L14, P5, P6, R11.
R12, T1, T11, T12, M14
VSS Ground (Digital)
B11, B12, C5, C6, E3, F3,
G3, H3, H12, H16, J3, J12,
J16, K3, L3, M3, P11, P12,
R5, R6, T16
VCC Core Power Supply
A2, A3, A4, A13, A14, B1,
B2, B3, B4, B13, B14, B15,
B16, C1, C2, C3, C4, C13,
C14, C15, C16, D1, D2, D3,
D4, D13, D14, D15, D16,
E1, E16, M1, M16, N1, N2,
N3, N4, N13, N14, N15,
N16, T2, T3, T4, T13, T14,
T15, N7, N8, N9, N10, P7,
P8, P9, P10, R7, R8, R9,
R10, T7, T8, T9, T10
DQ0-79 Data I/O
Data Stobe: Output with read data, input with write data. DQS is edge-aligned with
read data, centered in write data. It is used to capture data
E6, E7, E10, E11, F5, K5,
L12, N5, N12, E5 DQSLX, DQSHX
DESCRIPTION
CKExG4, G16, K2, K13, M6
Chip Select: CSx\ enables the COMMAND register(s) of each of the five (5) contained
words. All commands are masked with CSx\ is registered HIGH. CSx\ provides for
external bank selection on systems with multiple banks. CSx\ is considered part of the
COMMAND CODE.
CSx\G1, G13, K4, K16, M12
Address Input: Provide the row address for Active commands, and the column address
and auto precharge bit (A10) for READ / WRITE commands to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank or all banks.
The address inputs also provide the op-code during a MODE RESISTER SET
command.
A0-11, A12
E8, E9 BA0, BA1 Bank Address Inputs: BA0, BA1, define which bank an ACTIVE READ, WRITE or
PRECHARGE Command is being applied.
A7, A8, A9, A10, B7, B8,
B9, B10, C7, C8. C9, C10,
D7
F4, F16, G5, G15, K1, K12,
L2, L13, N6, M8 CKx, CKx\
Clock: CKx and CKx\ are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CKx and negative edge of CKx\.
Output data (DQ's and DQS) is referenced to the crossings of the differential clock
inputs.
G4, G16, K2, K14, M7
RASx\, CASx\,
Wex\
F4, F16, G5, G15, K1, K12,
L2, L13, N7, M9
Clock Enable: CKE controls the clock inputs. CKE high enables, CKE Low disables
the clock input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE
is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry CKE
is Asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input buffers are disabled
during POWER-DOWN Input buffers are disabled during SELF REFRESH. CKE is an
SSTL-2 input but will detect an LVCMOS LOW level after VCC is applied
Command Inputs: RASx, CASx and Wex\ define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DQMLx or Hx is sampled HIGH at time of a WRITE access. DM is sampled on both
edges of DQSLx and DQSHx.
DQMLx, DQMHx
PIN DEFINITIONS / FUNCTIONAL DESCRIPTION
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The 2.4Gb DDR SDRAM MCM, is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip’s 134,217,728-bit banks
is organized as 8,192 rows by 1024 columns by 32 bits.
The 256MB(2.4Gb) DDR SDRAM MCM uses a DDR
architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 256MB DDR SDRAM effectively consists of a single 2n-
bit wide, one-clock-cycle data tansfer at the internal DRAM
core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
and by the memory contoller during WRITEs. DQS is
edgealigned with data for READs and center-aligned with
data for WRITEs. Each chip has two data strobes, one for
the lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CLK and CLK#); the crossing of CLK going HIGH and CLK#
going LOW will be referred to as the positive edge of CLK.
Commands (address and control signals) are registered at
every positive edge of CLK. Input data is registered on both
edges of DQS, and output data is referenced to both edges
of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed. The address bits registered coincident with the
READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or
WRITE burst lengths of 2, 4, or 8 locations. An auto precharge
function may be enabled to provide a selftimed row
precharge that is initiated at the end of the burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a powersaving
power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed (BA0 and BA1 select the bank, A0-12 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering
device initialization, register defi nition, command descriptions
and device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. Power must first
be applied to VCC and VCCQ simultaneously, and then to VREF
(and to the system VTT). VTT must be applied after VCCQ to
avoid device latch-up, which may cause permanent damage
to the device. VREF can be applied any time after VCCQ but is
expected to be nominally coincident with VTT. Except for CKE,
inputs are not recognized as valid until after VREF is applied.
CKE is an SSTL_2 input but will detect an L VCMOS LOW level
after VCC is applied. Maintaining an LVCMOS LOW level on
CKE during powerup is required to ensure that the DQ and
DQS outputs will be in the High-Z state, where they will remain
until driven in normal operation (by a read access). After all
power supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior to
applying an executable command.
Once the 200µs delay has been satisfied, a DESELECT or
NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE
ALL command should be applied. Next a LOAD MODE
REGISTER command should be issued for the extended
mode register (BA1 LOW and BA0 HIGH) to enable the DLL,
followed by another LOAD MODE REGISTER command to
the mode register (BA0/ BA1 both LOW) to reset the DLL and
to program the operating parameters. Two-hundred clock
cycles are required between the DLL reset and any READ
command. A PRECHARGE ALL command should then be
applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed (tRFC must be satisfi ed.) Additionally, a LOAD
MODE REGISTER command for the mode register with the
reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required. Following
these requirements, the DDR SDRAM is ready for normal
operation.
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
Austin Semiconductor, Inc.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, and
an operating mode, as shown in Figure 3. The Mode Register
is programmed via the MODE REGISTER SET command
(with BA0 = 0 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses
power. (Except for bit A8 which is self clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are idle
and no bursts are in progress, and the controller must wait
the specified time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation. Mode register bits A0-A2 specify the
burst length, A3 specifies the type of burst (sequential or
interleaved), A4-A6 specify the CAS latency, and A7-A12
specify the operating mode.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable, as
shown in Figure 3. The burst length determines the maximum
number of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4 or 8
locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the
burst length is set to two; by A2-Ai when the burst length is
set to four (where Ai is the most significant column address
for a given configuration); and by A3-Ai when the burst length
is set to eight. The remaining (least significant) address
bit(s) is (are) used to select the starting location within the
block. The programmed burst length applies to both READ
and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3. The ordering of accesses
within a burst is determined by the burst length, the burst
type and the starting column address, as shown in Table 1.
TABLE 1 - BURST DEFINITION
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block;
A0 selects the starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block;
A0-1 select the starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block;
A0-2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
T
y
pe = Sequential T
y
pe = Interleaved
A0
0 0-1 0-1
1 1-0 1-0
A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Order of Accesses Within a Burst
2
4
8
Burst
Length
Starting Column
Address
READ LATENCY
The READ latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first bit of output data. The latency can be set to 2 or 2.5
clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
TABLE 2 - CAS LATENCY
CAS CAS
LATENCY=2 LATENCY=2.5
-10 75 100
-8 100 125
-75 100 133
-6 100 166
ALLOWABLE OPERATING
FREQUENCY (MHz)
SPEED
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
Austin Semiconductor, Inc.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to zero,
and bits A0-A6 set to the desired values. A DLL reset is initiated
by issuing a MODE REGISTER SET command with bit s A7 and
A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to
the desired values. Although not required, JEDEC specifications
recommend when a LOAD MODE REGISTER command is
issued to reset the DLL, it should always be followed by a
LOAD MODE REGISTER command to select normal operating
mode.
All other combinations of values for A7-A12 are reserved for
future use and/or test modes. Test modes and reserved states
should not be used because unknown operation or
incompatibility with future versions may result.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions are
DLL enable/disable, output drive strength, and QFC#. These
functions are controlled via the bits shown in Figure 3. The
extended mode register is programmed via the LOAD MODE
REGISTER command to the mode register (with BA0 = 1 and
BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power. The enabling of
the DLL should always be followed by a LOAD MODE
REGISTER command to the mode register (BA0/BA1 both LOW)
to reset the DLL.
The extended mode register must be loaded when all banks
are idle and no bursts are in progress, and the controller must
wait the specified time before initiating any subsequent
operation. Violating either of these requirements could result
in unspecified operation.
BA
1
BA
0
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
Burst LengthBT
Operating Mode
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
0*
0*
CAS Latency
* M14 and M13
mode register).
Mode Register (Mx)
M2 M1 M0 M3 = 0 M3 = 1
0 0 0 Reserved Reserved
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved Reserved
Burst Length
0
1
Sequential
Interleaved
M3 Burst Type
CAS Latency
M6 M5 M4
Reserved
0 00
Reserved
0 0 1
2
0 1 0
Reserved
0 1 1
Reserved
1 0 0
Reserved
1 0 1
2.5
1 1 0
Reserved
1 1 1
M12 M11 M10 M9 M8 M7 M6-M0
Operating Mode
0 0 0 0 0 0 Valid
Normal Operation
0 0 0 0 1 0 idVal Normal Operation/Reset DLL
------ -All other states reserved
FIGURE 1 - MODE BURST DEFINITION
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
Austin Semiconductor, Inc.
T0 T1 T2 T2n T3 T3n
COMMAND
DQS
DQ
T0 T1 T2 T2n T3 T3n
COMMAND
READ NOP NOP NOP
CL = 2
CLK
CLK
READ NOP NOP NOP
DQ
DQS
CLK
CLK
CL = 2.5
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
DATA
DON'T CARE
TRANSITIONING DATA
BA
1
BA
0
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
DLLDS
Operating Mode
11
01
QFC#
Extended Mode
Register (Ex)
DLL
Enable
Disable
E0
0
1
Drive Strength
Normal
Reduced
E1
0
1
QFC# Function
Disabled
Reserved
E22
0
-
Operating Mode
Reserved
Reserved
E2, E1, E0
Valid
-
E12
0
-
E10
0
-
E9
0
-
E8
0
-
E7
0
-
E6
0
-
E5
0
-
E4
0
-
E3
0
-
0
-
E11
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFE# function is not supported.
FIGURE 2 - CAS LATENCY FIGURE 3 - EXTENDED MODE REGISTER
DEFINITION
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM supports an option for
reduced drive. This option is intended for the support of the
lighter load and/or point-to-point environments. The selection
of the reduced drive strength will alter the DQs and DQSs
from SSTL2, Class II drive strength to a reduced drive strength,
which is approximately 54 percent of the SSTL2, Class II
drive strength.
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL enable
is required during power-up initialization and upon returning
to normal operation after having disabled the DLL for the
purpose of debug or evaluation. (When the device exits self
refresh mode, the DLL is enabled automatically.) Any time
the DLL is enabled, 200 clock cycles must occur before a
READ command can be issued.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command.
DESELECT
The DESELECT function (CS# HiGH) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a
NOP to the selected DDR SDRAM (CS# is LOW). This
prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not
affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on
the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0-12 selects the row. This row remains
active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE command
must be issued before opening a different row in the same
bank.
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
Austin Semiconductor, Inc.
NAME (FUNCTION) CS# RAS# CAS# WE#
A
DDR
DESELECT (NOP)(9) H XXXX
NO OPERATION (NOP) (9) L H H H X
ACTIVE (Select bank and activate row) (3) L L H H Bank/Row
READ (Select bank and column, and start READ burst) (4) L H L H Bank/Col
WRITE (Select bank and column, and start WRITE burst) (4) L H L L Bank/Col
BURST TERMINATE (8) L H H L X
PRECHARGE (Deactivate row in bank or banks) (5) L L H L Code
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6,7) L L L H X
LOAD MODE REGISTER (2) LLLLOp-Code
TRUTH TABLE - DM OPERATION
NAME (FUNCTION) DM DQs
WRITE ENABLE (10) L Valid
WRITE INHIBIT (10) H X
TRUTH TABLE - COMMANDS (NOTE 1)
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register.
BA0, BA1 select either the mode register (0, 0) or the extended mode
register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-8 provide column address; A10 HIGH enables the auto precharge
feature (non-persistent), while A10 LOW disables the auto precharge
feature; BA0, BA1 provide bank address.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH:
All banks precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if
CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are
“Don’t Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command
is undefined (and should not be used) for READ bursts with auto
precharge enabled and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding
data.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 input s
selects the bank, and the address provided on inputs A0-
9 selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ burst;
if AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 input s
selects the bank, and the address provided on inputs A0-
9 selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the WRITE
burst; if AUTO PRECHARGE is not selected, the row will
remain open for subsequent accesses. Input data
appearing on the D/Qs iswritten to the memory array
subject to the DQM input logic level appearing coincident
with the data. If a given DQM signal is registered LOW, the
corresponding data will be written to memory; if the DQM
signal is registered HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is
issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in
the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being
issued to that bank. A PRECHARGE command will be
treated as a NOP if there is no open row in that bank (idle
state), or if the previously open row is already in the process
of precharging.
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
Austin Semiconductor, Inc.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above, but
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specific READ or WRITE command. A precharge of
the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of
the READ or WRITE burst. AUTO PRECHARGE is
nonpersistent in that it is either enabled or disabled for each
individual READ or WRITE command. The device supports
concurrent auto precharge if the command to the other bank
does not interrupt the data transfer to the current bank.
AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. This “earliest valid
stage” is determined as if an explicit precharge command
was issued at the earliest possible time, without violating
tRAS (MIN).The user must not issue another command to the
same bank until the precharge time (tRP) is completed. This
is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, without violating tRAS
(MIN).
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ
bursts (with auto precharge disabled). The most recently
registered READ command prior to the BURST TERMINATE
command will be truncated. The open page which the READ
burst was terminated from remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command is
nonpersistent, so it must be issued each time a refresh is
required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an AUT O REFRESH command. Each DDR SDRAM requires
AUTO REFRESH cycles at an average interval of 7.8125µs
(maximum).
To allow for improved efficiency in scheduling and switching
between tasks, some flexibility in the absolute refresh interval
is provided. A maximum of eight AUTO REFRESH commands
can be posted to any given DDR SDRAM, meaning that the
maximum absolute interval between any AUTO REFRESH
command and the next AUTO REFRESH command is 9 x
7.8125µs (70.3µs). This maximum absolute interval is to
allow future support for DLL updates internal to the DDR
SDRAM to be restricted to AUTO REFRESH cycles, without
allowing excessive drift in tAC between updates.
Although not a JEDEC requirement, to provide for future
functionality features, CKE must be active (High) during the
AUTO REFRESH period. The AUT O REFRESH period begins
when the AUT O REFRESH command is registered and ends
tRFC later.
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the DDR SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the DDR SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). The DLL is automatically
disabled upon entering SELF REFRESH and is automatically
enabled upon exiting SELF REFRESH (200 clock cycles must
then occur before a READ command can be issued). Input
signals except CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable prior to CKE going
back HIGH. Once CKE is HIGH, the DDR SDRAM must have
NOP commands issued for tXSNR, because time is required
for the completion of any internal refresh in progress. A
simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for 200 clock cycles before
applying any other command.
* Self refresh available in commercial and industrial temperatures only.
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
Austin Semiconductor, Inc.
Paramete
r
Unit
Voltage on V
CC
, V
CCQ
Supply relative to V
SS
-1 ot 3.6 V
Voltage on I/O pins relative to V
SS
-1 ot 3.6 V
Operating Temperature T
A
(Mil) -55 to +125
o
C
Operating Temperature T
A
(Ind) -40 to +85
o
C
Storage Temperature, Plastic -55 to +150
o
C
Note: Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE (NOTE 13)
Paramete
r
Symbol Max Unit
Input Capacitance: CLK C
11
8pF
Addresses, BA0-1 Input Capacitance CA 30 pF
Input Capacitance: All other input-only pins C
12
9pF
Input/Output Capacitance: I/O's C
10
12 pF
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
Austin Semiconductor, Inc.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1,6)
VCC, VCCQ = +2.5V ± 0.2V ; -55oC ± 0.2V, -55oC T A +125oC
AC INPUT OPERATING CONDITIONS (NOTES 1,6)14, 28, 40
VCC, VCCQ = +2.5V ± 0.2V ; -55oC ± 0.2V, -55oC T A +125oC
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14)
VCC, VCCQ = +2.5V ± 0.2V ; -55oC ± 0.2V, -55oC T A +125oC
Parameter / Condition Symbol Min Max Units
Supply Voltage VCC 2.3 2.7 V
I/O Supply Voltage VCCQ 2.3 2.7 V
Input Leakage Current: Any input 0V VIN VCC (All other pins not under test = 0V) II-2 2 µA
Input Leakage Address Current (All other pins not under test = 0V) II-10 10 µA
Output Leakage Current: I/O's are disabled; 0V VOUT VCC IOZ -5 5 µA
Output Levels: Full drive option
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)IOL 12 - mA
Output Levels: Reduced drive option
High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)IOLR 9-mA
I/O Reference Voltage (6) VREF 0.49 x VCCQ 0.51 x VCCQ V
I/O Termination Voltage (53) VTT VREF - 0.04 VREF + 0.04 V
mA
-9 - mA
IOH
IOHR
-12 -
Parameter / Condition Symbol Min Max Units
Input High (Logic 1) Voltage: V
IH
(AC) V
REF
+ 0.310 -V
Input Low (Logic ) Voltage: V
IL
(AC) -V
REF
- 0.310 V
333, 266
250 Mbps
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; t
CK
=t
CK
(MIN); CKE=LOW; (23, 32. 50) I
CC2P
20 20 mA
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; t
CK
=t
CK
(MIN); CKE=LOW (23, 32, 50) I
CC3P
150 150 mA
I
CC5
1225 1225 mA
I
CC5A
30 30 mA
SELF REFRESH CURRENT: CKE 0.2V I
CC6
20 20 mAStandard (11)
Parameter / Condition
t
REF
=t
RC
(MIN) (27, 50)
t
REF
=7.8125 µs (27, 50)
AUTO REFRESH CURRENT
IDLE STANDBY CURRENT: CS#=HIGH, All banks idle; t
CK
=t
CK
(MIN); CKE=HIGH; Address and other control inputs changing once per clock
cycle. V
IN
=V
REF
for DQ, DQS and DM (51)
ACTIVE STANDBY CURRENT: CS#=HIGH; CKE=HIGH; One bank; Active Precharge; t
RC
=t
RAS
(MAX); t
CK
=t
CK
(MIN); DQ, DM and DQS inputs
changin twicer per clock cycle; Address and other control inputs changing once per clock cycle (22)
OPERATING CURRENT: Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; t
CK
=t
CK
(MIN); I
OUT
=0mA (22,48)
OPERATING CURRENT: Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; t
CK
=t
CK
(MIN); DQ, DM and DQS inputs changin twice per clock cycle (22)
OPERATING CURRENT: Four bank interleaving DEADs (BL=4) with auto precharge, t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); Addresses and control inputs
change only during Active READ or WRITE commands. (22, 49)
I
CC0
I
CC1
I
CC2F
I
CC3N
I
CC4R
I
CC4W
I
CC7
OPERATING CURRENT: One bank, Active-Precharge; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles; (22, 48)
OPERATING CURRENT: One bank, Active-Read- Precharge; Burst=2; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN); I
OUT
= 0mA; Address and control inputs
changing once every two clock cycles; (22, 48)
Units200 Mbps
Max
Symbol
625 600 mA
850 775 mA
225 225 mA
250 250 mA
2000 2000 mA
925 925 mA
800 800 mA
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING
CHARACTERISTICS (NOTES 1-5, 14-17, 33)
Min Max Min Max
t
AC
-0.70 +0.70 -0.75 +0.75 ns
t
CH
0.45 0.55 0.45 0.55 t
CK
t
CL
0.45 0.55 0.45 0.55 t
CK
CL=2.5 (45, 52) t
CK
(2.5) 6 13 7.5 13 ns
CL=2 (45, 52) t
CK
(2) 7.5 13 8 13 ns
t
DH
0.45 0.5 ns
t
DS
0.45 0.5 ns
t
DIPW
1.75 1.75 ns
t
DQSCK
-0.6 +0.6 -0.75 +0.75 ns
tDQSH
0.35 0.35 t
CK
t
DQSL
0.35 0.35 t
CK
t
DQSQ
0.45 0.5 ns
t
DQSS
0.75 1.25 0.75 1.25 t
CK
t
DSS
0.2 0.2 t
CK
t
DSH
0.2 0.2 t
CK
t
HP
t
CH
, t
CL
t
CH
, t
CL
ns
t
HZ
+0.7 +0.75 ns
t
LZ
-0.7 -0.75 ns
t
IHF
0.75 0.9 ns
t
ISF
0.75 0.9 ns
t
IHS
0.8 1.0 ns
t
ISS
0.8 1.0 ns
t
MRD
12 15 ns
t
QH
ns
t
QHS
0.55 1 ns
t
RAS
42 70,000 40 120,000 ns
t
RAP
15 15 ns
t
RC
60 60 ns
t
RFC
72 75 ns
t
RCD
15 15 ns
t
RP
15 15 ns
t
RPRE
0.9 1.1 0.9 1.1 t
CK
t
RPST
0.4 0.6 0.4 0.6 t
CK
t
RRD
12 15 ns
t
WPRE
0.25 0.25 t
CK
t
WPRES
00ns
t
WPST
0.4 0.6 0.4 0.6 t
CK
t
WR
15 15 ns
t
WTR
11
t
CK
NA ns
t
REFC
70.3 70.3 µs
t
REFC
35 35 µs
t
REFI
7.8 7.8 µs
t
REFI
3.9 3.9 µs
t
VTD
00ns
t
XSNR
75 75 ns
t
XSRD
200 200 t
CK
t
QH
- t
DQSQ
t
HP
-t
QHS
t
HP
-t
QHS
t
QH
- t
DQSQ
Symbol
@CL=2.5 [CL=2]
-6, 333 [266] Mbps
Units
-75, 266 [250] Mbps
@CL=2.5 [CL=2]
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Clock cycle time
Parameter
REFRESH to REFRESH command interval (Military temp only) (23)
Average periodic refresh interval (Commercial & Industrial temp only) (23)
Average periodic refresh interval (Military temp only) (23)
Terminating voltage delay to Vcc (53)
Write recovery time
Internal WRITE to READ command delay
REFRESH to REFRESH command interval (Commercial & Industrial temp
Active bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20,21)
DQS write postamble (19)
PRECHARGE command period
DQS read preamble (42)
DQS read postamble
Data valid output window (25)
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (50)
ACTIVE to READ or WRITE delay
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
ACTIVE to PRECHARGE command (35)
Address and control input hold time (fast slew rate) (14)
Address and control input setup time (fast slew rate) (14)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
DQS falling edge to CLK rising - hold time
Half clock period (34)
Data-out high-impedance window from CLK/CLK# (18, 42)
Data-out low-impedance window from CLK/CLK# (18, 43)
DQS input high pulse width
DQS-DQ skew, DQS to last valid, per group, per access (25,26)
Write command to first DQS latching transition
DQS falling edge to CLK rising - setup time
DQ and DM input setup time relative to DQS (26,31)
DQ and DM input pulse with (for each input) (31)
Access window of DQS from CLK/CLK#
DQS input high pulse width
Access window of DQs from CLK/CLK#
CLK high-level width (30)
CLK low-level width (30)
DQ and DM input hold time relative to DQS (26, 31)
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
14
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING
CHARACTERISTICS (NOTES 1-5, 14-17, 33)
Min Max Min Max
t
AC
-0.8 +0.8 -0.8 +0.8 ns
t
CH
0.45 0.55 0.45 0.55 t
CK
t
CL
0.45 0.55 0.45 0.55 t
CK
CL=2.5 (45, 52) t
CK
(2.5) 8 131013ns
CL=2 (45, 52) t
CK
(2) 10 13 13 15 ns
t
DH
0.6 0.6 ns
t
DS
0.6 0.6 ns
t
DIPW
22ns
t
DQSCK
-0.8 +0.8 -0.8 +0.8 ns
tDQSH
0.35 0.35 t
CK
t
DQSL
0.35 0.35 t
CK
t
DQSQ
0.6 0.6 ns
t
DQSS
0.75 1.25 0.75 1.25 t
CK
t
DSS
0.2 0.2 t
CK
t
DSH
0.2 0.2 t
CK
t
HP
t
CH
, t
CL
t
CH
, t
CL
ns
t
HZ
+0.8 +0.8 ns
t
LZ
-0.8 -0.8 ns
t
IHF
1.1 1.1 ns
t
ISF
1.1 1.1 ns
t
IHS
1.1 1.1 ns
t
ISS
1.1 1.1 ns
t
MRD
16 16 ns
t
QH
ns
t
QHS
11ns
t
RAS
40 120,000 40 120,000 ns
t
RAP
20 20 ns
t
RC
70 70 ns
t
RFC
80 80 ns
t
RCD
20 20 ns
t
RP
20 20 ns
t
RPRE
0.9 1.1 0.9 1.1 t
CK
t
RPST
0.4 0.6 0.4 0.6 t
CK
t
RRD
15 15 ns
t
WPRE
0.25 0.25 t
CK
t
WPRES
00ns
t
WPST
0.4 0.6 0.4 0.6 t
CK
t
WR
15 15 ns
t
WTR
11
t
CK
NA ns
t
REFC
70.3 70.3 µs
t
REFC
35 35 µs
t
REFI
7.8 7.8 µs
t
REFI
3.9 3.9 µs
t
VTD
00ns
t
XSNR
80 80 ns
t
XSRD
200 200 t
CK
t
QH
-t
DQSQ
t
HP
-t
QHS
t
HP
-t
QHS
t
QH
-t
DQSQ
Symbol
@CL=2.5 [CL=2]
-8, 250 [200] Mbps
Units
-10, 200 [167] Mbps
@CL=2.5 [CL=2]
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Clock cycle time
Parameter
REFRESH to REFRESH command interval (Military temp only) (23)
Average periodic refresh interval (Commercial & Industrial temp only) (23)
Average periodic refresh interval (Military temp only) (23)
Terminating voltage delay to Vcc (53)
Write recovery time
Internal WRITE to READ command delay
REFRESH to REFRESH command interval (Commercial & Industrial temp
Active bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20,21)
DQS write postamble (19)
PRECHARGE command period
DQS read preamble (42)
DQS read postamble
Data valid output window (25)
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (50)
ACTIVE to READ or WRITE delay
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
ACTIVE to PRECHARGE command (35)
Address and control input hold time (fast slew rate) (14)
Address and control input setup time (fast slew rate) (14)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
DQS falling edge to CLK rising - hold time
Half clock period (34)
Data-out high-impedance window from CLK/CLK# (18, 42)
Data-out low-impedance window from CLK/CLK# (18, 43)
DQS input high pulse width
DQS-DQ skew, DQS to last valid, per group, per access (25,26)
Write command to first DQS latching transition
DQS falling edge to CLK rising - setup time
DQ and DM input setup time relative to DQS (26,31)
DQ and DM input pulse with (for each input) (31)
Access window of DQS from CLK/CLK#
DQS input high pulse width
Access window of DQs from CLK/CLK#
CLK high-level width (30)
CLK low-level width (30)
DQ and DM input hold time relative to DQS (26, 31)
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
Austin Semiconductor, Inc.
NOTES:
1. All voltages referenced to VSS.
2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage
range specified.
3. Outputs measured with equivalent load:
4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing
point for CLK/CLK#), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 1V/ns in the range
between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2
Standard (i.e., the receiver will effectively switch as a result of the signal
crossing the AC input level, and will remain in that state as long as the
signal does not ring back above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VCCQ/2 of the transmitting device and to track
variations in the DC level of the same. Peak-to-peak noise (noncommon
mode) on VREF may not exceed ±2 percent of the DC value. Thus, from
VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the nearest VREF by-pass
capacitor.
7. VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. VID is the magnitude of the difference between the input level on CLK and
the input level on CLK#.
9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting
device and must track variations in the DC level of the same.
10. ICC is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle time with the outputs open.
11. Enables on-chip refresh and address counters.
12. ICC specifications are tested after the device is properly initialized, and is
averaged at the defined cycle rate.
13. This parameter is not tested but guaranteed by design. tA = 25OC, f = 1
MHz
14. Command/Address input slew rate = 0.5V/ns. For 266 MHz with slew rates
1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less
than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each
100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added,
that is, it remains constant. If the level, slew rate exceeds 4.5V/ns,
functionality is uncertain.
V
TT
50Ω
Reference
Output
Point
30pF
(V
OUT
)
15. The CLK/CLK# input reference level (for timing referenced to CLK/CLK#)
is the point at which CLK and CLK# cross; the input reference level for
signals other than CLK/CLK# is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the
period before VREF stablizes, CKE < 0.3 x VCCQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference
point indicated in Note 3, is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as valid
data transitions. These parameters are not referenced to a specific voltage
level, but specify when the device output is no longer driving (HZ) or
begins driving (LZ).
19. The maximum limit for this parameter is not a device limit. The device will
operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
20. This is not a device limit. The device will operate with a negative value, but
system performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the
WRITE command. The case shown (DQS going from High-Z to logic LOW)
applies when no WRITEs were previously in progress on the bus. If a
previous WRITE was in progress, DQS could be HIGH during this time,
depending on tDQSS.
22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that
meets the minimum absolute value for the respective parameter. tRAS
(MAX) for ICC measurements is the largest multiple of tCK that meets the
maximum absolute value for tRAS.
23. The refresh period 64ms. This equates to an average refresh rate of
However, an AUTO REFRESH command must be asserted at least once
every 70.3µs; burst refreshing or posting by the DRAM controller greater
than eight refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more
than this maximum amount for any given device.
25. The valid data window is derived by achieving other specifications - tHP
(tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates
directly porportional with the clock duty cycle and a practical data valid
window can be derived. The clock is allowed a maximum duty cycle
variation of 45/55. Functionality is uncertain when operating beyond a
45/55 ratio. The data valid window derating curves are provided
26. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with
DQ8-DQ15 of each chip.
27. This limit is actually a nominal value and does not result in a fail value.
CKE is HIGH below for duty cycles ranging between 50/50 and 45/55.
during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e.,
during standby)
28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the
target AC level, VIL(AC) or VIH(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the
target DC level, VIL(DC) or VIH(DC).
160 0
Maximum
Nominal high
Nominal low
Minimum
Nominal high
Nominal low
Minimum
Maximum
-20
140
-40
120
-60
-80
I
OUT
(mA)
I
OUT
(mA)
-100
-120
-140
40
-160
20 -180
0 -200
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5
V
OUT
(V) V
CCQ -
V
OUT
(V)
100
80
60
FIGURE A - PULL-DOWN CHARACTERISTICS FIGURE B - PULL-UP CHARACTERISTICS
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
Austin Semiconductor, Inc.
29. The Input capacitance per pin group will not differ by more than this
maximum amount for any given device.
30. CLK and CLK# input slew rate must be > 1V/ns (>2V/ns differentially).
31. DQ and DM input slew rates must not deviate from DQS by more than
10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be
derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction
in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain.
32. VCC must not vary more than 4% if CKE is not active while any bank is
active.
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is
allowed to vary by the same amount.
34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to
the device CLK and CLK# inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until
tRAS(MIN) can be satisfied prior to the internal precharge command being
issued.
36. Any positive glitch must be less than 1/3 of the clock and not more than
+400mV or 2.9 volts, whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts,
whichever is more positive.
37. Normal Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines
of the V-I curve of Figure A.
b) The variation in driver pull-down current within nominal limits of voltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines
of the V-I curve of Figure B.
d) The variation in driver pull-up current within nominal limits of voltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up
and pull-down current should be between .71 and 1.4, for device drain-
to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and
temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current
should be unity ¡À10%, for device drain-to-source voltages from 0.1V
to 1.0 Volt.
38. Reduced Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines
of the V-I curve of Figure C.
b) The variation in driver pull-down current within nominal limits of voltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure C.
c) The full variation in driver pull-up current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines
of the V-I curve of Figure D.
d) The variation in driver pull-up current within nominal limits of voltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up
and pull-down current should be between .71 and 1.4, for device drain-
to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and
temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current
should be unity ±10%, for device drain-to-source voltages from 0.1V
to 1.0 Volt.
39. The voltage levels used are derived from a minimum VCC level and the
referenced test load. In practice, the voltage levels obtained from a
properly terminated bus will provide significantly different voltage values.
40. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width < 3ns and the
pulse width can not be greater than 1/3 of the cycle rate.
41. VCC and V CCQ must track each other.
42. This maximum value is derived from the referenced test load. In practice,
the values obtained in a typical terminated design may reflect up to
310ps less for tHZ(MAX) and the last DVW. tHZ(MAX) will prevail over
tDQSCK(MAX) + tRPST(MAX) condition. tLZ(MIN) will prevail over tDQSCK(MIN)
+ tRPRE(MAX) condition.
43. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps
earlier.
44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC
+ 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even
if VCC/VCCQ are 0 volts, provided a minimum of 42 ohms of series
resistance is used between the VTT supply and the input pin.
45. The current part operates below the slowest JEDEC operating frequency
of 83 MHz. As such, future die may not reflect this option.
46. Reserved for future use.
47. Reserved for future use.
48. Random addressing changing 50% of data changing at every transfer.
49. Random addressing changing 100% of data changing at every transfer.
50. CKE must be active (high) during the entire time a refresh command is
executed. That is, from the time the AUTO REFRESH command is
registered, CKE must be active at each rising clock edge, until tRFC has
been satisfied.
51. ICC2N specifies the DQ, DQS, and DM to be driven to a valid high or low
logic level. ICC2Q is similar to ICC2F except ICC2Q specifies the address
and control inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are
similar, ICC2F is “worst case.”
52. Whenever the operating frequency is altered, not including jitter, the DLL
is required to be reset. This is followed by 200 clock cycles before any
READ command.
53. VTT is not applied directly to the device; however, tVTD should be greater
than or equal to zero to avoid device latch-up. VCCQ, VTT and VREF must
be equal to or less than VCC + 0.3V. Alternatively VTT may be 1.35V max
during power-up even if VCC/VCCQ are 0V, provided a minimum of 42 &! of
series resistance is used between the VTT supply and the input pin. Once
initialized, VREF must always be powered within the specified range.
80 0
Nominal low
Minimum
Maximum
Nominal high
Maximum
Nominal high
Nominal low
Minimum
-10
70
-20
60
-30
50
I
OUT
(mA)
-40
I
OUT
(mA)
40
-50
30
-60
20
-70
10
-80
0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5
V
OUT
(V) V
CCQ -
V
OUT
(V)
FIGURE C - PULL-DOWN CHARACTERISTICS FIGURE D - PULL-UP CHARACTERISTICS
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
Austin Semiconductor, Inc.
32.1 (1.264) MAX
1 2 3 4 5 6 7 8 9
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
25.1
(0.988)
MAX
0.61
(0.024)
NOM
2.03 (0.080)
MAX
19.05 (0.750) NOM
1.27
(0.050)
NOM
19.05
(0.750)
NOM
219 X Ø 0.762 (0.030) NOM
Bottom View
10 11 12 13 14 15 16
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA)
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18
Austin Semiconductor, Inc.
ORDERING INFORMATION
Part Numbe
r
Core Freq. Data Transfer Rate Package Process
AS4DDR32M72-6/IT 166 MHz 333 Mbps 219-PBGA Industrial
AS4DDR32M72-75/IT 133 MHz 266 Mbps 219-PBGA Industrial
AS4DDR32M72-8/IT 125 MHz 250 Mbps 219-PBGA Industrial
AS4DDR32M72-10/IT 100 MHz 200 Mbps 219-PBGA Industrial
AS4DDR32M72-75/ET 133 MHz 266 Mbps 219-PBGA Enhanced
AS4DDR32M72-8/ET 125 MHz 250 Mbps 219-PBGA Enhanced
AS4DDR32M72-10/ET 100 MHz 200 Mbps 219-PBGA Enhanced
AS4DDR32M72-75/XT 133 MHz 266 Mbps 219-PBGA Extended
AS4DDR32M72-8/XT 125 MHz 250 Mbps 219-PBGA Extended
AS4DDR32M72-10/XT 100 MHz 200 Mbps 219-PBGA Extended
ii
ii
iPEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4Gb SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.0 09/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
19
Austin Semiconductor, Inc.
DOCUMENT TITLE
32M x 72 DDR SDRAM Multi-Chip Packaged in a 32mm x 25mm - 219 PBGA
REVISION HISTORY
Rev # History Release Date Status
1.0 RELEASE March 2005 Preliminary
