LF198QML www.ti.com SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 LF198QML Monolithic Sample-and-Hold Circuits Check for Samples: LF198QML FEATURES DESCRIPTION * * * * * * * * The LF198 is a monolithic sample-and-hold circuit which utilizes BI-FET technology to obtain ultra-high dc accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, dc gain accuracy is 0.002% typical and acquisition time is as low as 6 s to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide bandwidth allows the LF198 to be included inside the feedback loop of 1 MHz op amps without having stability problems. Input impedance of 1010 allows high source impedances to be used without degrading accuracy. 1 2 * * Operates from 5V to 18V supplies Less than 10 s acquisition time TTL, PMOS, CMOS compatible logic input 0.5 mV typical hold step at Ch = 0.01 F Low input offset 0.002% gain accuracy Low output noise in hold mode Input characteristics do not change during hold mode High supply rejection ratio in sample or hold Wide bandwidth P-channel junction FET's are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1 F hold capacitor. The JFET's have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design specifies no feed-through from input to output in the hold mode, even for input signals equal to the supply voltages. Logic inputs on the LF198 are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS. Differential threshold is 1.4V. The LF198 will operate from 5V to 18V supplies. Connection Diagrams Figure 1. Small-Outline Package (CGLA) See Package Number NAC0014A Figure 2. Metal Can Package (TO-99) See Package Number LMC0008C 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005-2013, Texas Instruments Incorporated LF198QML SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Typical Connection and Performance Curve Figure 3. Figure 4. Acquisition Time Functional Diagram 2 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML LF198QML www.ti.com SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 Absolute Maximum Ratings (1) Supply Voltage 18V Power Dissipation (Package Limitation) (2) 500 mW Operating Ambient Temperature Range -55C to +125C Maximum Junction Temperature (TJmax) +150C Input Voltage Equal to Supply Voltage Logic To Logic Reference Differential Voltage (3) +7V, -30V Output Short Circuit Duration Indefinite Hold Capacitor Short Circuit Duration 10 sec Lead Temperature (Soldering, 10 sec.) 260C Thermal Resistance, JA Metal Can (Still Air at 0.5W) 160C/W Metal Can (500 LF/Min Air at 0.5W) 84C/W Ceramic SOIC (Stil Air at 0.5W) 140C/W Ceramic SOIC (500 LF/Min Air Flow at 0.5W) 95C/W JC Metal Can 48C/W Ceramic SOIC 20C/W Package Weight (typical) Metal Can TBD Ceramic SOIC ESD Tolerance (1) (2) (3) (4) 415mg (4) 500V "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For specifications and test conditions, see the Electrical Characteristics. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX - TA)/JA, or the number given in the Absolute Maximum Ratings, whichever is lower. . Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the negative supply. Human body model, 100pF discharged through 1.5K Quality Conformance Inspection Mil-Std-883, Method 5005 -- Group A Subgroup Description Temperature (C) 1 Static tests at +25C 2 Static tests at +125C 3 Static tests at -55C 4 Dynamic tests at +25C 5 Dynamic tests at +125C 6 Dynamic tests at -55C 7 Functional tests at +25C 8A Functional tests at +125C 8B Functional tests at -55C 9 Switching tests at +25C 10 Switching tests at +125C 11 Switching tests at -55C Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML 3 LF198QML SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Electrical Characteristics The following specifications apply unless otherwise specified. VCC = 15V, RL = 10K, VIN = 0V, CHOLD = 0.01 F, Logic Reference Pin = 0V, Logic Pin = 4V Symbol ICC+ Parameter Positive Supply Current Conditions Notes Max Unit Subgroups 5.5 mA 1, 2 6.5 mA 3 5.5 mA 1, 2 6.5 mA 3 5.5 mA 1, 2 6.5 mA 3 -5.5 mA 1, 2 Min +VCC = 15V, -VCC = -15V +VCC = 18V, -VCC = -18V, Mode = "Sample" +VCC = 18V, -VCC = -18V, Mode = "Hold" ICC- Negative Supply Current VOS Input Offset Voltage +VCC = 15V, -VCC = -15V -6.5 mA 3 +VCC = 18V, -VCC = -18V, Mode = "Sample" -5.5 mA 1, 2 -6.5 mA 3 +VCC = 18V, -VCC = -18V, Mode = "Hold" -5.5 mA 1, 2 -6.5 mA 3 +VCC = 3V, -VCC = -7V +VCC = 15V, -VCC = -15V +VCC = 3.5V, -VCC = -26.5V +VCC = 18V, -VCC = -18V +VCC = 3.5V, -VCC = -32.5V +VCC = 26.5V, -VCC = -3.5V +VCC = 32.5V, -VCC = -3.5V, Logic = 2.5V +VCC = 7V, -VCC = -3V IIB Input Bias Current +VCC = 3V, -VCC = -7V +VCC = 15V, -VCC = -15V +VCC = 3.5V, -VCC = -32.5V +VCC = 32.5V, -VCC = -3.5V +VCC = 7V, -VCC = -3V ILeak(Cap) Leakage Current into Hold Capacitor +VCC = 3V, -VCC = -7V +VCC = 7V, -VCC = -3V 4 (1) +VCC = 3.5V, -VCC = -32.5V +VCC = 32.5V, -VCC = -3.5V (1) See See (1) -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 -3.0 3.0 mV 1 -5.0 5.0 mV 2, 3 -25 25 nA 1 -75 75 nA 2, 3 -25 25 nA 1 -75 75 nA 2, 3 -25 25 nA 1 -75 75 nA 2, 3 -25 25 nA 1 -75 75 nA 2, 3 -25 25 nA 1 -75 75 nA 2, 3 -100 100 pA 1 -100 100 pA 1 -100 100 pA 1 -100 100 pA 1 Leakage current is measured at a junction temperature of 25C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25C value for each 11C increase in chip temperature. Leakage is specified over full input signal range. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML LF198QML www.ti.com SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 Electrical Characteristics (continued) The following specifications apply unless otherwise specified. VCC = 15V, RL = 10K, VIN = 0V, CHOLD = 0.01 F, Logic Reference Pin = 0V, Logic Pin = 4V Symbol VHS Parameter Hold Step Conditions +VCC = 15V -VCC = -15V +VCC = 3.5V, -VCC = -26.5V +VCC = 26.5V, -VCC = -3.5V AE Gain Error Notes See (2) See (2) See (2) Max Unit -2.0 2.0 mV 1 -5.6 5.6 mV 2, 3 -2.5 2.5 mV 1 -5.6 5.6 mV 2, 3 -2.5 2.5 mV 1 -5.6 5.6 mV 2, 3 0.02 % 1 0.06 % 2, 3 0.00 5 % 1 0.02 % 2, 3 0.00 5 % 1 0.06 % 2, 3 0.00 5 % 1 +VCC = 7V, -VCC = -3V +VCC = 3.5V, -VCC = -26.5V +VCC = 32.5V, -VCC = -3.5V +VCC = 26.5V, -VCC = -3.5V 0.02 ZI Input Impedance +VCC = 8V, -VCC = -28V +VCC = 28V, -VCC = -8V ZO Output Impedance ICharge Capacitor Charging Current +VCC = 28V, -VCC = -8V Logic Logic Pin Current % 2, 3 10.0 G 1 2, 3 0.8 G 10.0 G 1 0.8 G 2, 3 2.0 1 4.0 2, 3 -25 -4.5 mA 1 -25 -3.0 mA 2, 3 4.5 25 mA 1 3.0 25 mA 2, 3 10 A 1, 2, 3 1.0 A 1 0.5 A 2, 3 -3.5 3.5 mV 1 -6.0 6.0 mV 2, 3 -1.1 1.1 mV 1 +VCC = 18V, -VCC = -18V +VCC = 8V, -VCC = -28V +VCC = 18V, -VCC = -18V, Mode = "Sample", Logic = 7V +VCC = 18V, -VCC = -18V, Mode = "Hold", Logic = -30V VOS Input Offset Voltage +VCC = 15V, -VCC = -15V, IDrive = +1mA Subgroups Min Delta VOS Input Offset Voltage -2.0 2.0 mV 2, 3 IOS+ Output Short Circuit Current +VCC = 18V, -VCC = -18V 7.0 20 mA 1 IOS- Output Short Circuit Current +VCC = 18V, -VCC = -18V -25 -7.0 mA 1 ILogicRef Logic Reference Pin Current +VCC = 18V, -VCC = -18V, Mode = "Sample", Logic = 7V -1.0 1.0 A 1 -0.5 5.0 A 2, 3 10 A 1, 2, 3 +VCC = 15V, -VCC = -15V, IDrive = +1mA to -1mA +VCC = 18V, -VCC = -18V, Mode = "Hold", Logic = -30V (2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step with a 5V logic swing and a 0.01F hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML 5 LF198QML SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) The following specifications apply unless otherwise specified. VCC = 15V, RL = 10K, VIN = 0V, CHOLD = 0.01 F, Logic Reference Pin = 0V, Logic Pin = 4V Symbol PSRR Parameter Conditions Notes Power Supply Rejection Ratio +VCC = 10V, -VCC = -15V +VCC = 15V, -VCC = -10V FTRR Feed Through Rejection Ratio +VCC = 3.5V, -VCC = -32.5V +VCC = 32.5V, -VCC = -3.5V VTH Differential Logic Level VOS (2nd Stg) 2nd Stage VOS Max Unit Subgroups 80 dB 1 74 dB 2, 3 80 dB 1 74 dB 2, 3 86 dB 1 74 dB 2, 3 86 dB 1 dB 2, 3 0.8 74 2.4 V 1 -35 +35 mV 1 -50 +50 mV 2, 3 -35 +35 mV 1 -50 +50 mV 2, 3 -35 +35 mV 1 -50 +50 mV 2, 3 -35 +35 mV 1 -50 +50 mV 2, 3 Max Unit Subgroups Delta VOUT = 10V, CHold = 1000pF 6.0 S 4 Delta VOUT = 10V, CHold = 0.01F 25 S 4 Min Max Unit Subgroups See (3) +VCC = 3.5V, -VCC = -32.5V +VCC = 3V, -VCC = -7V +VCC = 32.5V, -VCC = -3.5V +VCC = 7V, -VCC = -3V (3) Min Parameter tested go no go only for Vth test. AC Parameters The following specifcations apply unless otherwise specified. VCC = 15V, RL = 10K, VIN = 0V, CHold = 0.01 F, Logic Reference Pin = 0V, Logic Pin = 4V Symbol TAQ Parameter Acquisition Time Conditions Notes Min DC Parameters: Drift Values The following conditions apply to all the following parameters, unless otherwise specified. VCC = 15V, RL = 10K, VIN = 0V, CHold = 0.01 F, Logic Reference Pin = 0V, Logic Pin = 4V Deltas required for S-Level product ONLY. Symbol Parameters Conditions Notes VOS Input Offset Voltage +VCC = 15V, -VCC = -15V -0.5 0.5 mV 1 IIB Input Bias Current +VCC = 15V, -VCC = -15V -2.5 2.5 nA 1 6 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML LF198QML www.ti.com SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 Typical Performance Characteristics Aperture Time (See the Definition of Terms) Dielectric Absorption Error in Hold Capacitor Figure 5. Figure 6. Dynamic Sampling Error Output Droop Rate Figure 7. Figure 8. Hold Step "Hold" Settling Time (See the Definition of Terms) Figure 9. Figure 10. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML 7 LF198QML SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 8 Leakage Current into Hold Capacitor Phase and Gain (Input to Output, Small Signal) Figure 11. Figure 12. Gain Error Power Supply Rejection Figure 13. Figure 14. Output Short Circuit Current Output Noise (See the Definition of Terms) Figure 15. Figure 16. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML LF198QML www.ti.com SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Input Bias Current Feedthrough Rejection Ratio (Hold Mode) Figure 17. Figure 18. Hold Step vs Input Voltage Output Transient at Start of Sample Mode Figure 19. Figure 20. Output Transient at Start of Hold Mode Figure 21. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML 9 LF198QML SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Logic Input Configurations TTL & CMOS 3V VLOGIC (Hi State) 7V Threshold = 1.4V Threshold = 1.4V*Select for 2.8V at pin 8 CMOS 7V VLOGIC (Hi State) 15V Threshold = 0.6 (V+) + 1.4V Threshold = 0.6 (V+) - 1.4V Op Amp Drive Threshold +4V 10 Threshold = -4V Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML LF198QML www.ti.com SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 APPLICATION INFORMATION HOLD CAPACITOR Hold step, acquisition time, and droop rate are the major trade-offs in the selection of a hold capacitor value. Size and cost may also become important for larger values. Use of the curves included with this data sheet should be helpful in selecting a reasonable value of capacitance. Keep in mind that for fast repetition rates or tracking fast signals, the capacitor drive currents may cause a significant temperature rise in the LF198. A significant source of error in an accurate sample and hold circuit is dielectric absorption in the hold capacitor. A mylar cap, for instance, may "sag back" up to 0.2% after a quick change in voltage. A long sample time is required before the circuit can be put back into the hold mode with this type of capacitor. Dielectrics with very low hysteresis are polystyrene, polypropylene, and Teflon. Other types such as mica and polycarbonate are not nearly as good. The advantage of polypropylene over polystyrene is that it extends the maximum ambient temperature from 85C to 100C. Most ceramic capacitors are unusable with > 1% hysteresis. Ceramic "NPO" or "COG" capacitors are now available for 125C operation and also have low dielectric absorption. For more exact data, see the curve Dielectric Absorption Error. The hysteresis numbers on the curve are final values, taken after full relaxation. The hysteresis error can be significantly reduced if the output of the LF198 is digitized quickly after the hold mode is initiated. The hysteresis relaxation time constant in polypropylene, for instance, is 10--50 ms. If A-to-D conversion can be made within 1 ms, hysteresis error will be reduced by a factor of ten. DC AND AC ZEROING DC zeroing is accomplished by connecting the offset adjust pin to the wiper of a 1 k potentiometer which has one end tied to V+ and the other end tied through a resistor to ground. The resistor should be selected to give 0.6 mA through the 1k potentiometer. AC zeroing (hold step zeroing) can be obtained by adding an inverter with the adjustment pot tied input to output. A 10 pF capacitor from the wiper to the hold capacitor will give 4 mV hold step adjustment with a 0.01 F hold capacitor and 5V logic supply. For larger logic swings, a smaller capacitor (< 10 pF) may be used. LOGIC RISE TIME For proper operation, logic signals into the LF198 must have a minimum dV/dt of 1.0 V/s. Slower signals will cause excessive hold step. If a R/C network is used in front of the logic input for signal delay, calculate the slope of the waveform at the threshold point to ensure that it is at least 1.0 V/s. SAMPLING DYNAMIC SIGNALS Sample error to moving input signals probably causes more confusion among sample-and-hold users than any other parameter. The primary reason for this is that many users make the assumption that the sample and hold amplifier is truly locked on to the input signal while in the sample mode. In actuality, there are finite phase delays through the circuit creating an input-output differential for fast moving signals. In addition, although the output may have settled, the hold capacitor has an additional lag due to the 300 series resistor on the chip. This means that at the moment the "hold" command arrives, the hold capacitor voltage may be somewhat different than the actual analog input. The effect of these delays is opposite to the effect created by delays in the logic which switches the circuit from sample to hold. For example, consider an analog input of 20 Vp-p at 10 kHz. Maximum dV/dt is 0.6 V/s. With no analog phase delay and 100 ns logic delay, one could expect up to (0.1 s)(0.6V/s)= 60 mVerror if the "hold" signal arrived near maximum dV/dt of the input. A positive-going input would give a +60 mV error. Now assume a 1 MHz (3 dB) bandwidth for the overall analog loop. This generates a phase delay of 160 ns. If the hold capacitor sees this exact delay, then error due to analog delay will be (0.16 s) (0.6 V/s) = -96 mV. Total output error is +60 mV (digital) -96 mV (analog) for a total of -36 mV. To add to the confusion, analog delay is proportioned to hold capacitor value while digital delay remains constant. A family of curves (dynamic sampling error) is included to help estimate errors. A curve labeled Aperture Time has been included for sampling conditions where the input is steady during the sampling period, but may experience a sudden change nearly coincident with the "hold" command. This curve is based on a 1 mV error fed into the output. A second curve, Hold Settling Time indicates the time required for the output to settle to 1 mV after the "hold" command. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML 11 LF198QML SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com DIGITAL FEEDTHROUGH Fast rise time logic signals can cause hold errors by feeding externally into the analog input at the same time the amplifier is put into the hold mode. To minimize this problem, board layout should keep logic lines as far as possible from the analog input and the Ch pin. Grounded guarding traces may also be used around the input line, especially if it is driven from a high impedance source. Reducing high amplitude logic signals to 2.5V will also help. Guarding Technique Figure 22. Use 10-pin layout. Guard around Chis tied to output. 12 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML LF198QML www.ti.com SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 Typical Applications X1000 Sample & Hold Sample and Difference Circuit (Output Follows Input in Hold Mode) VOUT = VB + VIN(HOLD MODE) *For lower gains, the LM108 must be frequency compensated Ramp Generator with Variable Reset Level Integrator with Programmable Reset Level Output Holds at Average of Sampled Input Increased Slew Current Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML 13 LF198QML SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 14 www.ti.com Reset Stabilized Amplifier (Gain of 1000) Fast Acquisition, Low Droop Sample & Hold Synchronous Correlator for Recovering Signals Below Noise Level 2-Channel Switch Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML LF198QML www.ti.com SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 A B Gain 1 0.02% 1 0.2% ZIN 1010 47 k BW 1 MHz 400 kHz Crosstalk -90 dB -90 dB 6 mV 75 mV @ 1 kHz Offset DC & AC Zeroing Staircase Generator *Select for step height 50k 1V Step Differential Hold Capacitor Hysteresis Compensation **Adjust for amplitude Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML 15 LF198QML SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 www.ti.com Definition of Terms Hold Step: The voltage step at the output of the sample and hold when switching from sample mode to hold mode with a steady (dc) analog input voltage. Logic swing is 5V. Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10V. Note that acquisition time is not just the time required for the output to settle, but also includes the time required for all internal nodes to settle so that the output assumes the proper value when switched to the hold mode. Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a per cent difference. Hold Settling Time: The time required for the output to settle within 1 mV of final value after the "hold" logic command. Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the time the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew rate. Note that this error term occurs even for long sample times. Aperture Time: The delay required between "Hold" command and an input analog transition, so that the transition does not affect the held output. 16 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML LF198QML www.ti.com SNOSAH9A - FEBRUARY 2005 - REVISED MARCH 2013 REVISION HISTORY SECTION Date Released Revision Section 02/25/05 A New release, Corporate format 03/20/2013 A All Sections Originator L. Lytle Changes 1 MDS converted to corp. datasheet format. MNLF198-X Rev 3B0 MDS to be archived. Change has been made to Electrical Section, Parameter IOS- . Max limit was 7.0 now is -7.0 confirmed with SG. Added note Parameter tested go no go to VTH test. Changed Layout of National Data Sheet to TI format Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LF198QML 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) (3) Top-Side Markings (4) 5962-8760801GA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LF198H/883 5962-8760801GA Q A CO 5962-8760801GA Q > T LF198H/883 ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LF198H/883 5962-8760801GA Q A CO 5962-8760801GA Q > T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2013, Texas Instruments Incorporated