LT3580IMS8E - LINEAR TECHNOLOGY

LT3580

3580fg

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Boost/Inverting DC/DC

Converter with 2A Switch,

Soft-Start, and Synchronization

The LT

3580 is a PWM DC/DC converter containing an

internal 2A, 42V switch. The LT3580 can be configured

as either a boost, SEPIC or inverting converter. Capable

of generating 12V at 550mA or –12V at 350mA from a

5V input, the LT3580 is ideal for many local power supply

designs.

The LT3580 has an adjustable oscillator, set by a resistor

from the RT pin to ground. Additionally, the LT3580 can

be synchronized to an external clock. The free running or

synchronized switching frequency range of the part can

be set between 200kHz and 2.5MHz.

The LT3580 also features innovative SHDN pin circuitry

that allows for slowly varying input signals and an adjust-

able undervoltage lockout function.

Additional features such as frequency foldback and

soft-start are integrated. The LT3580 is available in tiny

3mm × 3mm 8-lead DFN and 8-lead MSOP packages.

1.2MHz, 5V to 12V Boost Converter Achieves Over 88% Efficiency

n 2A Internal Power Switch

n Adjustable Switching Frequency

n Single Feedback Resistor Sets VOUT

n Synchronizable to External Clock

n High Gain SHDN Pin Accepts Slowly Varying

Input Signals

n Wide Input Voltage Range: 2.5V to 32V

n Low VCESAT Switch: 300mV at 1.5A (Typical)

n Integrated Soft-Start Function

n Easily Configurable as a Boost or Inverting Converter

n User Configurable Undervoltage Lockout (UVLO)

n Tiny 8-Lead 3mm × 3mm DFN and 8-Lead MSOP

Packages

n VFD Bias Supplies

n TFT-LCD Bias Supplies

n GPS Receivers

n DSL Modems

n Local Power Supply

Efficiency and Power Loss

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

10μF

VOUT

12V

550mA

4.2μH

130k

VIN

VIN SW

3580 TA01

LT3580

75k

10k

SHDN GND

SYNC SS

1nF

0.1μF

2.2μF

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

400

3580 TA01b

200

100 500

300 600

200

600

1200

400

800

1000

LT3580

3580fg

ABSOLUTE MAXIMUM RATINGS

VIN Voltage .................................................–0.3V to 32V

SW Voltage ................................................ –0.4V to 42V

RT Voltage ................................................... –0.3V to 5V

SS and FB Voltage ....................................–0.3V to 2.5V

VC Voltage ................................................... –0.3V to 2V

SHDN Voltage ............................................ –0.3V to 32V

SYNC Voltage ............................................–0.3V to 5.5V

(Note 1)

TOP VIEW

DD PACKAGE

8-LEAD

(

3mm s 3mm

)

PLASTIC DFN

GND

1FB

VIN

SYNC

SHDN

TJMAX = 125°C, θJA = 43°C/W

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

VIN

SYNC

SHDN

TOP VIEW

GND

MS8E PACKAGE

8-LEAD PLASTIC MSOP

θJA = 35°C/W TO 40°C/W

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3580EDD#PBF LT3580EDD#TRPBF LCXY 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT3580IDD#PBF LT3580IDD#TRPBF LCXY 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT3580EMS8E#PBF LT3580EMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP –40°C to 125°C

LT3580IMS8E#PBF LT3580IMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP –40°C to 125°C

LT3580HMS8E#PBF LT3580HMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP –40°C to 150°C

LT3580MPMS8E#PBF LT3580MPMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP –55°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Operating Junction Temperature Range

LT3580E (Notes 2, 5) .........................–40°C to 125°C

LT3580I (Notes 2, 5) ..........................–40°C to 125°C

LT3580H (Notes 2, 5) ........................–40°C to 150°C

LT3580MP (Notes 2, 5) ..................... –55°C to 125°C

Storage Temperature Range ..................–65°C to 150°C

LT3580

3580fg

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT3580E is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LT3580I is guaranteed over the full –40°C to 125°C operating junction

temperature range. The LT3580H is guaranteed over the full –40°C to

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN unless otherwise noted. (Note 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Operating Voltage Range l2.5 32 V

Positive Feedback Voltage l1.195 1.215 1.230 V

Negative Feedback Voltage l0 5 12 mV

Positive FB Pin Bias Current VFB = Positive Feedback Voltage, Current Into Pin l81 83.3 85 μA

Negative FB Pin Bias Current VFB = Negative Feedback Voltage, Current Out of Pin

(LT3580E, LT3580I, LT3580MP)

(LT3580H)

83.3

85.5

μA

Error Amplifier Transconductance 230 μmhos

Error Amplifier Voltage Gain 70 V/V

Quiescent Current VSHDN = 2.5V, Not Switching 1 1.5 mA

Quiescent Current in Shutdown VSHDN = 0V 0 1 μA

Reference Line Regulation 2.5V ≤ VIN ≤ 32V 0.01 0.05 %/V

Switching Frequency, fOSC RT = 45.3k (LT3580E, LT3580I, LT3580H)

RT = 45.3k (LT3580MP)

RT = 464k (LT3580E, LT3580I, LT3580H)

RT = 464k (LT3580MP)

1.8

180

200

2.2

2.25

220

225

MHz

kHz

Switching Frequency in Foldback Compared to Normal fOSC 1/4 Ratio

Switching Frequency Set Range SYNCing or Free Running l200 2500 kHz

SYNC High Level for Synchronization l1.3 V

SYNC Low Level for Synchronization l0.4 V

SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 35 65 %

Recommended Minimum SYNC Ratio fSYNC/fOSC 3/4

Minimum Off-Time 60 ns

Minimum On-Time 100 ns

Switch Current Limit Minimum Duty Cycle (Note3) (LT3580E, LT3580I, LT3580H)

Minimum Duty Cycle (Note3) (LT3580MP)

Maximum Duty Cycle (Notes 3, 4) (LT3580E, LT3580I,

LT3580MP)

Maximum Duty Cycle (Notes 3, 4) (LT3580H)

2.2

2.15

1.6

1.55

2.5

2.2

1.9

2.8

2.6

Switch VCESAT ISW = 1.5A 300 mV

Switch Leakage Current VSW = 5V 0.01 1 μA

Soft-Start Charging Current VSS = 0.5V l468 μA

SHDN Minimum Input

Voltage High

Active Mode, SHDN Rising (LT3580E, LT3580I)

Active Mode, SHDN Rising (LT3580H, LT3580MP)

Active Mode, SHDN Falling (LT3580E, LT3580I)

Active Mode, SHDN Falling (LT3580H, LT3580MP)

1.27

1.25

1.24

1.22

1.32

1.29

1.38

1.4

1.33

1.35

SHDN Input Voltage Low Shutdown Mode l0.3 V

SHDN Pin Bias Current VSHDN = 3V

VSHDN = 1.3V

VSHDN = 0V

9.7

11.6

13.4

0.1

μA

150°C operating junction temperature range. The LT3580MP is guaranteed

over the full –55°C to 125°C operating junction temperature range.

Operating lifetime is derated at junction temperatures greater than 125°C.

Note 3: Current limit guaranteed by design and/or correlation to static test.

Note 4: Current limit measured at equivalent switching frequency of 2.5MHz.

Note 5: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

LT3580

3580fg

TYPICAL PERFORMANCE CHARACTERISTICS

Switch Current Limit at 1MHz Switch Saturation Voltage

Switch Current Limit at Minimum

Duty Cycle

Switch Current Limit at Minimum

Duty Cycle Positive Feedback Voltage

Switching Waveforms for

Figure 14 Circuit

Oscillator Frequency

Oscillator Frequency During

Soft-Start Internal UVLO

TA = 25°C unless otherwise specified

DUTY CYCLE (%)

SWITCH CURRENT LIMIT (A)

0.5

1.0

1.5

2.0

30 50 70 90

3580 G01

2.5

20 40 60 80

SWITCH CURRENT (A)

SATURATION VOLTAGE (mV)

200

250

300

3580 G02

150

100

00.5 11.5

400

350

SS VOLTAGE (mV)

SWITCH CURRENT (A)

0.5

1.0

1.5

2.0

200 400 600 800

3580 G03

1000 1200

2.5

TEMPERATURE (°C)

–50

SWITCH CURRENT LIMIT (A)

0.5

1.0

1.5

2.0

2.5

3.0

0 50 100

3580 G04

TEMPERATURE (°C)

–50 –25

1.19

FB VOLTAGE (V)

1.21

1.24

050 75

3580 G05

1.20

1.23

1.22

25 100 125

VOUT

50mV/DIV

AC COUPLED

VSW

10V/DIV

0.5A/DIV

200ns/DIV 3580 G06

TEMPERATURE (°C)

–50

FREQUENCY (MHz)

1.9

2.1

2.3

3580 G07

1.7

1.5

1.1 050 100

1.3

2.7

RT = 35.7k

2.5

RT = 75k

FB VOLTAGE (V)

NORMALIZED OSCILLATOR FREQUENCY (F/FNOM)

1/4

1/2

TA = –35°C

TA = 25°C

TA = 100°C

1/3

0.2 0.4

INVERTING

CONFIGURATIONS

BOOSTING

CONFIGURATIONS

0.6 0.8

3580 G08

1.0 1.2

TEMPERATURE (°C)

–50

2.20

VIN VOLTAGE (V)

2.22

2.26

2.28

2.30

2.40

2.34

050

3580 G09

2.24

2.36

2.38

2.32

100

LT3580

3580fg

TYPICAL PERFORMANCE CHARACTERISTICS

SHDN Pin Current SHDN Pin Current Active/Lockout Threshold

TA = 25°C unless otherwise specified

PIN FUNCTIONS

FB (Pin 1): Positive and Negative Feedback Pin. For a

boost or inverting converter, tie a resistor from the FB pin

to VOUT according to the following equations:

RFB =VOUT −1.215

()

83.3 • 10−6; Boost or SEPIC Converter

RFB =VOUT +5mV

()

83.3 • 10−6; Inverting Converter

VC (Pin 2): Error Amplifier Output Pin. Tie external

compensation network to this pin.

VIN (Pin 3): Input Supply Pin. Must be locally bypassed.

SW (Pin 4): Switch Pin. This is the collector of the internal

NPN Power switch. Minimize the metal trace area connec-

ted to this pin to minimize EMI.

SHDN (Pin 5): Shutdown Pin. In conjunction with the

UVLO (undervoltage lockout) circuit, this pin is used

to enable/disable the chip and restart the soft-start

sequence. Drive below 1.24V (LT3580E, LT3580I) or 1.22V

(LT3580H, LT3580MP) to disable the chip. Drive above

1.38V (LT3580E, LT3580I) or 1.40V (LT3580H, LT3580MP)

to activate chip and restart the soft-start sequence. Do

not float this pin.

RT (Pin 6): Timing Resistor Pin. Adjusts the switching

frequency. Place a resistor from this pin to ground to set

the frequency to a fixed free running level. Do not float

this pin.

SS (Pin 7): Soft-Start Pin. Place a soft-start capacitor here.

Upon start-up, the SS pin will be charged by a (nominally)

275k resistor to about 2.2V.

SYNC (Pin 8): To synchronize the switching frequency to

an outside clock, simply drive this pin with a clock. The

high voltage level of the clock needs to exceed 1.3V, and

the low level should be less 0.4V. Drive this pin to less than

0.4V to revert to the internal free running clock. See the

Applications Information section for more information.

GND (Exposed Pad Pin 9): Ground. Exposed pad must

be soldered directly to local ground plane.

SHDN VOLTAGE (V)

SHDN PIN CURRENT (μA)

0.5 1

–50°C

1.5 2

3580 G10

100°C 20°C

SHDN VOLTAGE (V)

SHDN PIN CURRENT (μA)

200

250

–50°C

20°C

100°C

300

15 25

3580 G11

150

100

510 20 30

TEMPERATURE (°C)

–50

1.20

SHDN VOLTAGE (V)

1.22

1.26

1.28

1.30

1.40

1.34

050

3580 G12

1.24

1.36

1.38

1.32

100

SHDN RISING

SHDN FALLING

LT3580

3580fg

BLOCK DIAGRAM

The LT3580 uses a constant-frequency, current mode con-

trol scheme to provide excellent line and load regulation.

Refer to the Block Diagram which shows the LT3580 in a

boost configuration. At the start of each oscillator cycle,

the SR latch (SR1) is set, which turns on the power switch,

Q1. The switch current flows through the internal current

sense resistor generating a voltage proportional to the

switch current. This voltage (amplified by A4) is added

to a stabilizing ramp and the resulting sum is fed into the

positive terminal of the PWM comparator A3. When this

voltage exceeds the level at the negative input of A3, the SR

latch is reset, turning off the power switch. The level at the

negative input of A3 (VC pin) is set by the error amplifier A1

(or A2) and is simply an amplified version of the difference

between the feedback voltage (FB pin) and the reference

voltage (1.215V or 5mV depending on the configuration).

In this manner, the error amplifier sets the correct peak

current level to keep the output in regulation.

The LT3580 has a novel FB pin architecture that can be

used for either boost or inverting configurations. When

configured as a boost converter, the FB pin is pulled up

to the internal bias voltage of 1.215V by the RFB resistor

connected from VOUT to FB. Comparator A2 becomes

inactive and comparator A1 performs the inverting

amplification from FB to VC. When the LT3580 is in an

inverting configuration, the FB pin is pulled down to 5mV

by the RFB resistor connected from VOUT to FB. Comparator

A1 becomes inactive and comparator A2 performs the

noninverting amplification from FB to VC.

–

∑

31.215V

REFERENCE

ADJUSTABLE

OSCILLATOR

FREQUENCY

FOLDBACK

RAMP

GENERATOR

COMPARATOR

DISCHARGE

DETECT

SS VC

275k

SR2

14.6k

QSR1

SYNC

÷N

SHDN

1.3V

0.01Ω

GND

RFB

DRIVER

ILIMIT

VIN

VOU

CSS CCCIN

RCVIN

SOFT-

START

SYNC

BLOCK

UVLO

RSQ

3580 BD

OPERATION

LT3580

3580fg

OPERATION

Figure 1. SEPIC Topology Allows for the Input to Span

the Output Voltage. Coupled or Uncoupled Inductors

Can Be Used. Follow Noted Phasing if Coupled

Figure 2. Dual Inductor Inverting Topology Results in

Low Output Ripple. Coupled or Uncoupled Inductors

Can Be Used. Follow Noted Phasing if Coupled

SHUTDOWN

VIN > VOUT

VIN = VOUT

VIN < VOUT

VOUT

VIN SW

3580 F01

LT3580

SHDN

GND

SYNC SS

CSS

•

SHUTDOWN

VIN VOUT

VIN SW

3580 F02

LT3580

SHDN

GND

SYNC SS

CSS

••

SEPIC Topology

The LT3580 can be configured as a SEPIC (single-ended

primary inductance converter). This topology allows for

the input to be higher, equal, or lower then the desired

output voltage. Output disconnect is inherently built into

the SEPIC topology, meaning no DC path exists between the

input and output. This is useful for applications requiring

the output to be disconnected from the input source when

the circuit is in shutdown.

Inverting Topology

The LT3580 can also work in a dual inductor inverting

topology. The part’s unique feedback pin allows for the

inverting topology to be built by simply changing the

connection of external components. This solution results

in very low output voltage ripple due to inductor L2 in

series with the output. Abrupt changes in output capacitor

current are eliminated because the output inductor deliv-

ers current to the output during both the off-time and the

on-time of the LT3580 switch.

Start-Up Operation

Several functions are provided to enable a very clean

start-up for the LT3580.

• First, the SHDN pin voltage is monitored by an internal

voltage reference to give a precise turn-on voltage level.

An external resistor (or resistor divider) can be connected

from the input power supply to the SHDN pin to provide

a user-programmable undervoltage lockout function.

• Second, the soft-start circuitry provides for a gradual

ramp-up of the switch current. When the part is brought

out of shutdown, the external SS capacitor is first

discharged (providing protection against SHDN pin

glitches and slow ramping), then an integrated 275k

resistor pulls the SS pin up to ~2.2V. By connecting an

external capacitor to the SS pin, the voltage ramp rate

on the pin can be set. Typical values for the soft-start

capacitor range from 100nF to 1μF.

• Finally, the frequency foldback circuit reduces the

switching frequency when the FB pin is in a nominal range

of 350mV to 900mV. This feature reduces the minimum

duty cycle that the part can achieve thus allowing better

control of the switch current during start-up. When the

FB voltage is pulled outside of this range, the switching

frequency returns to normal.

Current Limit and Thermal Shutdown Operation

The LT3580 has a current limit circuit not shown in the

Block Diagram. The switch current is consistently moni-

tored and not allowed to exceed the maximum switch

current at a given duty cycle (see the Electrical Charac-

teristics table). If the switch current reaches this value,

the SR latch (SR1) is reset regardless of the state of the

comparator (A1/A2). Also not shown in the Block Diagram

is the thermal shutdown circuit. If the temperature of the

part exceeds approximately 165°C, the SR2 latch is set

regardless of the state of the comparator (A1/A2). A full

soft-start cycle will then be initiated. The current limit and

thermal shutdown circuits protect the power switch as well

as the external components connected to the LT3580.

LT3580

3580fg

Setting Output Voltage

The output voltage is set by connecting a resistor (RFB)

from VOUT to the FB pin. RFB is determined from the

following equation:

RFB =|V

OUT −VFB |

83.3µA

where VFB is 1.215V (typical) for non-inverting topologies

(i.e., boost and SEPIC regulators) and 5mV (typical) for

inverting topologies (see the Electrical Characteristics).

Power Switch Duty Cycle

In order to maintain loop stability and deliver adequate

current to the load, the power NPN (Q1 in the Block Dia-

gram) cannot remain “on” for 100% of each clock cycle.

The maximum allowable duty cycle is given by:

DCMAX =(T

P−Min Off Time)

•100%

where TP is the clock period and Min Off Time (found in

the Electrical Characteristics) is typically 60ns.

The application should be designed so that the operating

duty cycle does not exceed DCMAX.

Duty cycle equations for several common topologies are

given below, where VD is the diode forward voltage drop

and VCESAT is typically 300mV at 1.5A.

For the boost topology:

DC ≅VOUT −VIN +VD

VOUT +VD−VCESAT

For the SEPIC or dual inductor inverting topology (see

Figures 1 and 2):

DC ≅VD+|V

OUT |

VIN +|V

OUT |+VD−VCESAT

The LT3580 can be used in configurations where the duty

cycle is higher than DCMAX, but it must be operated in the

discontinuous conduction mode so that the effective duty

cycle is reduced.

APPLICATIONS INFORMATION

Inductor Selection

General Guidelines

: The high frequency operation of the

LT3580 allows for the use of small surface mount inductors.

For high efficiency, choose inductors with high frequency

core material, such as ferrite, to reduce core losses. To

improve efficiency, choose inductors with more volume

for a given inductance. The inductor should have low

DCR (copper wire resistance) to reduce I2R losses, and

must be able to handle the peak inductor current without

saturating. Note that in some applications, the current

handling requirements of the inductor can be lower, such

as in the SEPIC topology, where each inductor only carries

a fraction of the total switch current. Molded chokes or chip

inductors usually do not have enough core area to sup-

port peak inductor currents in the 2A to 3A range. To

minimize radiated noise, use a toroidal or shielded inductor.

Note that the inductance of shielded types will drop more

as current increases, and will saturate more easily. See

Table 1 for a list of inductor manufacturers. Thorough lab

evaluation is recommended to verify that the following

guidelines properly suit the final application.

Table 1.Inductor Manufacturers

Coilcraft DO3316P, MSS7341 and LPS4018

Series

www.coilcraft.com

Coiltronics DR, LD and CD Series www.coiltronics.com

Murata LQH55D and LQH66S Series www.murata.com

Sumida CDRH5D18B/HP, CDR6D23MN,

CDRH6D26/HP, CDRH6D28,

CDR7D28MN and CDRH105R Series

www.sumida.com

TDK RLF7030 and VLCF4020 Series www.tdk.com

Würth WE-PD and WE-PD2 Series www.we-online.com

Minimum Inductance

: Although there can be a tradeoff with

efficiency, it is often desirable to minimize board space by

choosing smaller inductors. When choosing an inductor,

there are two conditions that limit the minimum inductance;

(1) providing adequate load current, and (2) avoidance of

subharmonic oscillation. Choose an inductance that is high

enough to meet both of these requirements.

Adequate Load Current

: Small value inductors result in

increased ripple currents and thus, due to the limited peak

switch current, decrease the average current that can be

LT3580

3580fg

APPLICATIONS INFORMATION

provided to a load (IOUT). In order to provide adequate

load current, L should be at least:

L>DC • VIN

2(f) ILIM −|V

OUT |• I

OUT

VIN •η

⎛

⎝

⎜⎞

⎠

⎟

for boost, topologies, or:

L>DC • VIN

2(f) ILIM −VOUT •I

OUT

VIN •η−IOUT

⎛

⎝

⎜

⎞

⎠

⎟

for the SEPIC and inverting topologies.

where:

L = L1||L2 for uncoupled dual inductor topologies

DC = switch duty cycle (see previous section)

ILIM = switch current limit, typically about 2.4A at 50%

duty cycle (see the Typical Performance Characteristics

section).

η = power conversion efficiency (typically 88% for

boost and 75% for dual inductor topologies at high

currents).

f = switching frequency

Negative values of L indicate that the output load current

IOUT exceeds the switch current limit capability of the

LT3580.

Avoiding Subharmonic Oscillations

: The LT3580’s internal

slope compensation circuit will prevent subharmonic oscil-

lations that can occur when the duty cycle is greater than

50%, provided that the inductance exceeds a minimum

value. In applications that operate with duty cycles greater

than 50%, the inductance must be at least:

L>VIN •2•DC–1

()

(1−DC) • (f)

for boost, coupled inductor SEPIC, and coupled inductor

inverting topologies, or:

L1 L2 >VIN •2•DC–1

()

(1−DC) • (f)

for the uncoupled inductor SEPIC and uncoupled inductor

inverting topologies.

Maximum Inductance

: Excessive inductance can reduce

current ripple to levels that are difficult for the current com-

parator (A3 in the Block Diagram) to cleanly discriminate,

thus causing duty cycle jitter and/or poor regulation. The

maximum inductance can be calculated by:

LMAX =VIN –V

CESAT

IMIN−RIPPLE

•DC

where LMAX is L1||L2 for uncoupled dual inductor topolo-

gies and IMIN-RIPPLE is typically 95mA.

Current Rating

: Finally, the inductor(s) must have a rating

greater than its peak operating current to prevent inductor

saturation resulting in efficiency loss. In steady state, the

peak input inductor current (continuous conduction mode

only) is given by:

IL1−PEAK =VOUT •IOUT

VIN •η+VIN •DC

2•L1•f

for the boost, uncoupled inductor SEPIC and uncoupled

inductor inverting topologies.

For uncoupled dual inductor topologies, the peak output

inductor current is given by:

IL2−PEAK =IOUT +VOUT •1–DC

()

2•L2•f

For the coupled inductor topologies:

IOUT 1+VOUT

η•VIN

⎡

⎣

⎢⎤

⎦

⎥+VIN •DC

2•L•f

Note: Inductor current can be higher during load transients.

It can also be higher during start-up if inadequate soft-start

capacitance is used.

Capacitor Selection

Low ESR (equivalent series resistance) capacitors should

be used at the output to minimize the output ripple voltage.

Multilayer ceramic capacitors are an excellent choice, as

they have an extremely low ESR and are available in very

small packages. X5R or X7R dielectrics are preferred, as

LT3580

3580fg

APPLICATIONS INFORMATION

these materials retain their capacitance over wider voltage

and temperature ranges. A 4.7μF to 20μF output capaci-

tor is sufficient for most applications, but systems with

very low output currents may need only a 1μF or 2.2μF

output capacitor. Always use a capacitor with a sufficient

voltage rating. Many capacitors rated at 2.2μF to 20μF,

particularly 0805 or 0603 case sizes, have greatly reduced

capacitance at the desired output voltage. Solid tantalum

or OS-CON capacitors can be used, but they will occupy

more board area than a ceramic and will have a higher

ESR with greater output ripple.

Ceramic capacitors also make a good choice for the input

decoupling capacitor, which should be placed as closely as

possible to the LT3580. A 2.2μF to 4.7μF input capacitor

is sufficient for most applications.

Table 2 shows a list of several ceramic capacitor manufac-

turers. Consult the manufacturers for detailed information

on their entire selection of ceramic parts.

Table 2. Ceramic Capacitor Manufacturers

Kemet www.kemet.com

Murata www.murata.com

Taiyo Yuden www.t-yuden.com

Compensation—Adjustment

To compensate the feedback loop of the LT3580, a series

resistor-capacitor network in parallel with a single capacitor

should be connected from the VC pin to GND. For most

applications, the series capacitor should be in the range

of 470pF to 2.2nF with 1nF being a good starting value.

The parallel capacitor should range in value from 10pF to

100pF with 47pF a good starting value. The compensation

resistor, RC, is usually in the range of 5k to 50k. A good

technique to compensate a new application is to use a

100kΩ potentiometer in place of series resistor RC. With

the series capacitor and parallel capacitor at 1nF and 47pF

respectively, adjust the potentiometer while observing the

transient response and the optimum value for RC can be

found. Figures 3a to 3c illustrate this process for the circuit

of Figure 14 with a load current stepped between 400mA

and 500mA. Figure 3a shows the transient response with

RC equal to 1k. The phase margin is poor, as evidenced by

the excessive ringing in the output voltage and inductor

current. In Figure 3b, the value of RC is increased to 3k,

which results in a more damped response. Figure 3c

shows the results when RC is increased further to 10k. The

transient response is nicely damped and the compensation

procedure is complete.

Figure 3a. Transient Response Shows Excessive Ringing Figure 3b. Transient Response Is Better

Figure 3c. Transient Response Is Well Damped

VOUT

200mV/DIV

AC COUPLED

0.5A/DIV

200μs/DIVRC = 1k 3580 F03a

VOUT

200mV/DIV

AC COUPLED

0.5A/DIV

200μs/DIVRC = 3k 3580 F03b

VOUT

200mV/DIV

AC COUPLED

0.5A/DIV

200μs/DIVRC = 10k 3580 F03c

LT3580

3580fg

APPLICATIONS INFORMATION

Compensation—Theory

Like all other current mode switching regulators, the

LT3580 needs to be compensated for stable and efficient

operation. Two feedback loops are used in the LT3580—

a fast current loop which does not require compensation,

and a slower voltage loop which does. Standard bode plot

analysis can be used to understand and adjust the voltage

feedback loop.

As with any feedback loop, identifying the gain and phase

contribution of the various elements in the loop is critical.

Figure 4 shows the key equivalent elements of a boost

converter. Because of the fast current control loop, the

power stage of the IC, inductor and diode have been replaced

by a combination of the equivalent transconductance

amplifier gmp and the current controlled current source

(which converts IVIN to ηVIN/VOUT • IVIN). gmp acts as

a current source where the peak input current, IVIN, is

proportional to the VC voltage. η is the efficiency of the

switching regulator, and is typically about 88%.

Note that the maximum output currents of gmp and gma are

finite. The limits for gmp are in the Electrical Characteristics

section (switch current limit), and gma is nominally limited

to about ±12μA.

From Figure 4, the DC gain, poles and zeros can be cal-

culated as follows:

Output Pole: P1=2

2•π•RL•C

OUT

Error Amp Pole: P2 =1

2•π•R

O+RC

⎡

⎣⎤

⎦•C

Error Amp Zero: Z1=1

2•π•RC•C

DC Gain:

(Breaking Loop at FB Pin)

ADC = AOL(0) = ∂VC

∂VFB

•∂IVIN

∂VC

•∂VOUT

∂IVIN

•∂VFB

∂VOUT

gma •R0

(

)

•g

mp •η•VIN

VOUT

•RL

⎛

⎝

⎜⎞

⎠

⎟•0.5R2

R1+0.5R2

ESR Zero: Z2 =1

2•π•RESR •C

OUT

RHP Zero: Z3 =VIN2•RL

2•π•V

OUT2•L

High Frequency Pole: P3 >fS

Phase Lead Zero: Z4 =1

2•π•R1•CPL

Phase Lead Pole: P4 =1

2•π•

R1• R2

R1+R2

•C

Error Amp Filter Pole:

P5 = 1

2•π•RC•RO

RC+RO

•C

,CF<CC

The current mode zero (Z3) is a right-half plane zero

which can be an issue in feedback control design, but is

manageable with proper external component selection.

Figure 4. Boost Converter Equivalent Model

–

gma

RCRO

CC: COMPENSATION CAPACITOR

COUT: OUTPUT CAPACITOR

CPL: PHASE LEAD CAPACITOR

CF: HIGH FREQUENCY FILTER CAPACITOR

gma: TRANSCONDUCTANCE AMPLIFIER INSIDE IC

gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER

RC: COMPENSATION RESISTOR

RL: OUTPUT RESISTANCE DEFINED AS VOUT DIVIDED BY ILOAD(MAX)

RO: OUTPUT RESISTANCE OF gma

R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK

RESR: OUTPUT CAPACITOR ESR

3580 F04

COUT

CPL

RESR

VOUT

IVIN

gmp

1.215V

REFERENCE

H•V

VOUT

•IVIN

LT3580

3580fg

APPLICATIONS INFORMATION

Using the circuit in Figure 14 as an example, Table 3 shows

the parameters used to generate the bode plot shown in

Figure 5.

Table 3. Bode Plot Parameters

PARAMETER VALUE UNITS COMMENT

RL21.8 ΩApplication Specific

COUT 10 μF Application Specific

RESR 10 mΩApplication Specific

RO305 kΩNot Adjustable

CC1000 pF Adjustable

CF0 pF Optional/Adjustable

CPL 0 pF Optional/Adjustable

RC10 kΩAdjustable

R1 130 kΩAdjustable

R2 14.6 kΩNot Adjustable

VOUT 12 V Application Specific

VIN 5 V Application Specific

gma 230 μmho Not Adjustable

gmp 7 mho Not Adjustable

L 4.2 μH Application Specific

fS1.2 MHz Adjustable

In Figure 5, the phase is –140° when the gain reaches 0dB

giving a phase margin of 40°. The crossover frequency

is 10kHz, which is more than three times lower than the

frequency of the RHP zero to achieve adequate phase

margin.

Diode Selection

Schottky diodes, with their low forward voltage drops and

fast switching speeds, are recommended for use with the

LT3580. The Microsemi UPS120 is a very good choice.

Where the input-to-output voltage differential exceeds 20V,

use the UPS140 (a 40V diode). These diodes are rated to

handle an average forward current of 1A.

Oscillator

The operating frequency of the LT3580 can be set by the

internal free-running oscillator. When the SYNC pin is

driven low (< 0.4V), the frequency of operation is set by

a resistor from RT to ground. An internally trimmed timing

capacitor resides inside the IC. The oscillator frequency is

calculated using the following formula:

fOSC =91.9

(RT+1)

where fOSC is in MHz and RT is in kΩ. Conversely, RT

(in kΩ) can be calculated from the desired frequency

(in MHz) using:

RT=91.9

fOSC

−1

Clock Synchronization

The operating frequency of the LT3580 can be synchronized

to an external clock source. To synchronize to the external

source, simply provide a digital clock signal into the SYNC

pin. The LT3580 will operate at the SYNC clock frequency.

The LT3580 will revert to the internal free-running oscillator

clock after SYNC is driven low for a few free-running clock

periods.

Driving SYNC high for an extended period of time effectively

stops the operating clock and prevents latch SR1 from

becoming set (see the Block Diagram). As a result, the

switching operation of the LT3580 will stop.

The duty cycle of the SYNC signal must be between 35%

and 65% for proper operation. Also, the frequency of the

SYNC signal must meet the following two criteria:

Figure 5. Bode Plot for Example Boost Converter

FREQUENCY (Hz)

GAIN (dB)

PHASE (DEG)

100

120

140

100 1k 10k 100k 1M

3580 F05

–20

160

180

–120

–100

–80

–60

–40

–140

–160

–180

–200

–20

40o AT

10kHz

PHASE

GAIN

LT3580

3580fg

APPLICATIONS INFORMATION

(1) SYNC may not toggle outside the frequency range of

200kHz to 2.5MHz unless it is stopped low to enable

the free-running oscillator.

(2) The SYNC frequency can always be higher than the

free-running oscillator frequency, fOSC, but should not

be less than 25% below fOSC.

Operating Frequency Selection

There are several considerations in selecting the operating

frequency of the converter. The first is staying clear of

sensitive frequency bands, which cannot tolerate any

spectral noise. For example, in products incorporating RF

communications, the 455kHz IF frequency is sensitive to

any noise, therefore switching above 600kHz is desired.

Some communications have sensitivity to 1.1MHz, and in

that case, a 1.5MHz switching converter frequency may be

employed. The second consideration is the physical size

of the converter. As the operating frequency goes up, the

inductor and filter capacitors go down in value and size.

The tradeoff is efficiency, since the switching losses due

to NPN base charge (see Thermal Calculations), Schottky

diode charge, and other capacitive loss terms increase

proportionally with frequency.

Soft-Start

The LT3580 contains a soft-start circuit to limit peak switch

currents during start-up. High start-up current is inherent

in switching regulators in general since the feedback loop

is saturated due to VOUT being far from its final value. The

regulator tries to charge the output capacitor as quickly as

possible, which results in large peak currents.

The start-up current can be limited by connecting an

external capacitor (typically 100nF to 1μF) to the SS pin.

This capacitor is slowly charged to ~2.2V by an internal

275k resistor once the part is activated. SS pin voltages

below ~1.1V reduce the internal current limit. Thus, the

gradual ramping of the SS voltage also gradually increases

the current limit as the capacitor charges. This, in turn,

allows the output capacitor to charge gradually toward its

final value while limiting the start-up current.

In the event of a commanded shutdown or lockout (SHDN

pin), internal undervoltage lockout (UVLO) or a thermal

lockout, the soft-start capacitor is automatically discharged

to ~200mV before charging resumes, thus assuring that

the soft-start occurs after every reactivation of the chip.

Shutdown

The SHDN pin is used to enable or disable the chip.

For most applications, SHDN can be driven by a digital

logic source. Voltages above 1.38V enable normal active

operation. Voltages below 300mV will shutdown the chip,

resulting in extremely low quiescent current.

While the SHDN voltage transitions through the lockout

voltage range (0.3V to 1.24V) the power switch is disabled

and the SR2 latch is set (see the Block Diagram). This

causes the soft-start capacitor to begin discharging,

which continues until the capacitor is discharged and

active operation is enabled. Although the power switch

is disabled, SHDN voltages in the lockout range do not

necessarily reduce quiescent current until the SHDN voltage

is near or below the shutdown threshold.

Also note that SHDN can be driven above VIN or VOUT as

long as the SHDN voltage is limited to less than 32V.

Figure 6. Chip States vs SHDN Voltage

Configurable Undervoltage Lockout

Figure 7 shows how to configure an undervoltage lockout

(UVLO) for the LT3580. Typically, UVLO is used in situations

where the input supply is current-limited, has a relatively

high source resistance, or ramps up/down slowly. A

switching regulator draws constant power from the source,

so source current increases as source voltage drops. This

looks like a negative resistance load to the source and can

cause the source to current-limit or latch low under low

(HYSTERESIS AND TOLERANCE)

SHUTDOWN

(LOW QUIESCENT CURRENT)

ACTIVE

(NORMAL OPERATION)

LOCKOUT

(POWER SWITCH OFF,

SS CAPACITOR DISCHARGED)

1.24V

0.0V

1.38V

0.3V

3580 F06

SHDN (V)

LT3580

3580fg

APPLICATIONS INFORMATION

source voltage conditions. UVLO prevents the regulator

from operating at source voltages where these problems

might occur.

The shutdown pin comparator has voltage hysteresis with

typical thresholds of 1.32V (rising) and 1.29V (falling).

Resistor RUVLO2 is optional. RUVLO2 can be included

to reduce the overall UVLO voltage variation caused by

variations in SHDN pin current (see the Electrical Character-

istics). A good choice for RUVLO2 is ≤10k ±1%. After

choosing a value for RUVLO2, RUVLO1 can be determined

from either of the following:

RUVLO1 =VIN+−1.32V

1.32V

RUVLO2

⎛

⎝

⎜⎞

⎠

⎟+11.6μA

RUVLO1 =VIN−−1.29V

1.29V

RUVLO2

⎛

⎝

⎜⎞

⎠

⎟+11.6μA

where VIN+ and VIN– are the VIN voltages when rising or

falling respectively.

For example, to disable the LT3580 for VIN voltages below

3.5V using the single resistor configuration, choose:

RUVLO1 =3.5V −1.29V

1.29V

∞

⎛

⎝

⎜⎞

⎠

⎟+11.6μA

=190.5k

Figure 7. Configurable UVLO

To activate the LT3580 for VIN voltage greater than

4.5V using the double resistor configuration, choose

RUVLO2 = 10k and:

RUVLO1 =4.5V −1.32V

1.32V

10k

⎛

⎝

⎜⎞

⎠

⎟+11.6μA

=22.1k

Internal Undervoltage Lockout

The LT3580 monitors the VIN supply voltage in case VIN

drops below a minimum operating level (typically about

2.3V). When VIN is detected low, the power switch is

deactivated, and while sufficient VIN voltage persists, the

soft-start capacitor is discharged. After VIN is detected

high, the power switch will be reactivated and the soft-start

capacitor will begin charging.

Thermal Considerations

For the LT3580 to deliver its full output power, it is imperative

that a good thermal path be provided to dissipate the heat

generated within the package. This is accomplished by

taking advantage of the thermal pad on the underside of

the IC. It is recommended that multiple vias in the printed

circuit board be used to conduct heat away from the IC and

into a copper plane with as much area as possible.

Thermal Lockout

If the die temperature reaches approximately 165°C, the

part will go into thermal lockout, the power switch will be

turned off and the soft-start capacitor will be discharged.

The part will be enabled again when the die temperature

has dropped by ~5°C (nominal).

Thermal Calculations

Power dissipation in the LT3580 chip comes from four

primary sources: switch I2R loss, NPN base drive (AC), NPN

base drive (DC), and additional input current. The following

formulas can be used to approximate the power losses.

These formulas assume continuous mode operation,

RUVLO2

(OPTIONAL)

1.3V

RUVLO1

3580 F07

VIN

ACTIVE/

LOCKOUT

GND

11.6μA

AT 1.3V

–

SHDN

LT3580

3580fg

APPLICATIONS INFORMATION

so they should not be used for calculating efficiency in

discontinuous mode or at light load currents.

Average Input Current: IIN =VOUT •IOUT

VIN •η

Switch I2R Loss: PSW =(DC)(IIN )2(RSW )

Base Drive Loss (AC): PBAC =13n(IIN )(VOUT )(f)

Base Drive Loss (DC): PBDC =(V

IN )(IIN )(DC)

Input Power Loss: P

INP =7mA(VIN )

where:

RSW = switch resistance (typically 200mΩ at 1.5A)

DC = duty cycle (see the Power Switch Duty Cycle sec-

tion for formulas)

η = power conversion efficiency (typically 88% at high

currents)

Example: boost configuration, VIN = 5V, VOUT = 12V,

IOUT = 0.5A, f = 1.25MHz, VD = 0.5V:

IN = 1.36A

DC = 61.5%

SW = 228mW

BAC = 270mW

BDC = 84mW

INP = 35mW

Total LT3580 power dissipation (PTOT) = 617mW

Thermal resistance for the LT3580 is influenced by the pres-

ence of internal, topside or backside planes. To calculate

die temperature, use the appropriate thermal resistance

number and add in worst-case ambient temperature:

J = TA + θJA • PTOT

where TJ = junction temperature, TA = ambient tempera-

ture, θJA = 43°C/W for the 3mm × 3mm DFN package and

35°C/W to 40°C/W for the MSOP Exposed Pad package.

PTOT is calculated above.

VIN Ramp Rate

While initially powering a switching converter application,

the VIN ramp rate should be limited. High VIN ramp rates can

cause excessive inrush currents in the passive components

of the converter. This can lead to current and/or voltage

overstress and may damage the passive components or

the chip. Ramp rates less than 500mV/μs, depending on

component parameters, will generally prevent these issues.

Also, be careful to avoid hot-plugging. Hot-plugging occurs

when an active voltage supply is “instantly” connected or

switched to the input of the converter. Hot-plugging results

in very fast input ramp rates and is not recommended.

Finally, for more information, refer to Linear application

note AN88, which discusses voltage overstress that can

occur when an inductive source impedance is hot-plugged

to an input pin bypassed by ceramic capacitors.

Layout Hints

As with all high frequency switchers, when considering

layout, care must be taken to achieve optimal electrical,

thermal and noise performance. One will not get adver-

tised performance with a careless layout. For maximum

efficiency, switch rise and fall times are typically in the

5ns to 10ns range. To prevent noise, both radiated and

conducted, the high speed switching current path, shown in

Figure 8, must be kept as short as possible. This is imple-

mented in the suggested layout of a boost configuration in

Figure 9. Shortening this path will also reduce the parasitic

trace inductance. At switch-off, this parasitic inductance

produces a flyback spike across the LT3580 switch. When

operating at higher currents and output voltages, with poor

layout, this spike can generate voltages across the LT3580

that may exceed its absolute maximum rating. A ground

plane should also be used under the switcher circuitry to

prevent interplane coupling and overall noise.

The VC and FB components should be kept as far away

as practical from the switch node. The ground for these

components should be separated from the switch cur-

rent path. Failure to do so can result in poor stability or

subharmonic oscillation.

LT3580

3580fg

APPLICATIONS INFORMATION

C2, for best load regulation. You can tie the local ground

into the system ground plane at the C3 ground terminal.

The cut ground copper at D1’s cathode is essential to

obtain low noise. This important layout issue arises due

to the chopped nature of the currents flowing in Q1 and

D1. If they are both tied directly to the ground plane before

being combined, switching noise will be introduced into

the ground plane. It is almost impossible to get rid of this

noise, once present in the ground plane. The solution

is to tie D1’s cathode to the ground pin of the LT3580

before the combined currents are dumped in the ground

plane as drawn in Figure 2, Figure 12 and Figure 13. This

single layout technique can virtually eliminate high

frequency “spike” noise, so often present on switching

regulator outputs.

Figure 8. High Speed “Chopped” Switching Path for Boost Topology

Board layout also has a significant effect on thermal re-

sistance. The exposed package ground pad is the copper

plate that runs under the LT3580 die. This is a good thermal

path for heat out of the package. Soldering the pad onto

the board reduces die temperature and increases the power

capability of the LT3580. Provide as much copper area as

possible around this pad. Adding multiple feedthroughs

around the pad to the ground plane will also help. Figures

9 and 10 show the recommended component placement

for the boost and SEPIC configurations, respectively.

Layout Hints for Inverting Topology

Figure 11 shows recommended component placement for

the dual inductor inverting topology. Input bypass capaci-

tor, C1, should be placed close to the LT3580, as shown.

The load should connect directly to the output capacitor,

3580 F08

VOUT

GND

LT3580

VIN

HIGH

FREQUENCY

SWITCHING

PATH

LOAD

LT3580

3580fg

Figure 9. Suggested Component Placement for Boost Topology

(Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed

Pad) Must Be Soldered Directly to the Local Ground Plane for

Adequate Thermal Performance. Multiple Vias to Additional

Ground Planes Will Improve Thermal Performance

Figure 10. Suggested Component Placement for Sepic Topology

(Both DFN And MSOP Packages. Not to Scale). Pin 9 (Exposed

Pad) Must Be Soldered Directly to the Local Ground Plane for

Adequate Thermal Performance. Multiple Vias to Additional

Ground Planes Will Improve Thermal Performance

Figure 11. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale).

Note Cut in Ground Copper at Diode’s Cathode. Pin 9 (Exposed Pad) Must be Soldered Directly to Local Ground

Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal

Performance

APPLICATIONS INFORMATION

3580 F10

VOUT

VIN

D1 C3

SHDN

SYNC

GND

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

THERMAL

PERFORMANCE

3580 F11

VOUT

VIN

SHDN

SYNC

GND

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

THERMAL

PERFORMANCE

3580 F09

VOUT

VIN

SHDN

SYNC

GND

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

THERMAL

PERFORMANCE

LT3580

3580fg

APPLICATIONS INFORMATION

Figure 12. Switch-On Phase of an Inverting Converter. L1 and L2 Have Positive dI/dt

Figure 13. Switch-Off Phase of an Inverting Converter. L1 and L2 Currents Have Negative dI/dt

Figure 14. 1.2MHz, 5V to 12V Boost Converter

L1 L2

–(VIN + ⏐VOUT⏐)

SW SWX

3580 F12

C1 C3 RLOAD

–VOUT

VIN

VCESAT

L1 L2

VIN + |VOUT|+ VD

SW SWX

C1 C3 RLOAD

–VOUT

VIN

3580 F13

10μF

VOUT

12V

550mA

4.2μH D1

130k

VIN

VIN SW

3580 F14

LT3580

75k

10k

SHDN GND

SYNC SS

1nF

0.1μF

2.2μF

C1: 2.2μF, 25V, X5R, 1206

C2: 10μF, 25V, X5R, 1206

D1: MICROSEMI UPS120

L1: SUMIDA CDR6D23MN-4R2

LT3580

3580fg

TYPICAL APPLICATIONS

750kHz, 5V to 40V, 150mA Boost Converter

Wide Input Range SEPIC Converter with 5V Output Switches at 2.5MHz

Transient Response with 400mA to 500mA Output Load Step

2.2μF

VOUT

40V

150mA

47μH D1

464k

VIN

VIN SW

3580 TA02

LT3580

121k

10k

SHDN GND

SYNC SS

4.7nF

0.1μF 47pF

2.2μF

C1: 2.2μF, 25V, X5R, 1206

C2: 2.2μF, 50V, X5R, 1206

D1: MICROSEMI UPS140

L1: SUMIDA CDRH105R-470

10μF

VOUT

5V, 600mA (VIN = 5V OR HIGHER)

500mA (VIN = 4V)

400mA (VIN = 3V)

300mA (VIN = 2.6V)

4.7μH

1μF

4.7μH

46.4k

VIN

2.6V TO 12V

OPERATING

12V TO 32V

TRANSIENT VIN SW

3580 TA03a

LT3580

35.7k

10k

SHDN GND

SYNC SS

1nF

22pF

0.1μF

2.2μF

C1: 2.2μF, 35V, X5R, 1206

C2: 10μF, 10V, X5R, 1206

C3: 1μF, 50V, X5R, 0805

D1: MICROSEMI UPS140

L1, L2: TDK VLCF4020T-4R7N1R2

VOUT

100mV/DIV

AC COUPLED

IL1 +IL2

0.5A/DIV

100μs/DIVVIN = 12V 3580 TA03b

LT3580

3580fg

TYPICAL APPLICATIONS

VFD (Vacuum Flourescent Display) Power Supply Switches at 2MHz to Avoid AM Band

Danger High Voltage! Operation by High Voltage Trained Personnel Only

1μF

10μH

383k

VIN

9V TO 16V 3.3V

VIN SW

VOUT2

95V

80mA

VOUT1

64V

40mA

3580 TA04

LT3580

10Ω

45.3k

10k

SHDN

GND

SYNC SS

1μF

2.2nF

0.1μF 47pF

4.7μF

C1, C2: 4.7μF, 25V, X5R, 1206

C3-C7: 1μF, 50V, X5R, 0805

D1-D4: ON SEMICONDUCTOR MBR0540

D5: MICROSEMI UPS140

L1: SUMIDA CDR6D28MNNP-100

R1, R2: 0.5W

LT3580

3580fg

TYPICAL APPLICATIONS

High Voltage Positive Power Supply Uses Tiny 5.8mm × 5.8mm × 3mm Transformer and Switches at 200kHz

Danger High Voltage! Operation by High Voltage Trained Personnel Only

Start-Up Waveforms

Switching Waveforms

68nF

FOR ANY VOUT BETWEEN 50V TO

350V, CHOOSE RFB ACCORDING TO

FOR 5V INPUT, KEEP MAXIMUM

OUTPUT POWER AT 1.58W

FOR 3.3V INPUT, KEEP MAXIMUM

OUTPUT POWER AT 0.88W

*MAY REQUIRE MULTIPLE SERIES

RESISTORS TO COMPLY WITH

MAXIMUM VOLTAGE RATINGS

VOUT

350V

4.5mA (VIN = 5V)

2.5mA (VIN = 3.3V)

1:10.4

RFB 4.22M*

VIN

3.3V TO 5V

VIN SW

3580 TA05a

LT3580

464k

10k

SHDN GND

7, 8

5, 6

SYNC SS

10nF

100pF

0.47μF

2.2μF

C1: 2.2μF, 25V, X5R, 1206

C2: TDK C3225X7R2J683M

D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES

D2: ON SEMICONDUCTOR MBR0540

T1: TDK LDT565630T-041

•

VOUT – 1.215

83.3μA

RFB =

4.7μH

IPRIMARY

1A/DIV

VOUT

50V/DIV

2ms/DIV5V INPUT

NO LOAD

3580 TA05b

IPRIMARY

1A/DIV

VOUT

2V/DIV

AC COUPLED

2μs/DIV5V INPUT

4.5mA LOAD

3580 TA05c

LT3580

3580fg

TYPICAL APPLICATIONS

High Voltage Negative Power Supply Uses Tiny 5.8mm × 5.8mm × 3mm Transformer and Switches at 200kHz

Danger High Voltage! Operation by High Voltage Trained Personnel Only

68nF

FOR ANY VOUT BETWEEN –50V TO

–350V, CHOOSE RFB ACCORDING TO

FOR 5V INPUT, KEEP MAXIMUM

OUTPUT POWER AT 1.58W

FOR 3.3V INPUT, KEEP MAXIMUM

OUTPUT POWER AT 0.88W

*MAY REQUIRE MULTIPLE SERIES

RESISTORS TO COMPLY WITH

MAXIMUM VOLTAGE RATINGS

VOUT

–350V

4.5mA (VIN = 5V)

2.5mA (VIN = 3.3V)

1:10.4 D1

RFB 4.22M*

VIN

3.3V TO 5V

VIN SW

3580 TA06

LT3580

464k

10k

SHDN GND

7, 8

5, 6

SYNC SS

10nF

100pF

0.47μF

2.2μF

C1: 2.2μF, 25V, X5R, 1206

C2: TDK C3225X7R2J683M

D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES

D2: ON SEMICONDUCTOR MBR0540

T1: TDK LDT565630T-041

•

VOUT

83.3μA

RFB =

4.7μH

LT3580

3580fg

TYPICAL APPLICATIONS

5V to 12V Boost Converter Switches at 2.5MHz and Uses a Tiny 4mm × 4mm × 1.7mm Inductor

Efficiency and Power Loss

vs Load Current

Transient Response with 400mA to

500mA to 400mA Output Load Step Start-Up Waveforms

4.7μF

VOUT

12V

500mA

3.3μH D1

130k

VIN

VIN SW

3580 TA07a

LT3580

35.7k

10k

SHDN GND

SYNC SS

2.2nF

0.1μF 47pF

4.7μF

C1, C2: 4.7μF, 25V, X5R, 1206

D1: MICROSEMI UPS120

L1: COILCRAFT LPS4018-332ML

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

400

3580 TA07b

200

100 500

300 600

200

400

600

1400

800

1000

1200

0.5A/DIV

VOUT

0.5V/DIV

AC COUPLED

100μs/DIV 3580 TA07c

1A/DIV

VOUT

5V/DIV

VSHDN

1V/DIV

2ms/DIV500mA LOAD 3580 TA07d

LT3580

3580fg

TYPICAL APPLICATIONS

–5V Output Inverting Converter Switches at 2.5MHz and Accepts Inputs Between 3.3V to 12V

Efficiency and Power Loss

vs Load Current

10μF

VOUT

–5V

800mA (VIN = 12V)

620mA (VIN = 5V)

450mA (VIN = 3.3V)

4.7μH

1μF

60.4k

VIN

3.3V TO 12V

VIN SW

3580 TA08a

LT3580

35.7k

10k

SHDN GND

SYNC SS

2.2nF

100pF

0.1μF

2.2μF

C1: 2.2μF, 25V, X5R, 1206

C2: 10μF, 25V, X5R, 1206

C3: 1μF, 50V, X5R, 0805

D1: CENTRAL SEMI CMMSH1-40

L1, L2: COILCRAFT LSP4018-472ML

4.7μH

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (W)

400

3580 TA08b

200

100 500

300 700600

200

400

600

1200

800

1000

VIN = 5V

LT3580

3580fg

PACKAGE DESCRIPTION

3.00 p0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

0.40 p 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 p 0.10

(2 SIDES)

0.75 p0.05

R = 0.125

TYP

2.38 p0.10

PIN 1

TOP MARK

(NOTE 6)

0.200 REF

0.00 – 0.05

(DD8) DFN 0509 REV C

0.25 p 0.05

2.38 p0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.65 p0.05

(2 SIDES)2.10 p0.05

0.50

BSC

0.70 p0.05

3.5 p0.05

PACKAGE

OUTLINE

0.25 p 0.05

0.50 BSC

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698 Rev C)

LT3580

3580fg

PACKAGE DESCRIPTION

MS8E Package

8-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1662 Rev F)

MSOP (MS8E) 0210 REV F

0.53 p 0.152

(.021 p .006)

SEATING

PLANE

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.18

(.007)

0.254

(.010)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015)

TYP

0.86

(.034)

REF

0.65

(.0256)

BSC

0o – 6o TYP

DETAIL “A”

GAUGE PLANE

4.90 p 0.152

(.193 p .006)

BOTTOM VIEW OF

EXPOSED PAD OPTION

765

3.00 p 0.102

(.118 p .004)

(NOTE 3)

3.00 p 0.102

(.118 p .004)

(NOTE 4)

0.52

(.0205)

REF

1.68

(.066)

1.88

(.074)

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

1.68 p 0.102

(.066 p .004)

1.88 p 0.102

(.074 p .004)

0.889 p 0.127

(.035 p .005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 p 0.038

(.0165 p .0015)

TYP

0.65

(.0256)

BSC

0.1016 p 0.0508

(.004 p .002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

LT3580

3580fg

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

F 06/10 Added GND to the Pin Configuration section.

Revised Note 2 in the Electrical Characteristics section.

Revised Graph G08 in the Typical Performance Characteristics section.

Revised the Applications Information section.

Revised Table 3 in the Applications Information section.

Revised Figure 13 in the Applications Information section.

Updated drawing TA01a in the Typical Applications section.

Updated Related Parts table.

10-11

G 09/10 Added H- and MP-Grade information to Absolute Maximum Ratings, Order Information, Electrical Characteristics and

Pin Functions sections.

Added text at end of General Guidelines and revised equations under Avoiding Subharmonic Oscillations in

Applications Information section.

2, 3, 5

8, 9

(Revision history begins at Rev F)

LT3580

3580fg

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0910 REV G • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LT1310 2A (ISW), 40V, 1.2MHz High Efficiency Step-Up DC/DC Converter VIN: 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1μA, ThinSOT™

Package

LT1613 550mA (ISW), 1.4MHz High Efficiency Step-Up DC/DC Converter VIN: 0.9V to 10V, VOUT(MAX) = 34V, IQ = 3mA, ISD < 1μA,

ThinSOT Package

LT1618 1.5A (ISW), 1.25MHz High Efficiency Step-Up DC/DC Converter VIN: 1.6V to 18V, VOUT(MAX) = 35V, IQ = 1.8mA, ISD < 1μA,

MS10 Package

LT1930/LT1930A 1A (ISW), 1.2MHz/2.2MHz High Efficiency Step-Up DC/DC

Converter

VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2mA/5.5mA, ISD < 1μA,

ThinSOT Package

LT1931/LT1931A 1A (ISW), 1.2MHz/2.2MHz High Efficiency Inverting DC/DC

Converter

VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2mA/5.5mA, ISD < 1μA,

ThinSOT Package

LT1935 2A (ISW), 40V, 1.2MHz High Efficiency Step-Up DC/DC Converter VIN: 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1μA,

ThinSOT Package

LT1944/LT1944-1

(Dual)

Dual Output 350mA (ISW), Constant Off-Time, High Efficiency

Step-Up DC/DC Converter

VIN: 1.2V to 15V, VOUT(MAX) = 34V, IQ = 20μA, ISD < 1μA,

MS10 Package

LT1945 (Dual) Dual Output Pos/Neg 350mA (ISW), Constant Off-Time,

High Efficiency Step-Up DC/DC Converter

VIN: 1.2V to 15V, VOUT(MAX) = ±34V, IQ = 20μA, ISD < 1μA,

MS10 Package

LT1946/LT1946A 1.5A (ISW), 1.2MHz/2.7MHz High Efficiency Step-Up DC/DC

Converter

VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 3.2mA, ISD < 1μA,

MS8E Package

LT1961 1.5A (ISW), 1.25MHz High Efficiency Step-Up DC/DC Converter VIN: 3V to 25V, VOUT(MAX) = 35V, IQ = 0.9mA, ISD < 6μA,

MS8E Package

LT3436 3A (ISW), 800kHz, 34V Step-Up DC/DC Converter VIN: 3V to 25V, VOUT(MAX) = 34V, IQ = 0.9mA, ISD < 6μA,

TSSOP16E Package

LT3467 1.1A (ISW), 1.3MHz High Efficiency Step-Up DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 40V, IQ = 1.2mA, ISD < 1μA,

ThinSOT, 2mm × 3mm DFN Packages

LT3477 42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED Driver VIN: 2.5V to 25V, VOUT(MAX) = 40V, Analog/PWM, ISD < 1μA,

QFN, TSSOP20E Packages

LT3479 3A Full-Featured DC/DC Converter with Soft-Start and Inrush

Current Protection

VIN: 2.5V to 24V, VOUT(MAX) = 40V, Analog/PWM, ISD < 1μA,

DFN, TSSOP Packages

2MHz Inverting Converter Generates –12V from a 5V to 12V Input Efficiency and Power Loss

vs Load Current

10μF

VOUT

–12V

500mA (VIN = 12V)

350mA (VIN = 5V)

10μH

1μF

147k

VIN

5V TO 12V

VIN SW

3580 TA09a

LT3580

45.3k

10k

SHDN GND

SYNC SS

2.2nF

47pF

0.1μF

2.2μF

C1: 2.2μF, 25V, X5R, 1206

C2: 10μF, 25V, X5R, 1206

C3: 1μF, 50V, X5R, 0805

D1: CENTRAL SEMI CMMSH1-40

L1: SUMIDA CDRH6D28NP-100NC

L2: SUMIDA CDRH3D28NP-220NC

22μH

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mw)

400

3580 TA09b

50 100 200 300

50 150 250 350

600

1000

200

1400

400

800

1200

VIN = 5V