CY37032V
PRELIMINARY
2
Functional Description
The CY37032 V is a n In-Sys tem Reprog ram mable (ISR) Com-
plex Programmable Logic Device (CPLD) and is part of the
Ultra37000™ family of high-density, high-speed CPLDs. Li ke
all members of the Ultra37000 family, the CY37032V is de-
signed to bring the ease of use and high perfor mance of the
22V10 to high-density PLDs.
The CY37032V is rich in I/O resources. Each macrocell in the
device features an associated I/O pin, resul ting in 32 I/O pins
on the CY37032V.
For a more detailed description of the architecture and fea-
tures of the CY3 7032V see the Ultra37000 family data sheet .
Fully Routable with 100% Logic Utili zation
The CY37032V is designed with a robust routing architecture
which allows utili zation of the ent ire de vice wi th a fixed pi nout.
This mak es Ul tra3 7000 optimal f o r impl ement ing on -boa rd de-
sign changes using ISR without changing pinouts.
Simple Timing Model
The CY37032V features a very simple tim ing m odel with pre-
dict able dela ys. Unlike other high-densi ty CPLD architec tures ,
ther e are no hidden spe ed dela ys such as f anout eff ects, inte r-
connect delays, or expander delays. The timing model allows
for design changes with I SR without causing changes to sys-
tem performance.
Low-Power Operation
Each Logic Block of the CY37032V can be configured as either
High-Speed (default) or Low-Power. In the Low-Power mode,
the logic bl ock consumes approximately 50% less power and
slows down by tLP
.
Output Slew Rate Cont rol
Each output can be configured with either a fast edge rate
(default ) for high perfor mance, or a slow edge rate for added
noise reduction. In the fast edge rate mode, outputs switch at
3V/ns m ax. and in the slow edge rate mode, out puts switch a t
1V/ns max. There is a nominal delay for I/Os using the slow
edge rate mode.
In-System Reprogramming
The CY37032V can be programmed in system using IEEE
1149.1 compliant JTAG programming protocol. The
CY37032V ca n also be prog rammed on a nu mber of tr aditional
parallel programmers including Cypress’s
Impulse3
pro-
grammer and industry standard thi rd-party programmers. For
an ov erview of ISR prog ramming, refer to the Ult ra37000 F am-
ily data sheet and for UltraISR cable and software specifica-
tions, refer to InSRkit: ISR Programming data sheet
(CY3600i).
User-Programm able Bus Hold
All out puts of the CY37032 V can either be conf igure d into b us
hold mode or l eft floating. Wh en in b us hold mode, t he undriv-
en outpu ts retai n their last value with a wea k latch. This f eature
allo ws the design er the flexibility of eith er eliminating or includ -
ing external pull-up/pull-down resistors. Enabling this feature
affects all I/Os si multaneously.
Design Tools
Development soft w are f or t he CY37032V is av ai lab le fr om Cy-
pre ss’s
Warp
or t hird- party bol t-i n sof tw are pa c kages as w ell
as a numbe r of third-party de velopment packages. Please re-
fer to the
Warp
or third- par ty tool suppor t data sheet s for fur-
ther informatio n .