CXK5T8512TM-TN-12LLX - Sony Semiconductor

– 1 –

CXK5T8512TM/TN-10LLX/12LLX

PE96727-PS

65536-word ×8-bit High Speed CMOS Static RAM

Description

The CXK5T8512TM/TN is a high speed CMOS

static RAM organized as 65536-words by 8-bits.

Special feature are low power consumption and

high speed.

The CXK5T8512TM/TN is a suitable RAM for

portable equipment with battery back up.

Features

•Extended operating temperature range:

–25 to +85°C

•Wide supply voltage range operation: 2.7 to 3.6V

•Fast access time: (Access time)

3.0V operation

CXK5T8512TM/TN-10LLX 100ns (Max.)

CXK5T8512TM/TN-12LLX 120ns (Max.)

3.3V operation

CXK5T8512TM/TN-10LLX 85ns (Max.)

CXK5T8512TM/TN-12LLX 100ns (Max.)

•Low standby current: 14µA (Max.)

•Low data retention current: 12µA (Max.)

•Low power data retention: 2.0V (Min.)

•Package line-up

CXK5T8512TM

8mm ×20mm 32 pin TSOP package

CXK5T8512TN

8mm ×13.4mm 32 pin TSOP package

Function

65536-word ×8-bit static RAM

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

VCC

GND

CE1

CE2

Row

Decoder

Buffer

I/O Buffer

A15

A13

A8

A11

A9

A7

A6

A5

A14

A12

A4

A3

A10

A0

A1

OE

WE

Buffer I/O Gate

Column

Decoder

Memory

Matrix

1024 × 512

A2

I/O1 I/O8

Block Diagram

CXK5T8512TM

32 pin TSOP (Plastic) CXK5T8512TN

32 pin TSOP (Plastic)

Preliminary

For the availability of this product, please contact the sales office.

– 2 –

CXK5T8512TM/TN

Address input

Data input output

Chip enable 1, 2 input

Write enable input

Output enable input

Power supply

Ground

No connection

Symbol Description

Supply voltage

Input voltage

Input and output voltage

Allowable power dissipation

Operating temperature

Storage temperature

Soldering temperature · time

VCC

VIN

VI/O

PD

Topr

Tstg

Tsolder

–0.5 to +4.6

–0.5∗1to VCC + 0.5

0.7

–25 to +85

–55 to +150

235 · 10

V

W

°C

°C · s

Item Symbol Rating Unit

Absolute Maximum Ratings (Ta = 25°C, GND = 0V)

∗1VIN, VI/O = –3.0V Min. for pulse width less than 50ns.

Pin Description

A0 to A15

I/O1 to I/O8

CE1, CE2

WE

OE

VCC

GND

NC

OE

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

GND

I/O3

I/O2

I/O1

A0

A1

A2

A3

A11

A9

A8

A13

WE

CE2

A15

Vcc

NC

A14

A12

A7

A6

A5

A4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16 18

19

20

21

22

23

24

25

26

27

28

29

30

32

31

17

CXK5T8512TM

(Standard Pinout)

Pin Configuration (Top View)

H

×

L

×

L

H

×

H

L

×

H

L

Not selected

Output disable

Read

Write

High Z

Data out

Data in

ISB1, ISB2

ICC1, ICC2, ICC3

CE1 CE2 OE WE Mode I/O pin VCC Current

Truth Table

×:

“

H” or “L”

OE

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

GND

I/O3

I/O2

I/O1

A0

A1

A2

A3

A11

A9

A8

A13

WE

CE2

A15

Vcc

NC

A14

A12

A7

A6

A5

A4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16 18

19

20

21

22

23

24

25

26

27

28

29

30

32

31

17

CXK5T8512TN

(Standard Pinout)

– 3 –

CXK5T8512TM/TN

DC Recommended Operating Conditions (Ta = –25 to +85°C, GND = 0V)

∗1VIL = –3.0V Min. for pulse width less than 50ns.

Input leakage current

Output leakage current

Operating power supply

current

ILI

ILO

ICC1

VIN = GND to VCC

CE1 = VIH or CE2 = VIL or

OE = VIH or WE = VIL

VI/O = GND to VCC

CE1 = VIL, CE2 = VIH

VIN = VIH or VIL

IOUT = 0mA

10LLX

12LLX

–25 to +85°C

–25 to +70°C

+25°C

–1

—

—510

—

0.24

0.12

14

7

—

1.4

µA

mA

—

1

25∗2

25

+1

3

35∗3

35

µA

mA

Item Symbol Min. Typ.∗1Max. UnitTest conditions

Electrical Characteristics

• DC Characteristics (VCC = 2.7 to 3.6V, GND = 0V, Ta = –25 to +85°C)

∗1VCC = 3.3V, Ta = 25°C

∗2ICC2 = 30mA for 3.3V operation (VCC = 3.3V ± 0.3V)

∗3ICC2 = 40mA for 3.3V operation (VCC = 3.3V ± 0.3V)

Average operating current

Output high voltage

Output low voltage

Standby current

ICC2

ICC3

ISB1

ISB2

VOH

VOL

Min. cycle

duty = 100%

IOUT = 0mA

Cycle time 1µs

duty = 100%

IOUT = 0mA

CE1 ≤0.2V

CE2 ≥Vcc – 0.2V

VIL ≤0.2V

VIH ≥Vcc – 0.2V

CE1 = VIH or CE2 = VIL

IOL = 2.0mA

2.4

—

0.4

V

IOH = –2.0mA

CE2 ≤0.2V

CE1 ≥Vcc – 0.2V

or

{

CE2 ≥Vcc – 0.2V

Supply voltage

Input high voltage

Input low voltage

Item Symbol Min. VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V

Typ. Max. Unit

VCC

VIH

VIL

2.7

2.4

–0.3∗1

3.3

—

3.6

VCC + 0.3

0.4

Min. Typ. Max.

3.0

2.2

–0.3∗1

3.3

—

3.6

VCC + 0.3

0.6

V

– 4 –

CXK5T8512TM/TN

Input capacitance

I/O capacitance

Item Symbol Test conditions Min. Typ. Max. Unit

CIN

CI/O

—

8

10

pF

VIN = 0V

VI/O = 0V

AC Characteristics

• AC test conditions (Ta = –25 to +85°C)

I/O capacitance (Ta = 25°C, f = 1MHz)

Note) This parameter is sampled and is not 100% tested.

TTL

CL

•Test circuit

Input pulse high level

Input pulse low level

Input rise time

Input fall time

Input and output reference level

-10LLX

Output load conditions -12LLX

VIH = 2.4V

VIL = 0.4V

tr = 5ns

tf = 5ns

1.4V

CL∗1= 100pF, 1TTL

Item VCC = 2.7 to 3.6V

Conditions

VIH = 2.2V

VIL = 0.6V

tr = 5ns

tf = 5ns

1.4V

CL∗1= 30pF, 1TTL

CL∗

1

= 100pF, 1TTL

VCC = 3.3V ± 0.3V

∗1CLincludes scope and jig capacitances.

– 5 –

CXK5T8512TM/TN

• Read cycle (WE = “H”)

∗1tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not

referred to as output voltage levels.

∗2tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as

output voltage level.

• Write cycle

Item Symbol

Min. Max. Min. Max.

-10LLX

VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V

-12LLX Unit

tRC

tAA

tCO1

tCO2

tOE

tOH

tLZ1

tLZ2

tOLZ

tHZ1∗1

tHZ2∗1

tOHZ∗1

100

—

10

5

—

100

50

—

40

35

120

—

10

5

—

120

60

—

40

35

Min. Max. Min. Max.

-10LLX -12LLX

85

—

10

5

—

85

40

—

35

30

100

—

10

5

—

100

50

—

40

35

Read cycle time

Address access time

Chip enable access time (CE1)

Chip enable access time (CE2)

Output enable to output valid

Output hold from address change

Chip enable to output in low Z

(CE1, CE2)

Output enable to output in low Z (OE)

Chip disable to output in high Z

(CE1, CE2)

Output disable to output in high Z (OE)

ns

Item Symbol

Min. Max. Min. Max.

-10LLX

VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V

-12LLX Unit

tWC

tAW

tCW

tDW

tDH

tWP

tAS

tWR

tWR1

tOW

tWHZ∗2

100

80

40

0

70

0

5

—

40

120

100

50

0

70

0

5

—

40

Min. Max. Min. Max.

-10LLX -12LLX

85

70

35

0

60

0

5

—

35

100

80

40

0

70

0

5

—

40

Write cycle time

Address valid to end of write

Chip enable to end of write

Data to write time overlap

Data hold from write time

Write pulse width

Address setup time

Write recovery time (WE)

Write recovery time (CE1, CE2)

Output active from end of write

Write to output in high Z

ns

– 6 –

CXK5T8512TM/TN

• Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH

Address

tAA

tRC

tOH

Data out Previous data valid Data valid

• Read cycle (2) : WE = VIH

Address

tAA

tRC

tLZ2

tOHZ

tOE

tOLZ

CE1

OE

Data out High impedance Data valid

tCO1 tHZ

tLZ1 tHZ1

tHZ2

tCO2

CE2

Timing Waveform

– 7 –

CXK5T8512TM/TN

• Write cycle (1) : WE control

Address

tAW

tWC

tCW

tDH

tWHZ

tDW

CE1

WE

Data out High impedance

Data valid

tOW

(∗2)(∗2)

OE

Data in

tWR

tAS tWP (∗1)

tCW

CE2

• Write cycle (2) : CE1 control

Address

OE

tWC

tAW

Data valid

tAS tCW tWR1

tWP

tDW tDH

High impedance

CE1

WE

Data out

Data in

tCW

(∗3)

CE2

– 8 –

CXK5T8512TM/TN

• Write cycle (3) : CE2 control

Address

OE

tWC

tAW

Data valid

tCW

tWR1

tWP

tDW tDH

High impedance

CE1

WE

Data out

Data in

tAS tCW (∗3)

CE2

∗1Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.

∗2Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.

∗3tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until

the end of the write cycle.

– 9 –

CXK5T8512TM/TN

∗1

–25 to +85°C

–25 to +70°C

+25°C

VCC = 2.0 to 3.6V∗1

Chip disable to data retention mode

Data retention voltage

Data retention setup time

Recovery time

VDR

ICCDR1

ICCDR2

tCDRS

tR

2.0

—

0

5

—

0.2

0.24∗2

—

3.6

12

6

—

14

—

V

µA

ns

ms

Item Symbol Test conditions Min. Typ. Max. Unit

Data Retention Characteristics (Ta = –25 to +85°C)

∗1CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control)

∗2Vcc = 3.3V, Ta = 25°C

Data retention current VCC = 3.0V∗1

Data retention waveform

• Low supply voltage data retention waveform (1) (CE1 contol)

VCC

2.7V

VIH

VDR

CE1

GND

tCDRS Data retention mode

CE1 ≥ VCC – 0.2V

• Low supply voltage data retention waveform (2) (CE2 contol)

tR

Data retention mode

tRtCDRS

CE2 ≤ 0.2V

VCC

2.7V

VIL

CE2

GND

VDR

– 10 –

CXK5T8512TM/TN

Package Outline Unit: mm

CXK5T8512TM

CXK5T8512TN

SONY CODE

EIAJ CODE

JEDEC CODE

TSOP-32P-L01

TSOP032-P-0820

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

42 ALLOY

SOLDER PLATING

EPOXY RESIN

32PIN TSOP (PLASTIC)

M

0.08 0.5

0.2 – 0.03

+ 0.08 16

1

17

32

8.0 ± 0.2

∗18.4 ± 0.2

20.0 ± 0.2

1.07 – 0.1

+ 0.2

0.127 – 0.02

+ 0.05

0.1 ± 0.1

0.5 ± 0.1

0° to 10°

A

0.1

DETAIL A

NOTE : “∗” Dimensions do not include mold protrusion.

0.3g

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER PLATING

42 ALLOY

∗8.0 ± 0.1

∗11.8 ± 0.1

13.4 ± 0.3

1.2 MAX

0.5

0° to 10°

0.05 – 0.05

+ 0.1

0.145

A

0.1

DETAIL A

0.2g

NOTE: Dimension “∗” does not include mold protrusion.

M

0.08 0.5

0.2

1

32

16

17

32PIN TSOP (PLASTIC)

TSOP-32P-L02

TSOP032-P-0813.4-C