FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 1.0 * Figure 1: Block Diagram Features Generates the Host and Memory clocks required for 2-way and 4-way multi-processor (MP) clockpartitioned platforms, including: M Six differential current-mode Host clock pairs M Two 3.3V Memory Reference clocks M 66.67MHz and 14.318MHz 3.3V Reference clocks for the FS6159 device M Three optional 33.3MHz 1.8V APIC clocks * Control of current-mode Host clocks via IREF current programming pin and ISEL_0:1 current multiplier pins * Optional APIC clocks enabled via APICON input (see Table 5 for Pins 21-23 configuration) * * Spread-spectrum modulation (-0.5% at 31.5kHz) of Host, Memory, APIC, and 66MHz Reference clocks, enabled via SS_EN# input * Supports test mode and tristate output control to facilitate board testing * Available in a 48-pin SSOP and TSSOP PHASE adjust IREF VDD_H VSS_H /3 66REF PLL MREF_N 1 66REF 1 3.3V 3.3V VDD_M SKEW (MAX) VDD_66 0 100ps 180 Pair to Pair 0 66.67 50.00 180 66.67 0 /4 VSS_66 VDD_M Control MREF_P MREF_N /4 APICON /6 APIC_0:2 FS6158 /8 VSS_A optional Figure 2: Pin Configuration VSS_R 1 48 VDD_R 14REF 2 47 VSS / APICON VDD_R 3 46 VDD_H XIN 4 45 HOST_P1 XOUT 5 44 HOST_N1 VSS_R 6 43 VSS_H VDD_M 7 42 HOST_P2 MREF_P 8 41 HOST_N2 MREF_N 9 40 VDD_H VDD 11 VSS 12 VDD_66 13 66REF 14 - VDD_A VSS_66 15 39 HOST_P3 38 HOST_N3 37 VSS_H 36 HOST_P4 35 HOST_N4 34 VDD_H 33 HOST_P5 - ISEL_0 17 32 HOST_N5 ISEL_1 18 31 VSS_H VDD_A 19 30 HOST_P6 VSS_A 20 29 HOST_N6 14REF 1 3.3V VDD_R 14.318 0 - APIC (optional) 3 1.8V VDD_A 33.33 0 - SEL_A / APIC_0 21 28 VDD_H SEL_B / APIC_1 22 27 IREF SS_EN# / APIC_2 23 26 VSS_I PWR_DWN# 24 25 VDD_I Pair 6 SEL133/100# 16 Pair 5 1 133.33 100.00 VDD_66 Pair 4 MREF_P VDD_H HOST_N1:6 Pair 3 6 3.3V /2 FS6158-01 HOST_N 6 HOST_P1:6 PWR_DWN# VSS_M 10 HOST_P /1 Pair 2 FREQ. (MHz) VSS_R Pair 1 Table 1: Clock Parameters SUPPLY GROUP 14REF VSS_M * SUPPLY VOLTAGE VDD_R Crystal Oscillator ISEL_0:1 SEL133/100# SEL_A:B Active-low PWR_DWN# signal allows one complete clock cycle on each clock outputs and then shuts down the crystal oscillator, PLL, and disables outputs # PINS XOUT SS_EN# Host clock frequency selection via the SEL_A, SEL_B, and SEL133/100# pins CLOCK GROUP XIN Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. ISO9001 9.18.00 IntWBY FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 2: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active-low pin PIN TYPE NAME DESCRIPTION SUPPLY 47 DI APICON APIC_0 21 DIO 22 DIO 23 DIO 2 14 DO DO 14REF 66REF VDD_R VDD_A VDD_A, VDD_H VDD_A VDD_A, VDD_H VDD_A VDD_A, VDD_H VDD_R VDD_66 27 AI IREF 17, 18 DI 45, 44 AO 42, 41 AO Host clock pair #2; one of six pairs of current-steering differential current-mode outputs VDD_H 39, 38 AO Host clock pair #3; one of six pairs of current-steering differential current-mode outputs VDD_H 36, 35 AO Host clock pair #4; one of six pairs of current-steering differential current-mode outputs VDD_H 33, 32 AO Host clock pair #5; one of six pairs of current-steering differential current-mode outputs VDD_H 30, 29 AO Host clock pair #6; one of six pairs of current-steering differential current-mode outputs VDD_H 8 DO ISEL_0 ISEL_1 HOST_P1 HOST_N1 HOST_P2 HOST_N2 HOST_P3 HOST_N3 HOST_P4 HOST_N4 HOST_P5 HOST_N5 HOST_P6 HOST_N6 MREF_P Enables (logic-high) or disables (logic-low) the optional 1.8V APIC clocks One of three optional APIC clocks, enabled or disabled by APICON One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high. One of three optional APIC clocks, enabled or disabled by APICON One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high. One of three optional APIC clocks, enabled or disabled by APICON Active-low spread spectrum enable turns on spread spectrum modulation of PLL clocks. Input levels are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high. One 14.318MHz clock output, provided as a reference clock to the companion clock device One 66.67MHz clock output, provided as a reference clock to the companion clock device A fixed precision resistor from this pin to ground provides a reference current used for the differential current-mode HOST clock outputs The logic setting on these two pins selects the multiplying factor of the IREF reference current for the HOST pair outputs Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1 VDD_M 9 DO MREF_N 24 DI PWR_DWN# 16 11 19 13 28, 34, 40, 46 25 7 3, 48 12 15 20 31, 37, 43 26 10 1, 6 4 5 DI P P P P P P P P P SEL133/100# VDD VDD_A VDD_66 VDD_H VDD_I VDD_M VDD_R VSS VSS_66 VSS_A VSS_H VSS_I VSS_M VSS_R XIN XOUT One clock in a pair of outputs provided as a reference clock to a memory clock driver One clock (180 out of phase with MREF_P) in a pair of outputs provided as a reference clock to a memory clock driver Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all clocks in low state. Complete clock cycles on all outputs will occur before shut down begins. Selects 133MHz or 100MHz Host clock frequency 3.3V core power supply 1.8V power supply for optional APIC clocks or a 3.3V supply to pins 21-23 3.3V power supply for 66REF clock output 3.3V power supply for the differential HOST clock outputs 3.3V power supply for IREF current reference input 3.3V power supply for MREF clock outputs 3.3V power supply for the 14REF clock output and the crystal oscillator Core Ground Ground for the 66REF clock output Ground for the APIC clock outputs Ground for the differential HOST clock outputs Ground for IREF current reference input Ground for the MREF clock outputs Ground for the 14REF clock output and the crystal oscillator 14.318MHz crystal oscillator input 14.318MHz crystal oscillator output SEL_A APIC_1 SEL_B APIC_2 ISO9001 P P P P AI AO SS_EN# VDD_I VDD_66 VDD_H VDD_M VDD_I VDD_66 VDD_R VDD_R 9.18.00 2 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 2.0 Programming Information Table 3: Function/Clock Enable Configuration CONTROL INPUTS (2) CLOCK OUTPUTS (MHz) PWR_DWN# SEL133/100# SEL_A SEL_B HOST_P1:6 HOST_N1:6 MREF_P, MREF_N 66REF APIC_0:2 (optional) 14REF 1 0 0 0 100.00 100.00 50.00 66.67 33.33 14.318 (1) (1) (1) 1. low low low low (1) 1 0 0 1 100.00 100.00 1 0 1 0 reserved reserved reserved reserved reserved 1 0 1 1 tristate tristate tristate tristate tristate tristate 1 1 0 0 133.33 133.33 66.67 66.67 33.33 14.318 1 1 0 1 reserved reserved reserved reserved reserved reserved 1 1 1 0 reserved reserved reserved reserved reserved reserved 1 1 1 1 XIN/2 XIN/2 XIN/4 XIN/4 XIN/8 XIN 0 X X X 2x IREF tristate low low low low reserved Certain clock outputs may be disabled through a combination of SEL_A, SEL_B, and SEL133/100# logic states as defined in Table 3. Enabled clocks will continue to run while disabled clocks are stopped low. Note that if clocks are disabled while active, glitches may occur. Table 4: Synthesis Error 3.0 TARGET (MHz) ACTUAL (MHz) DEVIATION (ppm) HOST_P1:6, HOST_N1:6 100.0000 99.9963 -36.657 133.3333 133.3072 -195.924 MREF_P, MREF_N 50.0000 49.9982 -36.657 66.6667 66.6536 -195.924 CLOCK 66REF 66.6667 66.6642 -36.657 APIC_0:2 33.3333 33.3321 -36.657 1. 48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB standards. 2. Spread spectrum is disabled The current supplied at the HOST outputs is controlled by two parameters: 1) the value of the programming resistor from the IREF pin to ground (VSS), and 2) the multiplier factor determined by the logic setting of the ISEL_0 and ISEL_1 pins. 3.1 Current Reference The HOST output current is a mirrored and scaled copy of the reference current flowing through the programming resistor on the IREF pin. Conceptually, the circuit given in Figure 2 shows how the mirror current is generated. The voltage that appears at the IREF pin is one-third of the voltage at the VDD_I pin. The reference current is Table 5: APICON Control APICON HOST Buffer Current Control FREQUENCY SELECT CONTROL / APIC CLOCKS PIN 47 PIN 21 PIN 22 PIN 23 0 SEL_A Input (LVTTL) SEL_B Input (LVTTL) SS_EN# Input (LVTTL) 1 APIC_0 Output / SEL_A Latched Input APIC_1 Output / SEL_B Latched Input APIC_2 Output / SS_EN# Latched Input I REF 3.2 1 x VDD_I 3 . = RIREF Current Scaling The mirrored reference current can be increased by adding one or more copies of the mirror current together. The additional current is controlled by the logic settings on the ISEL_0 and ISEL_1 pins. ISO9001 9.18.00 3 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 6: Current Multiplier ISEL_0 Table 8: HOST Buffer Clock Outputs ISEL_1 MULTPLIER HIGH DRIVE CURRENT (mA) AT PRIMARY SYSTEM CONFIGURATION Output Voltage (V) 0 0 IO = 5 x IREF 0 1 IO = 6 x IREF 1 0 IO = 4 x IREF 3.30 0.00 0.00 0.00 IO = 7 x IREF 3.14 -3.03 -4.22 -5.76 2.97 -5.66 -7.68 -9.86 2.81 -7.87 -10.30 -11.85 1 1 MIN. Figure 2: Current Reference Circuit 1.1V Mirror Current R IREF Reference Current IREF HOST_N RIREF -9.67 -11.91 -12.45 2.48 -11.05 -12.56 -12.84 Additional Mirror Current 2.31 -11.98 -12.85 -13.16 2.14 -12.52 -13.07 -13.45 1.98 -12.77 -13.26 -13.72 ISEL_0:1 1.81 -12.91 -13.42 -13.96 1.65 -12.99 -13.54 -14.17 1.48 -13.04 -13.64 -14.36 1.32 -13.07 -13.70 -14.52 1.15 -13.08 -13.73 -14.64 0.99 -13.09 -13.75 -14.71 0.82 -13.11 -13.76 -14.74 0.66 -13.12 -13.78 -14.76 0.49 -13.13 -13.79 -14.78 0.33 -13.13 -13.80 -14.80 0.16 -13.14 -13.81 -14.82 0.00 -13.15 -13.82 -14.83 HOST_P RS RS RP RP Table 7: HOST Current Selection REFERENCE CURRENT CURRENT MULTIPLIER IREF 475 (1%) 2.32mA IO = 5 x IREF 475 (1%) 2.32mA IO = 6 x IREF 475 (1%) 2.32mA IO = 4 x IREF 475 (1%) 2.32mA IO = 7 x IREF 221 (1%) 5mA IO = 5 x IREF 221 (1%) 221 (1%) 221 (1%) 5mA 5mA 5mA TRACE IMPEDANCE OUTPUT VOLTAGE 60 0.71V 50 0.59V 0 60 0.85V -2 50 0.71V -4 60 0.56V 50 0.47V 60 0.99V 50 0.82V 30 0.75V 25 0.62V 30 0.90V 25 0.75V 30 0.60V 25 0.50V 30 1.05V 25 0.84V IO = 6 x IREF IO = 4 x IREF IO = 7 x IREF Output Voltage (V) 0 Output Current (mA) PROGRAM RESISTOR RIREF 1 2 3 -6 -8 -10 -12 -14 -16 -18 -20 30 50 90 Max VOH NOTE: Shaded row indicates the Primary System Configuration ISO9001 MAX. 2.64 VDD_I (3.3V) 2R TYP. Data in this table represents nominal characterization data only 9.18.00 4 FS6158-01 AMERICAN MICROSYSTEMS, INC. Two-Way/Four Way Motherboard Clock Generator/Buffer IC September 2000 4.0 Table 9: Latency Table Power Management The PWR_DWN# signal is an asynchronous, active-low LVTTL input that places the device in a low power inactive state without removing power from the device. All internal clocks are turned off, and all clock outputs are held low. Since PWR_DWN# is asynchronous, the signal is synchronized internally to each individual clock. As shown in Figure 3, a falling-rising-falling edge sequence on any individual clock output is required before that clock output is disabled low. This edge sequence ensures that one complete clock cycle will occur before the clock stops. PWR_ DWN# LATENCY SIGNAL STATE SIGNAL 0 Power OFF 1 Power ON MIN. MAX. Output: 2 clocks 3 clocks Device: 2x 14REF clocks 3x 14REF clocks 3ms Upon the release of PWR_DWN# (power-up), external circuitry should allow a minimum of 3ms for the PLL to lock before enabling any clocks. Figure 3: PWR_DWN# Timing Any Clock (internal) PWR_DWN# Any Clock (output) After 14REF output shuts off... 3ms until clock is valid VCO Crystal Oscillator Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active. 5.0 Figure 4: I/O Pin Programming Dual Function I/O Pins Several pins on this device serve as dual function input/output pins. During the initial application of VDD to the device, this type of pin functions as an input pin. Upon completion of power-up, the logic state present on the pin is latched internally, and the pin is converted to an output driver. An external 10k pull-down resistor to ground is required for a logic low and a 10k pull-up resistor to the clock output VDD is required for a logic high. The 10k resistor presents an insignificant load to the output driver that should not affect the output clock. Note that the latching of the logic state occurs only on the application of the chip supply voltage (VDD). The logic state on the pin is not latched if the PWR_DWN# signal is used to power-down the device with VDD still applied. ISO9001 Termination Resistor Clock Trace Device Solder Pads 10k Programming Resistor Ground or Power Via 9.18.00 5 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 6.0 Electrical Specifications Table 10: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER SYMBOL MIN. Supply Voltage (VSS = ground) MAX. UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 125 C Junction Temperature TJ 125 C Lead Temperature (soldering, 10s) 260 C 2 kV Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 11: Operating Conditions PARAMETER SYMBOL Supply Voltage VDD Operating Temperature Range TA Crystal Resonator Frequency fXTAL Crystal Resonator Load Capacitance CXL Load Capacitance Load Resistance ISO9001 CL RL CONDITIONS/DESCRIPTION MIN. TYP. MAX. Core (VDD) 3.135 3.3 3.465 Clock Buffers (VDD_66, VDD_H, VDD_I, VDD_M, VDD_R) 3.135 3.3 3.465 APIC Clock Buffers (VDD_A) 1.65 1.8 1.95 0 XIN, XOUT pins UNITS V 70 C 14.316 14.318 14.32 MHz 13.5 18 22.5 pF MREF_P, MREF_N 10 30 APIC_0:2 10 20 66REF 10 20 14REF 10 20 HOST_P1 to HOST_P6, HOST_N1 to HOST_N6 20 105 pF 9.18.00 6 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 12: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Supply Current, Dynamic, with Loaded Outputs IDD fHOST = 133MHz; all supplies = 3.465V, RIREF= 475, IOH = 6 x IREF mA Supply Current, Static IDDs PWR_DWN# low, all supplies = 3.465V, RIREF= 475, IOH = 6 x IREF A Overall Digital Inputs (PWR_DWN#, ISEL_0, ISEL_1, SEL133/100#) High-Level Input Voltage VIH 2.0 VDD+0.3 V Low-Level Input Voltage VIL VSS-0.3 0.8 V Input Leakage Current IIL -5 +5 A Crystal Oscillator Feedback (XIN) Threshold Bias Voltage VTH 1.5 V High-Level Input Current IIH VIH = 3.3V 32 A Low-Level Input Current IIL VIL = 0V -32 A Crystal Loading Capacitance * CL(xtal) As seen by an external crystal connected to XIN and XOUT Input Loading Capacitance * CL(XIN) As seen by an external clock driver on XOUT; XIN unconnected 36 13.5 18 22.5 pF pF Crystal Oscillator Drive (XOUT) High Level Output Source Current IOH VI (XIN) = 3.3V, VO = 0V -8.0 mA Low Level Output Sink Current IOL VI (XIN) = 0V, VO = 3.3V 8.7 mA Bias Voltage VOH no load 1.1 Short Circuit Output Source Current IOH VO = 0V Current Reference (IREF) V mA MREF_P, MREF_N, 14REF, and 66REF Clock Outputs (Type 5 Clock Driver) IOH min VDD_M, VDD_R, VDD_66 = 3.135V, VO = 1.0V IOH max VDD_M, VDD_R, VDD_66 = 3.465V, VO = 3.135V IOL min VDD_M, VDD_R, VDD_66 = 3.135V, VO = 1.95V IOL max VDD_M, VDD_R, VDD_66 = 3.465V, VO = 0.4V zOL Measured at 1.65V, output driving low 12 55 zOH Measured at 1.65V, output driving high 12 55 High Level Output Source Current Low Level Output Sink Current Output Impedance -33 mA -33 30 mA 38 10 A Tristate Output Current IOZ Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -51 mA Short Circuit Output Sink Current IOSL VO = 3.3V; shorted for 30s, max. 62 mA ISO9001 -10 9.18.00 7 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 13: DC Electrical Specifications, continued Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 55 %VOH HOST_P1:4, HOST_N1:4 Clock Outputs (Type X1 Clock Buffer) Crossover Voltage VX High-Level Output Source Current IOH Output Source Current Tolerance IOH Output Impedance zOH Tristate Output Current IOZ RS = 33.2, RP = 49.9, RIREF = 475, IOH = 6 x IREF VO = 0.65V, RIREF = 475, IOH = 6 x IREF 45 12.9 VO = 0.74V, RIREF = 475, IOH = 6 x IREF 14.9 VDD = 3.30V, over settings in Table 7 -7 +7 VDD_I=3.3V5%, over settings in Table 7 -12 +12 VO/IO, where VO1 = 1.0V, VO2 = VSS, RIREF = 475, IOH = 6 x IREF mA %IOH 3000 -10 10 A SEL_A / APIC_0, SEL_B / APIC_1, and SS_EN# / APIC_3 Latched Inputs / Clock Outputs (1.8V Clock Buffer) High-Level Input Voltage Input Low-Level Input Voltage VIH VIL VDD_A = 3.3V, LVTTL Input (APICON=0) 2.0 VDD+0.3 VDD_A = 1.8V, Latched Input (APICON=1) 1.17 VDD+0.3 VDD_A = 3.3V, LVTTL Input (APICON=0) VSS-0.3 0.8 VDD_A = 1.8V, Latched Input (APICON=1) VSS-0.3 0.63 -5 +5 IIL High Level Output Source Current IOH VDD_A = 1.8V, VO = 1.4V Low Level Output Sink Current IOL VDD_A = 1.8V, VO = 0.4V 24 zOL Measured at 0.7V, output driving low 11 37 zOH Measured at 0.7V, output driving high 18 41 Output Impedance Tristate Output Current Output Input Leakage Current -25 V V A mA mA A IOZ Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -97 mA Short Circuit Output Sink Current IOSL VO = 1.8V; shorted for 30s, max. 64 mA ISO9001 9.18.00 8 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 14: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Spread Spectrum Modulation Frequency * fm SS_EN# low 31.5 kHz Spread Spectrum Modulation Index * m SS_EN# low -0.5 % 10 ns Tristate Enable Delay * tDZL, tDZH SEL_A:B=00, SEL133/100#=0 1.0 Tristate Disable Delay * tDLZ, tDHZ SEL_A:B=11, SEL133/100#=0 1.0 10 ns tSTB via PWR_DWN# 3.0 ms Clock Skew * tsk(o) HOST pair to HOST pair @ VX, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 100 ps Duty Cycle * dt 55 % Clock Stabilization (on power-up) * HOST_P1:4, HOST_N1:4 Clock Outputs Ratio of high pulse width to one clock period at VX, RIREF = 475, IOH = 6 x IREF, RS=33.2, RP=49.9 Jitter, Long Term (y( )) * tj(LT) On rising edges 500s apart at VX relative to an ideal clock, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 Jitter, Period (peak-peak) * tj(P) Rising edge to rising edge at VX,, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 tr Rising edge to rising edge at VX,, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 Rise Time * 45 ps 175 Rising edge to rising edge at VX,, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 Rise/Fall Time Matching* 150 ps 450 ps 20 % 55 % MREF_P, MREF_N Clock Outputs Duty Cycle * Jitter, Long Term (y( )) * Jitter, Period (peak-peak) * Rise Time * Fall Time * ISO9001 dt Ratio of high pulse width to one clock period, measured at 1.5V tj(LT) On rising edges 500s apart at 1.5V relative to an ideal clock, CL=30pF tj(P) From rising edge to rising edge at 1.5V, CL=30pF tr min Measured @ 0.4V - 2.4V; CL=10pF tr max Measured @ 0.4V - 2.4V; CL=30pF tf min Measured @ 2.4V - 0.4V; CL=10pF tf max Measured @ 2.4V - 0.4V; CL=30pF 45 ps 250 0.4 1.6 0.4 1.6 ps ns ns 9.18.00 9 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 15: AC Timing Specifications, continued Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 55 % 66REF Reference Clock Output Duty Cycle * dt Ratio of high pulse width to one clock period, measured at 1.5V 45 Jitter, Long Term (y( )) * tj(LT) On rising edges 500s apart at 1.5V relative to an ideal clock, CL=20pF Jitter, Period (peak-peak) * tj(P) From rising edge to rising edge at 1.5V, CL=20pF tr min Measured @ 0.4V - 2.4V; CL=10pF tr max Measured @ 0.4V - 2.4V; CL=20pF tf min Measured @ 2.4V - 0.4V; CL=10pF tf max Measured @ 2.4V - 0.4V; CL=20pF Rise Time * Fall Time * ps ps 0.5 2.0 0.5 2.0 ns ns 14REF Reference Clock Output Duty Cycle * dt Jitter, Long Term (y( )) * Jitter, Period (peak-peak) * Rise Time * Fall Time * Ratio of high pulse width to one clock period, measured at 1.5V tj(LT) On rising edges 500s apart at 1.5V relative to an ideal clock, CL=20pF tj(P) From rising edge to rising edge at 1.5V, CL=20pF tr min Measured @ 0.4V - 2.4V; CL=10pF tr max Measured @ 0.4V - 2.4V; CL=20pF tf min Measured @ 2.4V - 0.4V; CL=10pF tf max Measured @ 2.4V - 0.4V; CL=20pF Figure 5: DC Measurement Points VOL = 0.4V 55 % ps ps 0.5 2.0 0.5 2.0 ns ns Figure 6: Timing Diagram 3.3V VOH = 2.4V 45 tr VIH = 2.0V tf 3.3V 2.4V 1.5V VIL = 0.8V 0.4V dt Figure 7: HOST Clock Measurement Point Figure 8: HOST Clock Test Point HOST_P From output under test VX Test node RS RP HOST_N ISO9001 9.18.00 10 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 16: MCLK_P, MCLK_N, 14REF, 66REF Clock Outputs High Drive Current (mA) MIN. TYP. MAX. Voltage (V) 0 0 0 0 0.2 11 17 0.4 21 32 0.6 30 0.8 Voltage (V) Low Drive Current (mA) MIN. TYP. MAX. 150 0 -49 -83 -132 125 24 0.2 -48 -83 -131 100 45 0.4 -48 -82 -130 45 64 0.6 -47 -81 -129 37 56 79 0.8 -47 -80 -127 1.0 43 65 92 1.0 -46 -79 -126 1.2 47 73 103 1.2 -46 -78 -124 1.4 50 78 112 1.4 -45 -76 -121 1.6 53 82 117 1.6 -43 -74 -117 1.8 54 84 120 1.8 -41 -70 -112 2.0 55 85 121 2.0 -37 -65 -105 2.2 55 85 122 2.2 -33 -59 -97 2.4 55 86 123 2.4 -28 -52 -87 -125 2.6 56 86 123 2.6 -22 -43 -74 -150 2.8 56 86 124 2.8 -14 -32 -60 3.0 56 87 124 3.0 -6 -20 -45 87 124 3.2 -7 -27 125 3.4 3.2 3.4 -7 Output Current (mA) 75 50 25 0 -25 0 0.5 1 1.5 2 2.5 3 3.5 -50 -75 -100 30 50 Output Voltage (V) 90 Data in this table represents nominal characterization data only Table 17: APIC_0:2 Clock Outputs High Drive Current (mA) MIN. TYP. MAX. Voltage (V) Low Drive Current (mA) MIN. TYP. 0 0 0 0 0 -40 -67 -97 0.1 3 5 7 0.1 -37 -62 -92 0.2 6 9 13 0.2 -34 -58 -87 0.3 8 13 19 0.3 -31 -53 -82 0.4 11 17 24 0.4 -28 -49 -76 0.5 13 21 29 0.5 -25 -45 -71 0.6 15 24 34 0.6 -22 -41 -66 0.7 17 27 38 0.7 -19 -37 -61 0.8 19 30 42 0.8 -16 -33 -56 0.9 20 32 46 0.9 -14 -29 -51 1.0 21 35 49 1.0 -12 -25 -46 1.2 24 39 55 1.2 -7 -18 -36 1.4 26 41 59 1.4 -3 -11 -26 1.5 26 43 61 1.5 -2 -8 -21 1.6 27 43 62 1.6 -1 -5 -16 1.7 44 63 1.7 -2 -11 1.8 44 64 1.8 0 -7 64 1.9 1.9 ISO9001 100 MAX. -2 75 50 Output Current (mA) Voltage (V) 25 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 -25 -50 -75 30 -100 Output Voltage (V) 50 90 Data in this table represents nominal characterization data only 9.18.00 11 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 7.0 Package Information Table 18: 48-pin SSOP (0.300") Package Dimensions 48 DIMENSIONS INCHES A MILLIMETERS MIN. MAX. MIN. MAX. 0.095 0.110 2.41 2.79 A1 0.008 0.016 0.20 0.41 b 0.008 0.0135 0.20 0.34 c 0.005 0.010 0.13 0.25 D 0.620 0.630 15.75 16.00 E 0.395 0.420 10.03 10.67 E1 0.291 0.299 7.39 7.59 e 0.025 BSC 0.64 BSC h 0.015 0.025 0.38 0.64 L 0.020 0.040 0.51 1.01 0 8 0 8 E1 E AMERICAN MICROSYSTEMS, INC. 1 b SEATING PLANE e A D A1 h x 45 c L Table 19: 48-pin SSOP (0.300") Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS Thermal Impedance, Junction to Free-Air JA Air flow = 0 m/s 93 C/W Lead Inductance, Self L11 Longest lead 5.5 nH L12 Longest lead to any 1st adjacent lead 3.0 L13 Longest lead to any 2nd adjacent lead 2.1 C11 Longest lead to VSS 0.94 Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual ISO9001 st C12 Longest lead to any 1 adjacent lead 0.46 C13 Longest lead to any 2nd adjacent lead 0.05 nH pF pF 9.18.00 12 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 20: 48-pin TSSOP (6.1mm) Package Dimensions DIMENSIONS INCHES MIN. MILLIMETERS MAX. MIN. MAX. A - 0.047 - 1.20 A1 0.002 0.006 0.05 0.15 b 0.0067 0.011 0.17 0.27 c 0.0035 0.008 0.09 0.20 D 0.488 0.496 12.40 12.60 E E1 e 0.318 BSC 0.236 0.244 48 E1 E AMERICAN MICROSYSTEMS, INC. 8.10 BSC 6.00 0.019 BSC 6.20 0.50 BSC L 0.018 0.030 0.45 0.75 S 0.008 - 0.20 - 1 0 8 0 8 2 12 REF 12 REF 3 12 REF 12 REF 1 b SEATING PLANE e A D A1 2 S c 3 L 1 Table 21: 48-pin TSSOP (6.1mm) Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS 89 C/W nH Thermal Impedance, Junction to Free-Air JA Air flow = 0 m/s Lead Inductance, Self L11 Longest lead 3.50 L12 Longest lead to any 1st adjacent lead 1.82 L13 Longest lead to any 2nd adjacent lead 1.17 C11 Longest lead to VSS 0.63 C12 Longest lead to any 1st adjacent lead 0.30 C13 Longest lead to any 2nd adjacent lead 0.03 Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual ISO9001 nH pF pF 9.18.00 13 FS6158-01 Two-Way/Four Way Motherboard Clock Generator/Buffer IC AMERICAN MICROSYSTEMS, INC. September 2000 8.0 Ordering Information DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION 11915-801 48-pin (0.300") SSOP 0 C to 70 C (Commercial) Tape and Reel 11915-811 48-pin (0.300") SSOP 0 C to 70 C (Commercial) Tubes 11915-201 48-pin (6.1mm) TSSOP 0 C to 70 C (Commercial) Tape and Reel 11915-211 48-pin (6.1mm) TSSOP 0 C to 70 C (Commercial) Tubes FS6158-01 Copyright (c) 1999, 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 9.18.00 14