AMERICAN MICROSYSTEMS, INC.
September 2000
Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
9.18.00
IntWBY
ISO9001
ISO9001ISO9001
ISO9001
FS6158
FS6158FS6158
FS6158-01
-01-01
-01
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er ICTwo-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
1.0 Features
• Generates the Host and Memory clocks required for
2-way and 4-way multi-processor (MP) clock-
partitioned platforms, including:
M Six differential current-mode Host clock pairs
M Two 3.3V Memory Reference clocks
M 66.67MHz and 14.318MHz 3.3V Reference
clocks for the FS6159 device
M Three optional 33.3MHz 1.8V APIC clocks
• Control of current-mode Host clocks via IREF current
programming pin and ISEL_0:1 current multiplier pins
• Optional APIC clocks enabled via APICON input
(see Table 5 for Pins 21-23 configuration)
• Host clock frequency selection via the SEL_A,
SEL_B, and SEL133/100# pins
• Active-low PWR_DWN# signal allows one complete
clock cycle on each clock outputs and then shuts
down the crystal oscillator, PLL, and disables outputs
• Spread-spectrum modulation (-0.5% at 31.5kHz) of
Host, Memory, APIC, and 66MHz Reference clocks,
enabled via SS_EN# input
• Supports test mode and tristate output control to fa-
cilitate board testing
• Available in a 48-pin SSOP and TSSOP
Table 1: Clock Parameters
CLOCK
GROUP #
PINS SUPPLY
VOLTAGE SUPPLY
GROUP FREQ.
(MHz) PHASE SKEW
(MAX)
HOST_P 6 0°
HOST_N 6 3.3V VDD_H 133.33
100.00 180°
100ps
Pair to
Pair
MREF_P 1 0°
MREF_N 1 3.3V VDD_M 66.67
50.00 180° -
66REF 1 3.3V VDD_66 66.67 0° -
14REF 1 3.3V VDD_R 14.318 0° -
APIC
(optional)3 1.8V VDD_A 33.33 0° -
Figure 1: Block Diagram
Crystal
Oscillator
XOUT
XIN
PWR_DWN#
FS6158
66REF
adjust
IREF
14REF
VDD_R
VSS_R
ISEL_0:1
÷6
÷8
APIC_0:2
VDD_A
VSS_A
÷3
÷4
÷4
VSS_M
VDD_M
MREF_P
MREF_N
VDD_66
VSS_66
÷1
÷2
VSS_H
VDD_H
HOST_P1:6
HOST_N1:6
PLL
SEL133/100#
SS_EN#
SEL_A:B
APICON
Control
optional
Figure 2: Pin Configuration
148
2
3
4
5
6
7
8
47
46
45
44
43
42
41
14REF
VDD_R
VSS_R
XOUT
VSS_R
VSS
VSS / APICON
VDD_R
9
10
11
12
13
14
15
16
66REF
VSS_66
SEL133/100#
ISEL_0
ISEL_1
VSS_A
VDD
SEL_A / APIC_0
17
18
19
20
21
22
23
SEL_B / APIC_1
MREF_P
MREF_N 40
39
38
37
36
35
34
33
VSS_H
HOST_N1
VSS_H
HOST_P2
32
31
30
29
IREF
HOST_P6
HOST_N6
VSS_H
24
FS6158-01
VDD_A
SS_EN# / APIC_2
HOST_P5
HOST_P1
VDD_H
25
26
27
28
VDD_I
XIN
VSS_M
VSS_I
HOST_N2
VDD_66
PWR_DWN#
VDD_H
HOST_N5
VDD_H
HOST_N4
HOST_P4
HOST_N3
HOST_P3
VDD_H
VDD_M
Pair 1 Pair 2 Pair 3 Pair 4 Pair 5 Pair 6
AMERICAN MICROSYSTEMS, INC.
September 2000
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Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN TYPE NAME DESCRIPTION SUPPLY
47 DI APICON Enables (logic-high) or disables (logic-low) the optional 1.8V APIC clocks VDD_R
APIC_0 One of three optional APIC clocks, enabled or disabled by APICON VDD_A
21 DIO SEL_A One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
VDD_A,
VDD_H
APIC_1 One of three optional APIC clocks, enabled or disabled by APICON VDD_A
22 DIO SEL_B One of two frequency select inputs, used in combination with SEL133/100#. Input signal levels
are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
VDD_A,
VDD_H
APIC_2 One of three optional APIC clocks, enabled or disabled by APICON VDD_A
23 DIO SS_EN# Active-low spread spectrum enable turns on spread spectrum modulation of PLL clocks. Input
levels are referred to VDD_H (3.3V) if APICON is low, or to VDD_A (1.8V) if APICON is high.
VDD_A,
VDD_H
2 DO 14REF One 14.318MHz clock output, provided as a reference clock to the companion clock device VDD_R
14 DO 66REF One 66.67MHz clock output, provided as a reference clock to the companion clock device VDD_66
27 AI IREF A fixed precision resistor from this pin to ground provides a reference current used for the
differential current-mode HOST clock outputs VDD_I
17, 18 DI ISEL_0
ISEL_1
The logic setting on these two pins selects the multiplying factor of the IREF reference current
for the HOST pair outputs VDD_66
45, 44 AO HOST_P1
HOST_N1
Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1 VDD_H
42, 41 AO HOST_P2
HOST_N2 Host clock pair #2; one of six pairs of current-steering differential current-mode outputs VDD_H
39, 38 AO HOST_P3
HOST_N3 Host clock pair #3; one of six pairs of current-steering differential current-mode outputs VDD_H
36, 35 AO HOST_P4
HOST_N4 Host clock pair #4; one of six pairs of current-steering differential current-mode outputs VDD_H
33, 32 AO HOST_P5
HOST_N5 Host clock pair #5; one of six pairs of current-steering differential current-mode outputs VDD_H
30, 29 AO HOST_P6
HOST_N6 Host clock pair #6; one of six pairs of current-steering differential current-mode outputs VDD_H
8 DO MREF_P One clock in a pair of outputs provided as a reference clock to a memory clock driver VDD_M
9DOMREF_N
One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver VDD_M
24 DI PWR_DWN# Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins. VDD_I
16 DI SEL133/100# Selects 133MHz or 100MHz Host clock frequency VDD_66
11 P VDD 3.3V core power supply -
19 P VDD_A 1.8V power supply for optional APIC clocks or a 3.3V supply to pins 21-23 -
13 P VDD_66 3.3V power supply for 66REF clock output -
28, 34, 40, 46 P VDD_H 3.3V power supply for the differential HOST clock outputs -
25 P VDD_I 3.3V power supply for IREF current reference input -
7 P VDD_M 3.3V power supply for MREF clock outputs -
3, 48 P VDD_R 3.3V power supply for the 14REF clock output and the crystal oscillator -
12 P VSS Core Ground -
15 P VSS_66 Ground for the 66REF clock output -
20 VSS_A Ground for the APIC clock outputs
31, 37, 43 P VSS_H Ground for the differential HOST clock outputs -
26 P VSS_I Ground for IREF current reference input -
10 P VSS_M Ground for the MREF clock outputs -
1, 6 P VSS_R Ground for the 14REF clock output and the crystal oscillator -
4 AI XIN 14.318MHz crystal oscillator input VDD_R
5 AO XOUT 14.318MHz crystal oscillator output VDD_R
AMERICAN MICROSYSTEMS, INC.
September 2000
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2.0 Programming Information
Table 3: Function/Clock Enable Configuration
CONTROL INPUTS (2) CLOCK OUTPUTS (MHz )
PWR_DWN# SEL133/100# SEL_A SEL_B HOST_P1:6 HOST_N1:6 MREF_P,
MREF_N 66REF APIC_0:2
(optional)14REF
1 0 0 0 100.00 100.00 50.00 66.67 33.33 14.318
1 0 0 1 100.00 100.00 low (1) low (1) low (1) low (1)
1 0 1 0 reserved reserved reserved reserved reserved reserved
1 0 1 1 tristate tristate tristate tristate tristate tristate
1 1 0 0 133.33 133.33 66.67 66.67 33.33 14.318
1 1 0 1 reserved reserved reserved reserved reserved reserved
1 1 1 0 reserved reserved reserved reserved reserved reserved
1 1 1 1 XIN÷2 XIN÷2 XIN÷4 XIN÷4 XIN÷8 XIN
0XXX
2× IREF tristate low low low low
1. Certain clock outputs may be disabled through a combination of SEL_A, SEL_B, and SEL133/100# logic states as defined in Table 3. Enabled clocks will continue to run while disabled clocks
are stopped low. Note that if clocks are disabled while active, glitches may occur.
Table 4: Synthesis Error
CLOCK TARGET
(MHz) ACTUAL
(MHz) DEVIATION
(ppm)
100.0000 99.9963 -36.657
HOST_P1:6,
HOST_N1:6 133.3333 133.3072 -195.924
50.0000 49.9982 -36.657
MREF_P,
MREF_N 66.6667 66.6536 -195.924
66REF 66.6667 66.6642 -36.657
APIC_0:2 33.3333 33.3321 -36.657
1. 48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB
standards.
2. Spread spectrum is disabled
Table 5: APICON Control
APICON F REQUENCY SELECT CONTROL / APIC CLOCKS
PIN 47 PIN 21 P IN 22 PIN 23
0SEL_A Input
(LVTTL)
SEL_B Input
(LVTTL)
SS_EN# Input
(LVTTL)
1
APIC_0 Output /
SEL_A Latched
Input
APIC_1 Output /
SEL_B Latched
Input
APIC_2 Output /
SS_EN# Latched
Input
3.0 HOST Buffer Curr ent Control
The current supplied at the HOST outputs is controlled by
two parameters:
1) the value of the programming resistor from the IREF
pin to ground (VSS), and
2) the multiplier factor determined by the logic setting of
the ISEL_0 and ISEL_1 pins.
3.1 Current Reference
The HOST output current is a mirrored and scaled copy
of the reference current flowing through the programming
resistor on the IREF pin. Conceptually, the circuit given in
Figure 2 shows how the mirror current is generated.
The voltage that appears at the IREF pin is one-third of
the voltage at the VDD_I pin. The reference current is
IREF
REF R
I
×
=VDD_I
3
1
.
3.2 Current Scaling
The mirrored reference current can be increased by
adding one or more copies of the mirror current together.
The additional current is controlled by the logic settings
on the ISEL_0 and ISEL_1 pins.
AMERICAN MICROSYSTEMS, INC.
September 2000
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Table 6: Current Multiplier
ISEL_0 ISEL_1 MULTPLIER
00
IO = 5 × IREF
01
IO = 6 × IREF
10
IO = 4 × IREF
11
IO = 7 × IREF
Figure 2: Current Reference Circuit
R
IREF
IREF
Reference
Current I
REF
2R
R
Mirror
Current
Additional
Mirror
Current
HOST_N
ISEL_0:1
HOST_P
1.1V
R
P
R
S
R
P
R
S
VDD_I (3.3V)
Table 7: HOST Current Selection
PROGRAM
RESISTOR
RIREF
REFERENCE
CURRENT
IREF
CURRENT
MULTIPLIER TRACE
IMPEDANCE OUTPUT
VOLTAGE
60Ω0.71V
475Ω (1%) 2.32mA IO = 5 × IREF 50Ω0.59V
60Ω0.85V
475Ω (1%) 2.32mA IO = 6 × IREF 50Ω0.71V
60Ω0.56V
475Ω (1%) 2.32mA IO = 4 × IREF 50Ω0.47V
60Ω0.99V
475Ω (1%) 2.32mA IO = 7 × IREF 50Ω0.82V
30Ω0.75V
221Ω (1%) 5mA IO = 5 × IREF 25Ω0.62V
30Ω0.90V
221Ω (1%) 5mA IO = 6 × IREF 25Ω0.75V
30Ω0.60V
221Ω (1%) 5mA IO = 4 × IREF 25Ω0.50V
30Ω1.05V
221Ω (1%) 5mA IO = 7 × IREF 25Ω0.84V
NOTE: Shaded row indicates the Primary System Configuration
Table 8: HOST Buffer Clock Outputs
HIGH DRIVE CURRENT (mA)
AT PRIMARY SYSTEM CONFIGURATION
Output
Voltage (V) MIN. TYP. MAX.
3.30 0.00 0.00 0.00
3.14 -3.03 -4.22 -5.76
2.97 -5.66 -7.68 -9.86
2.81 -7.87 -10.30 -11.85
2.64 -9.67 -11.91 -12.45
2.48 -11.05 -12.56 -12.84
2.31 -11.98 -12.85 -13.16
2.14 -12.52 -13.07 -13.45
1.98 -12.77 -13.26 -13.72
1.81 -12.91 -13.42 -13.96
1.65 -12.99 -13.54 -14.17
1.48 -13.04 -13.64 -14.36
1.32 -13.07 -13.70 -14.52
1.15 -13.08 -13.73 -14.64
0.99 -13.09 -13.75 -14.71
0.82 -13.11 -13.76 -14.74
0.66 -13.12 -13.78 -14.76
0.49 -13.13 -13.79 -14.78
0.33 -13.13 -13.80 -14.80
0.16 -13.14 -13.81 -14.82
0.00 -13.15 -13.82 -14.83
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
0123
Output Voltage (V)
Output Current (mA)
30Ω
50Ω
90Ω
Max VOH
Data in this table represents nominal characterization data only
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4.0 Power Management
The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that places the device in a low power inac-
tive state without removing power from the device. All
internal clocks are turned off, and all clock outputs are
held low.
Since PWR_DWN# is asynchronous, the signal is syn-
chronized internally to each individual clock. As shown in
Figure 3, a falling-rising-falling edge sequence on any
individual clock output is required before that clock output
is disabled low. This edge sequence ensures that one
complete clock cycle will occur before the clock stops.
Table 9: Latency Table
LATENCY
SIGNAL SIGNAL
STATE MIN. MAX.
Output: 2 clocks 3 clocks
0Power
OFF Device: 2× 14REF
clocks
3× 14REF
clocks
PWR_
DWN#
1Power
ON 3ms
Upon the release of PWR_DWN# (power-up), external
circuitry should allow a minimum of 3ms for the PLL to
lock before enabling any clocks.
Figure 3: PWR_DWN# Timing
Any Clock
(output)
PWR_DWN#
Any Clock
(internal)
VCO
Crystal
Oscillator
After 14REF
output shuts off... 3ms until clock is valid
Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.
5.0 Dual Function I/O Pins
Several pins on this device serve as dual function in-
put/output pins. During the initial application of VDD to
the device, this type of pin functions as an input pin.
Upon completion of power-up, the logic state present on
the pin is latched internally, and the pin is converted to an
output driver.
An external 10kΩ pull-down resistor to ground is required
for a logic low and a 10kΩ pull-up resistor to the clock
output VDD is required for a logic high. The 10kΩ resistor
presents an insignificant load to the output driver that
should not affect the output clock.
Note that the latching of the logic state occurs only on the
application of the chip supply voltage (VDD). The logic
state on the pin is not latched if the PWR_DWN# signal is
used to power-down the device with VDD still applied.
Figure 4: I/O Pin Programming
Clock Trace
Termination
Resistor
Device Solder
Pads
Ground or
Power Via
10k
Ω
Programming
Resistor
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6.0 Electrical Specifications
Table 10: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER SYMBOL MIN. MAX. UNITS
Supply Voltage (VSS = ground) VDD VSS-0.5 7 V
Input Voltage, dc VIVSS-0.5 VDD+0.5 V
Output Voltage, dc VOVSS-0.5 VDD+0.5 V
Input Clamp Current, dc (VI < 0 or VI > VDD)I
IK -50 50 mA
Output Clamp Current, dc (VI < 0 or VI > VDD)I
OK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ125 °C
Lead Temperature (soldering, 10s) 260 °C
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 11: Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Core (VDD) 3.135 3.3 3.465
Clock Buffers
(VDD_66, VDD_H, VDD_I, VDD_M, VDD_R) 3.135 3.3 3.465
Supply Voltage VDD
APIC Clock Buffers (VDD_A) 1.65 1.8 1.95
V
Operating Temperature Range TA070°C
Crystal Resonator Frequency fXTAL 14.316 14.318 14.32 MHz
Crystal Resonator Load Capacitance CXL XIN, XOUT pins 13.5 18 22.5 pF
MREF_P, MREF_N 10 30
APIC_0:2 10 20
66REF 10 20
Load Capacitance CL
14REF 10 20
pF
Load Resistance RL
HOST_P1 to HOST_P6,
HOST_N1 to HOST_N6 20 105 Ω
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Tabl e 12: DC Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs IDD
fHOST = 133MHz; all supplies = 3.465V,
RIREF= 475Ω, IOH = 6 × IREF mA
Supply Current, Static IDDs
PWR_DWN# low, all supplies = 3.465V,
RIREF= 475Ω, IOH = 6 × IREF µA
Digital Inputs (PWR_DWN#, ISEL_0, ISEL_1, SEL133/100#)
High-Level Input Voltage VIH 2.0 VDD+0.3 V
Low-Level Input Voltage VIL VSS-0.3 0.8 V
Input Leakage Current IIL -5 +5 µA
Crystal Oscillator Feedback (XIN)
Threshold Bias Voltage VTH 1.5 V
High-Level Input Current IIH VIH = 3.3V 32 µA
Low-Level Input Current IIL VIL = 0V -32 µA
Crystal Loading Capacitance * CL(xtal)
As seen by an external crystal connected to
XIN and XOUT 13.5 18 22.5 pF
Input Loading Capacitance * CL(XIN)
As seen by an external clock driver on
XOUT; XIN unconnected 36 pF
Crystal Oscillator Drive (XOUT)
High Level Output Source Current IOH VI (XIN) = 3.3V, VO = 0V -8.0 mA
Low Level Output Sink Current IOL VI (XIN) = 0V, VO = 3.3V 8.7 mA
Current Reference (IREF)
Bias Voltage VOH no load 1.1 V
Short Circuit Output Source Current IOH VO = 0V mA
MREF_P, MREF_N, 14REF, and 66REF Clock Outputs (Type 5 Clock Driver)
IOH min
VDD_M, VDD_R, VDD_66 = 3.135V,
VO = 1.0V -33
High Level Output Source Current
IOH max
VDD_M, VDD_R, VDD_66 = 3.465V,
VO = 3.135V -33
mA
IOL min
VDD_M, VDD_R, VDD_66 = 3.135V,
VO = 1.95V 30
Low Level Output Sink Current
IOL max
VDD_M, VDD_R, VDD_66 = 3.465V,
VO = 0.4V 38
mA
zOL Measured at 1.65V, output driving low 12 55
Output Impedance zOH Measured at 1.65V, output driving high 12 55 Ω
Tristate Output Current IOZ -10 10 µA
Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -51 mA
Short Circuit Output Sink Current IOSL VO = 3.3V; shorted for 30s, max. 62 mA
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Table 13: DC Electrical Specifications, continued
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
HOST_P1:4, HOST_N1:4 Clock Outputs (Type X1 Cl ock Buffer)
Crossover Voltage VX
RS = 33.2Ω, RP = 49.9Ω,
RIREF = 475Ω, IOH = 6 × IREF
45 55 %VOH
VO = 0.65V, RIREF = 475Ω, IOH = 6 × IREF 12.9
High-Level Output Source Current IOH VO = 0.74V, RIREF = 475Ω, IOH = 6 × IREF 14.9 mA
VDD = 3.30V, over settings in Table 7 -7 +7
Output Source Current Tolerance ∆IOH VDD_I=3.3V±5%, over settings in Table 7 -12 +12 %IOH
Output Impedance zOH ∆VO/∆IO, where VO1 = 1.0V, VO2 = VSS,
RIREF = 475Ω, IOH = 6 × IREF
3000 Ω
Tristate Output Current IOZ -10 10 µA
SEL_A / APIC_0, SE L_B / APIC_1, and SS_EN# / APIC_3 Latched Inputs / Clock Outputs (1.8V Clock Buffer)
VDD_A = 3.3V, LVTTL Input (APICON=0) 2.0 VDD+0.3
High-Level Input Voltage VIH VDD_A = 1.8V, Latched Input (APICON=1) 1.17 VDD+0.3 V
VDD_A = 3.3V, LVTTL Input (APICON=0) VSS-0.3 0.8
Low-Level Input Voltage VIL VDD_A = 1.8V, Latched Input (APICON=1) VSS-0.3 0.63 V
Input Leakage Current
Input
IIL -5 +5 µA
High Level Output Source Current IOH VDD_A = 1.8V, VO = 1.4V -25 mA
Low Level Output Sink Current IOL VDD_A = 1.8V, VO = 0.4V 24 mA
zOL Measured at 0.7V, output driving low 11 37
Output Impedance zOH Measured at 0.7V, output driving high 18 41 Ω
Tristate Output Current IOZ µA
Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -97 mA
Short Circuit Output Sink Current
Output
IOSL VO = 1.8V; shorted for 30s, max. 64 mA
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
9
ISO9001
ISO9001ISO9001
ISO9001
FS6158
FS6158FS6158
FS6158-01
-01-01
-01
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er ICTwo-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Table 14: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Spread Spectrum Modulation
Frequency * fmSS_EN# low 31.5 kHz
Spread Spectrum Modulation
Index * δmSS_EN# low -0.5 %
Tristate Enable Delay * tDZL, tDZH SEL_A:B=00, SEL133/100#=0 1.0 10 ns
Tristate Disable Delay * tDLZ, tDHZ SEL_A:B=11, SEL133/100#=0 1.0 10 ns
Clock Stabilization (on power-up) * tSTB via PWR_DWN# 3.0 ms
HOST_P1:4, HOST_N1:4 Clock Outputs
Clock Skew * tsk(o)
HOST pair to HOST pair @ VX, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω100 ps
Duty Cycle * dt
Ratio of high pulse width to one clock period at VX,
RIREF = 475Ω, IOH = 6 × IREF, RS=33.2Ω, RP=49.9Ω45 55 %
Jitter, Long Term (σy(τ)) * tj(LT)
On rising edges 500µs apart at VX relative to an
ideal clock, RIREF = 475Ω, IOH = 6 × IREF,
RS = 33.2Ω, RP = 49.9Ωps
Jitter, Period (peak-peak) * tj(∆P)
Rising edge to rising edge at VX,, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω150 ps
Rise Time * tr
Rising edge to rising edge at VX,, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω175 450 ps
Rise/Fall Time Matching* Rising edge to rising edge at VX,, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω20 %
MR EF_P, MR EF_N C loc k O utputs
Duty Cycle * dt
Ratio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Jitter, Long Term (σy(τ)) * tj(LT)
On rising edges 500µs apart at 1.5V relative to an
ideal clock, CL=30pF ps
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL=30pF 250 ps
tr min Measured @ 0.4V – 2.4V; CL=10pF 0.4
Rise Time * tr max Measured @ 0.4V – 2.4V; CL=30pF 1.6 ns
tf min Measured @ 2.4V – 0.4V; CL=10pF 0.4
Fall Time * tf max Measured @ 2.4V – 0.4V; CL=30pF 1.6 ns
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
10
ISO9001
ISO9001ISO9001
ISO9001
FS6158-01
FS6158-01FS6158-01
FS6158-01
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er ICTwo-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Table 15: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
66REF Reference Clock Output
Duty Cycle * dt
Ratio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Jitter, Long Term (σy(τ)) * tj(LT)
On rising edges 500µs apart at 1.5V relative to an
ideal clock, CL=20pF ps
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL=20pF ps
tr min Measured @ 0.4V – 2.4V; CL=10pF 0.5
Rise Time * tr max Measured @ 0.4V – 2.4V; CL=20pF 2.0 ns
tf min Measured @ 2.4V – 0.4V; CL=10pF 0.5
Fall Time * tf max Measured @ 2.4V – 0.4V; CL=20pF 2.0 ns
14REF Reference Clock Output
Duty Cycle * dt
Ratio of high pulse width to one clock period,
measured at 1.5V 45 55 %
Jitter, Long Term (σy(τ)) * tj(LT)
On rising edges 500µs apart at 1.5V relative to an
ideal clock, CL=20pF ps
Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL=20pF ps
tr min Measured @ 0.4V – 2.4V; CL=10pF 0.5
Rise Time * tr max Measured @ 0.4V – 2.4V; CL=20pF 2.0 ns
tf min Measured @ 2.4V – 0.4V; CL=10pF 0.5
Fall Time * tf max Measured @ 2.4V – 0.4V; CL=20pF 2.0 ns
Figure 5: DC Measurement Points
3.3V
V
IH
= 2.0V
V
IL
= 0.8V
V
OH
= 2.4V
V
OL
= 0.4V
Figure 6: Timing Diagram
1.5V
2.4V
0.4V
d
t
t
r
t
f
3.3V
Figure 7: HOST Clock Measurement Point
HOST_P
HOST_N
V
X
Figure 8: HOST Clock Test Point
R
P
R
S
Test node
From output
under test
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
11
ISO9001
ISO9001ISO9001
ISO9001
FS6158
FS6158FS6158
FS6158-01
-01-01
-01
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er ICTwo-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Table 16: MCLK_P, MCLK_N, 14REF, 66REF Clock Outputs
High Drive Current (mA) Low Drive Current (mA)
Voltage
(V) MIN. TYP. MAX.
Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -49 -83 -132
0.2 11 17 24 0.2 -48 -83 -131
0.4 21 32 45 0.4 -48 -82 -130
0.6 30 45 64 0.6 -47 -81 -129
0.8 37 56 79 0.8 -47 -80 -127
1.0 43 65 92 1.0 -46 -79 -126
1.2 47 73 103 1.2 -46 -78 -124
1.4 50 78 112 1.4 -45 -76 -121
1.6 53 82 117 1.6 -43 -74 -117
1.8 54 84 120 1.8 -41 -70 -112
2.0 55 85 121 2.0 -37 -65 -105
2.2 55 85 122 2.2 -33 -59 -97
2.4 55 86 123 2.4 -28 -52 -87
2.6 56 86 123 2.6 -22 -43 -74
2.8 56 86 124 2.8 -14 -32 -60
3.0 56 87 124 3.0 -6 -20 -45
3.2 87 124 3.2 -7 -27
3.4 125 3.4 -7
-150
-125
-100
-75
-50
-25
0
25
50
75
100
125
150
00.511.522.533.5
Output Voltage (V)
Output Current (mA)
30Ω
50Ω
90Ω
Data in this table represents nominal characterization data only
Table 17: APIC_0:2 Clock Outputs
High Drive Current (mA) Low Drive Current (mA)
Voltage
(V) MIN. TYP. MAX.
Voltage
(V) MIN. TYP. MAX.
0 0 0 0 0 -40 -67 -97
0.1 3 5 7 0.1 -37 -62 -92
0.2 6 9130.2-34-58-87
0.3 8 13 19 0.3 -31 -53 -82
0.4 111724 0.4-28-49-76
0.5 132129 0.5-25-45-71
0.6 152434 0.6-22-41-66
0.7 172738 0.7-19-37-61
0.8 193042 0.8-16-33-56
0.9 203246 0.9-14-29-51
1.0 213549 1.0-12-25-46
1.2 243955 1.2 -7-18-36
1.4 264159 1.4 -3-11-26
1.5 264361 1.5 -2 -8-21
1.6 274362 1.6 -1 -5-16
1.7 44 63 1.7 -2 -11
1.8 44 64 1.8 0 -7
1.9 64 1.9 -2
-100
-75
-50
-25
0
25
50
75
100
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
Output Voltage (V)
Output Current (mA)
30Ω
50Ω
90Ω
Data in this table represents nominal characterization data only
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
12
ISO9001
ISO9001ISO9001
ISO9001
FS6158-01
FS6158-01FS6158-01
FS6158-01
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er ICTwo-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
7.0 Package Information
Table 18: 48-pin SSOP (0.300") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.095 0.110 2.41 2.79
A10.008 0.016 0.20 0.41
b 0.008 0.0135 0.20 0.34
c 0.005 0.010 0.13 0.25
D 0.620 0.630 15.75 16.00
E 0.395 0.420 10.03 10.67
E10.291 0.299 7.39 7.59
e 0.025 BSC 0.64 BSC
h 0.015 0.025 0.38 0.64
L 0.020 0.040 0.51 1.01
θ0°8°0°8°
E
E
1
48
1
AMERICAN MICROSYSTEMS, INC.
b
DA
1
SEATING PLANE
A
e
c
L
θ
h × 45°
Table 19: 48-pin SSOP (0.300") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 93 °C/W
Lead Inductance, Self L11 Longest lead 5.5 nH
L12 Longest lead to any 1st adjacent lead 3.0
Lead Inductance, Mutual L13 Longest lead to any 2nd adjacent lead 2.1 nH
Lead Capacitance, Bulk C11 Longest lead to VSS 0.94 pF
C12 Longest lead to any 1st adjacent lead 0.46
Lead Capacitance, Mutual C13 Longest lead to any 2nd adjacent lead 0.05 pF
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
13
ISO9001
ISO9001ISO9001
ISO9001
FS6158
FS6158FS6158
FS6158-01
-01-01
-01
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er ICTwo-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Table 20: 48-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A - 0.047 - 1.20
A10.002 0.006 0.05 0.15
b 0.0067 0.011 0.17 0.27
c 0.0035 0.008 0.09 0.20
D 0.488 0.496 12.40 12.60
E 0.318 BSC 8.10 BSC
E10.236 0.244 6.00 6.20
e 0.019 BSC 0.50 BSC
L 0.018 0.030 0.45 0.75
S 0.008 - 0.20 -
θ10°8°0°8°
θ212° REF 12° REF
θ312° REF 12° REF
E
1
AMERICAN MI CROSY STEM S, IN C.
E
1
48
be
DA
1
SEATING PLANE
Ac
L
θ
1
θ
3
θ
2
S
Table 21: 48-pin TSSOP (6.1mm) Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 89 °C/W
Lead Inductance, Self L11 Longest lead 3.50 nH
L12 Longest lead to any 1st adjacent lead 1.82
Lead Inductance, Mutual L13 Longest lead to any 2nd adjacent lead 1.17 nH
Lead Capacitance, Bulk C11 Longest lead to VSS 0.63 pF
C12 Longest lead to any 1st adjacent lead 0.30
Lead Capacitance, Mutual C13 Longest lead to any 2nd adjacent lead 0.03 pF
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
14
ISO9001
ISO9001ISO9001
ISO9001
FS6158-01
FS6158-01FS6158-01
FS6158-01
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er ICTwo-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
Two-Wa y/Four Way M otherbo ard Cloc k Gene r ator/Bu ff er IC
8.0 Ordering Information
DEVICE NUMBER ORDE RING CODE PACKAGE TYPE OPERATING
TEMPERATURE RANGE SHIPPING
CONFIGURATION
11915-801 48-pin (0.300”) SSOP 0°C to 70°C (Commercial) Tape and Reel
11915-811 48-pin (0.300”) SSOP 0°C to 70°C (Commercial) Tubes
11915-201 48-pin (6.1mm) TSSOP 0°C to 70°C (Commercial) Tape and Reel
FS6158-01
11915-211 48-pin (6.1mm) TSSOP 0°C to 70°C (Commercial) Tubes
Copyright © 1999, 2000 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-
mended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address: http://www.amis.com E-mail: tgp@amis.com
