Ultrafast SiGe
Voltage Comparators
ADCMP580/ADCMP581/ADCMP582
Rev. A
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FEATURES
180 ps propagation delay
25 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
100 ps minimum pulse width
37 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
−2 V to +3 V input range with +5 V/−5 V supplies
On-chip terminations at both input pins
Resistor-programmable hysteresis
Differential latch control
Power supply rejection > 70 dB
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration
FUNCTIONAL BLOCK DIAGRAM
V
P
NONINVERTING
INPUT
V
TP
TERMINATION
V
CCI
V
CCO
V
EE
V
EE
V
TN
TERMINATION
V
N
INVERTING
INPUT
LE INPUTHYS
Q OUTPUT
Q OUTPUT
LE INPUT
ADCMP580/
ADCMP581/
ADCMP582
CML/ECL/
PECL
04672-001
Figure 1.
GENERAL DESCRIPTION
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage
comparators fabricated on the Analog Devices, Inc. proprietary
XFCB3 Silicon Germanium (SiGe) bipolar process. The
ADCMP580 features CML output drivers, the ADCMP581
features reduced swing ECL (negative ECL) output drivers, and
the ADCMP582 features reduced swing PECL (positive ECL)
output drivers.
All three comparators offer 180 ps propagation delay and 100 ps
minimum pulse width for 10 Gbps operation with 200 fs random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 15 ps.
The ±5 V power supplies enable a wide −2 V to +3 V input
range with logic levels referenced to the CML/NECL/PECL
outputs. The inputs have 50 Ω on-chip termination resistors
with the optional capability to be left open (on an individual
pin basis) for applications requiring high impedance input.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to ground. The NECL output
stages are designed to directly drive 400 mV into 50 Ω terminated
to −2 V. The PECL output stages are designed to directly drive
400 mV into 50 Ω terminated to VCCO − 2 V. High speed latch
and programmable hysteresis are also provided. The differential
latch input controls are also 50 Ω terminated to an independent
VTT pin to interface to either CML or ECL or to PECL logic.
The ADCMP580/ADCMP581/ADCMP582 are available in a
16-lead LFCSP_VQ.
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Considerations.............................................................. 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Typical Application Circuits ......................................................... 10
Application Information................................................................ 11
Power/Ground Layout and Bypassing..................................... 11
ADCMP58x Family of Output Stages ..................................... 11
Using/Disabling the Latch Feature........................................... 11
Optimizing High Speed Performance ..................................... 12
Comparator Propagation Delay Dispersion............................... 12
Comparator Hysteresis .............................................................. 13
Minimum Input Slew Rate Requirement................................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
8/07—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Table 4............................................................................ 7
Changes to Figure 9.......................................................................... 8
Changes to Figure 21, Figure 22, and Figure 23 ......................... 10
Changes to Using/Disabling the Latch Feature .......................... 11
Changes to Comparator Hysteresis Section and Figure 29....... 13
Changes to Ordering Guide .......................................................... 14
7/05—Revision 0: Initial Version
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 3 of 16
SPECIFICATIONS
VCCI = 5.0 V; VEE = −5.0 V; VCCO = 3.3 V; TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Condition Min Typ Max Unit
DC INPUT CHARACTERISTICS
Input Voltage Range VP, VN −2.0 +3.0 V
Input Differential Range −2.0 +2.0 V
Input Offset Voltage VOS −10.0 ±4 +10.0 mV
Offset Voltage Temperature Coefficient ΔVOS/dT 10 μV/°C
Input Bias Current IP, INOpen termination 15 30.0 μA
Input Bias Current Temperature Coefficient ΔIB/dT 50 nA/°C
Input Offset Current +2 ±5.0 μA
Input Resistance 47 to 53 Ω
Input Resistance, Differential Mode Open termination 50 kΩ
Input Resistance, Common Mode Open termination 500 kΩ
Active Gain AV 48 dB
Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +3.0 V 60 dB
Hysteresis RHYS = ∞ 1 mV
LATCH ENABLE CHARACTERISTICS
Latch Enable Input Impedance ZIN Each pin, VTT at ac ground 47 to 53 Ω
Latch-to-Output Delay tPLOH, tPLOL VOD = 200 mV 175 ps
Latch Minimum Pulse Width tPL VOD = 200 mV 100 ps
ADCMP580 (CML)
Latch Enable Input Range −0.8 0 V
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time tSVOD = 200 mV 95 ps
Latch Hold Time tHVOD = 200 mV −90 ps
ADCMP581 (NECL)
Latch Enable Input Range −1.8 +0.8 V
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time tSVOD = 200 mV 70 ps
Latch Hold Time tHVOD = 200 mV −65 ps
ADCMP582 (PECL)
Latch Enable Input Range VCCO − 1.8 VCCO − 0.8 V
Latch Enable Input Differential 0.2 0.4 0.5 V
Latch Setup Time tSVOD = 200 mV 30 ps
Latch Hold Time tHVOD = 200 mV −25 ps
DC OUTPUT CHARACTERISTICS
ADCMP580 (CML)
Output Impedance ZOUT 50 Ω
Output Voltage High Level VOH 50 Ω to GND −0.10 0 +0.03 V
Output Voltage Low Level VOL 50 Ω to GND −0.50 −0.40 −0.35 V
Output Voltage Differential 50 Ω to GND 340 395 450 mV
ADCMP581 (NECL)
Output Voltage High Level VOH 50 Ω to −2 V, TA = 125°C −0.99 −0.87 −0.75 V
Output Voltage High Level VOH 50 Ω to −2 V, TA = 25°C −1.06 −0.94 −0.82 V
Output Voltage High Level VOH 50 Ω to −2 V, TA = −55°C −1.11 −0.99 −0.87 V
Output Voltage Low Level VOL 50 Ω to −2 V, TA = 125°C −1.43 −1.26 −1.13 V
Output Voltage Low Level VOL 50 Ω to −2 V, TA = 25°C −1.50 −1.33 −1.20 V
Output Voltage Low Level VOL 50 Ω to −2 V, TA = −55°C −1.55 −1.38 −1.25 V
Output Voltage Differential 50 Ω to −2.0 V 340 395 450 mV
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 4 of 16
Parameter Symbol Condition Min Typ Max Unit
ADCMP582 (PECL) VCCO = 3.3 V
Output Voltage High Level VOH 50 Ω to VCCO − 2 V, TA = 125°C VCCO − 0.99 VCCO − 0.87 VCCO − 0.75 V
Output Voltage High Level VOH 50 Ω to VCCO − 2 V, TA = 25°C VCCO − 1.06 VCCO − 0.94 VCCO − 0.82 V
Output Voltage High Level VOH 50 Ω to VCCO − 2 V, TA = −55°C VCCO − 1.11 VCCO − 0.99 VCCO − 0.87 V
Output Voltage Low Level VOL 50 Ω to VCCO − 2 V, TA = 125°C VCCO − 1.43 VCCO − 1.26 VCCO − 1.13 V
Output Voltage Low Level VOL 50 Ω to VCCO − 2 V, TA = 25°C VCCO − 1.50 VCCO − 1.33 VCCO − 1.20 V
Output Voltage Low Level VOL 50 Ω to VCCO − 2 V, TA = −55°C VCCO − 1.55 VCCO − 1.35 VCCO − 1.25 V
Output Voltage Differential 50 Ω to VCCO − 2.0 V 340 395 450 mV
AC PERFORMANCE
Propagation Delay tPD VOD = 500 mV 180 ps
Propagation Delay Temperature Coefficient ΔtPD/dT 0.25 ps/°C
Propagation Delay Skew—Rising
Transition to Falling Transition
V
OD = 500 mV, 5 V/ns 10 ps
Overdrive Dispersion 50 mV < VOD < 1.0 V 10 ps
10 mV < VOD < 200 mV 15 ps
Slew Rate Dispersion 2 V/ns to 10 V/ns 15 ps
Pulse Width Dispersion 100 ps to 5 ns 15 ps
Duty Cycle Dispersion 5% to 95% 1.0 V/ns, 15 MHz, VCM = 0.0 V 10 ps
Common-Mode Dispersion VOD = 0.2 V, −2 V < VCM < 3 V 5 ps/V
Equivalent Input Bandwidth1BWEQ 0.0 V to 400 mV input,
tR = tF = 25 ps, 20/80
8 GHz
Toggle Rate >50% output swing 12.5 Gbps
Deterministic Jitter DJ VOD = 500 mV, 5 V/ns,
PRBS31 − 1 NRZ, 5 Gbps
15 ps
Deterministic Jitter DJ VOD = 200 mV, 5 V/ns,
PRBS31 − 1 NRZ, 10 Gbps
25 ps
RMS Random Jitter RJ VOD = 200 mV, 5 V/ns, 1.25 GHz 0.2 ps
Minimum Pulse Width PWMIN ΔtPD < 5 ps 100 ps
Minimum Pulse Width PWMIN ΔtPD < 10 ps 80 ps
Rise/Fall Time tR, tF 20/80 37 ps
POWER SUPPLY
Positive Supply Voltage VCCI +4.5 +5.0 +5.5 V
Negative Supply Voltage VEE −5.5 −5.0 −4.5 V
ADCMP580 (CML)
Positive Supply Current IVCCI VCCI = 5.0 V, 50 Ω to GND 6 8 mA
Negative Supply Current IVEE VEE = −5.0 V, 50 Ω to GND −50 −40 −34 mA
Power Dissipation PD50 Ω to GND 230 260 mW
ADCMP581 (NECL)
Positive Supply Current IVCCI VCCI = 5.0 V, 50 Ω to −2 V 6 8 mA
Negative Supply Current IVEE VEE = −5.0 V, 50 Ω to −2 V −35 −25 −19 mA
Power Dissipation PD50 Ω to −2 V 155 200 mW
ADCMP582 (PECL)
Logic Supply Voltage VCCO +2.5 +3.3 +5.0 V
Input Supply Current IVCCI VCCI = 5.0 V, 50 Ω to VCCO − 2 V 6 8 mA
Output Supply Current IVCCO VCCO = 5.0 V, 50 Ω to VCCO − 2 V 44 55 mA
Negative Supply Current IVEE VEE = −5.0 V, 50 Ω to VCCO − 2 V −35 −25 −19 mA
Power Dissipation PD50 Ω to VCCO − 2 V 310 350 mW
Power Supply Rejection (VCCI) PSRVCCI VCCI = 5.0 V + 5% −75 dB
Power Supply Rejection (VEE) PSRVEE VEE = −5.0 V + 5% −60 dB
Power Supply Rejection (VCCO) PSRVCCO VCCO = 3.3 V + 5% (ADCMP582) −75 dB
1 Equivalent input bandwidth assumes a simple first-order input response and is calculated with the following formula: BWEQ = 0.22/(trCOMP2 – trIN2), where trIN is the 20/80
transition time of a quasi-Gaussian input edge applied to the comparator input and trCOMP is the effective transition time digitized by the comparator.
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 5 of 16
TIMING INFORMATION
Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the
terms shown in Figure 2.
50%
50%
V
N
± V
OS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
Q OUTPUT
LATCH ENABLE
t
H
t
PDL
t
PDH
t
PLOH
t
PLOL
t
R
t
F
V
N
V
OD
t
S
t
PL
04672-028
Figure 2. Comparator Timing Diagram
Table 2. Timing Descriptions
Symbol Timing Description
tPDH Input-to-Output High Delay Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low-to-high transition.
tPDL Input-to-Output Low Delay Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high-to-low transition.
tPLOH Latch Enable-to-Output High Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL Latch Enable-to-Output Low Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tHMinimum Hold Time Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
tPL Minimum Latch Enable Pulse Width Minimum time that the latch enable signal must be high to acquire an input signal change.
tSMinimum Setup Time Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
tROutput Rise Time Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
tFOutput Fall Time Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
VNNormal Input Voltage Difference between the input voltages VP and VN for output true.
VOD Voltage Overdrive Difference between the input voltages VP and VN for output false.
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
SUPPLY VOLTAGES
Positive Supply Voltage (VCCI to GND) −0.5 V to +6.0 V
Negative Supply Voltage (VEE to GND) –6.0 V to +0.5 V
Logic Supply Voltage (VCCO to GND) −0.5 V to +6.0 V
INPUT VOLTAGES
Input Voltage −3.0 V to +4.0 V
Differential Input Voltage −2 V to +2 V
Input Voltage, Latch Enable −2.5 V to +5.5 V
HYSTERESIS CONTROL PIN
Applied Voltage (HYS to VEE) −5.5 V to +0.5 V
Maximum Input/Output Current 1 mA
OUTPUT CURRENT
ADCMP580 (CML) −25 mA
ADCMP581 (NECL) −40 mA
ADCMP582 (PECL) −40 mA
TEMPERATURE
Operating Temperature Range, Ambient −40°C to +125°C
Operating Temperature, Junction 125°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CONSIDERATIONS
The ADCMP580/ADCMP581/ADCMP582 16-lead LFCSP
option has a θJA (junction-to-ambient thermal resistance) of
70°C/W in still air.
ESD CAUTION
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Q
LE
PIN 1
INDICATOR
1V
TP
2V
P
3V
N
4V
TN
11 Q
12 GND
10
9GND
5
V
CCI
6
7
LE
8
V
TT
15 GND
16 V
CCI
14 HYS
13 V
EE
ADCMP580
TOP VIEW
(Not to Scale)
0
4672-003
Figure 3. ADCMP580 Pin Configuration
Q
LE
PIN 1
INDICATOR
1V
TP
2V
P
3V
N
4V
TN
11 Q
12 GND
10
9GND
5
V
CCI
6
7
LE
8
V
TT
15 GND
16 V
CCI
14 HYS
13 V
EE
ADCMP581
TOP VIEW
(Not to Scale)
0
4672-004
Figure 4. ADCMP581 Pin Configuration
Q
LE
PIN 1
INDICATOR
1V
TP
2V
P
3V
N
4V
TN
11 Q
12 V
CCO
10
9V
CCO
5
V
CCI
6
7
LE
8
V
TT
15 GND
16 V
CCI
14 HYS
13 V
EE
ADCMP582
TOP VIEW
(Not to Scale)
0
4672-005
Figure 5. ADCMP582 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VTP Termination Resistor Return Pin for VP Input.
2 VPNoninverting Analog Input.
3 VNInverting Analog Input.
4 VTN Termination Resistor Return Pin for VN Input.
5, 16 VCCI Positive Supply Voltage.
6 LE Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of
the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator being
placed into latch mode. LE must be driven in complement with LE.
7 LE Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the
input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the
comparator being placed into latch mode. LE must be driven in complement with LE.
8 VTT Termination Return Pin for the LE/LE Input Pins.
For the ADCMP580 (CML output stage), this pin should be connected to the GND ground.
For the ADCMP581 (ECL output stage), this pin should be connected to the –2 V termination potential.
For the ADCMP582 (PECL output stage), this pin should be connected to the VCCO – 2 V termination potential.
9, 12 GND/VCCO Digital Ground Pin/Positive Logic Power Supply Terminal.
For the ADCMP580/ADCMP581, this pin should be connected to the GND pin.
For the ADCMP582, this pin should be connected to the positive logic power VCCO supply.
10 QInverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog
voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions
(Pin 6 to Pin 7) for more information.
11 Q Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE
descriptions (Pin 6 to Pin 7) for more information.
13 VEE Negative Power Supply.
14 HYS Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a
suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 9 for proper sizing of the HYS
hysteresis control resistor.
15 GND Analog Ground.
Heat Sink
Paddle
N/C The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left
floating for optimal electrical isolation between the package handle and the substrate of the die. It can also
be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal
at package corners is connected to the heat sink paddle.
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = 5.0 V, VEE = −5.0 V, VCCO = 3.3 V, TA = 25°C, unless otherwise noted.
12
0
–4 4
COMMON-MODE (V)
BIAS CURRENT (µA)
10
8
6
4
2
–2 0 2
V
IN
COMMON-MODE BIAS SWEEP
04672-006
Figure 6. Bias Current vs. Common-Mode Voltage
–
0.8
–1.5
–55 145
TEMPERATURE (°C)
OUTPUT (V)
–0.9
–1.0
–1.1
–1.2
–1.3
–1.4
–5 45 95
V
OL
vs. TEMPERATURE
OUTPUT (NECL)
V
OH
vs. TEMPERATURE
OUTPUT (NECL)
04672-007
Figure 7. ADCMP581 Output Voltage vs. Temperature
80
0
0600
–IHYST (µA)
HYSTERESIS (mV)
70
60
50
40
30
20
10
100 200 300 400 500
04672-008
Figure 8. Hysteresis vs. −IHYST
80
0
1 10k
R
HYS
CONTROL RESISTOR (Ω)
HYSTERESIS (mV)
70
60
50
40
30
20
10
10 100 1k
04672-009
Figure 9. Hysteresis vs. RHYS Control Resistor
2.5
1.9
–55 145
TEMPERATURE (°C)
OUTPUT (V)
2.4
2.3
2.2
2.1
2.0
–5 45 95
V
OH
vs. TEMPERATURE
OUTPUT (PECL)
V
OL
vs. TEMPERATURE
OUTPUT (PECL)
04672-010
Figure 10. ADCMP582 Output Voltage vs. Temperature
8
0
–2 4
COMMON-MODE (V)
OFFSET (mV)
7
6
5
4
3
1
2
02
+25°C COMMON-MODE OFFSET SWEEP
–55°C COMMON-MODE OFFSET SWEEP
+125°C COMMON-MODE OFFSET SWEEP
04672-011
Figure 11. A Typical VOS vs. Common-Mode Voltage
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 9 of 16
5
–5
–2 3
V
CM
(V)
PROPAGATION DELAY ERROR (ps)
4
3
2
1
0
–1
–2
–3
–4
–1012
LOT2 CHAR1 RISE
LOT2 CHAR1 FALL
LOT3 CHAR1 RISE
LOT3 CHAR1 FALL
04672-012
Figure 12. ADCMP580 Propagation Delay Error vs. Common-Mode Voltage
M1
04672-013
M1
Figure 13. ADCMP580 Eye Diagram at 7.5 Gbps
18
0
0250
OVERDRIVE (mV)
DISPERSION (ps)
16
14
12
10
8
6
4
2
50 100 150 200
OD DISPERSION RISE
OD DISPERSION FALL
04672-014
Figure 14. Dispersion vs. Overdrive
45
25
–55 125
TEMPERATURE (°C)
t
R
/
t
F
(ps)
43
41
39
37
35
33
31
27
29
–35 –15 5 25 45 65 85 105
QRISE
QRISE
QFALL
QFALL
04672-015
Figure 15. ADCMP581 tR/tF vs. Temperature
M1
500mV
500mV 20ps/DIV
04672-016
M1
Figure 16. ADCMP582 Eye Diagram at 2.5 Gbps
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 10 of 16
TYPICAL APPLICATION CIRCUITS
Q
ADCMP580
Q
V
IN
V
P
V
TP
V
TN
V
N
LATCH
INPUTS
50Ω50Ω
GND
0
4672-017
Figure 17. Zero-Crossing Detector with CML Outputs
Q
ADCMP581
Q
V
P
V
N
V
TT
V
P
V
TP
V
TN
V
N
LATCH
INPUTS
50Ω50Ω
0
4672-018
Figure 18. LVDS to a 50 Ω Back-Terminated (RS) ECL Receiver
HYS
V
EE
50Ω50Ω
ADCMP580
0ΩTO 5kΩ
04672-019
Figure 19. Adding Hysteresis Using the HYS Control
50Ω50Ω
+
–
Q
Q
VIN
V
TH
LATCH
INPUTS
GND
ADCMP580
04672-020
Figure 20. Comparator with −2 to +3 V Input Range
V
P
V
N
V
EE
ADCMP580
50Ω
1kΩ50Ω
CML
04672-021
Figure 21. Disabling the Latch Feature on the ADCMP580
V
P
V
N
ADCMP581
V
TT
V
EE
50Ω50Ω
750Ω
RSECL
V
TT
= –2V
04672-022
Figure 22. Disabling the Latch Feature on the ADCMP581
V
P
V
N
V
TT
= V
CCO
– 2V
V
CCO
ADCMP582
50Ω
750Ω50Ω
RSPECL
04672-023
Figure 23. Disabling the Latch Feature on the ADCMP582
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 11 of 16
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP58x family of comparators is designed for very
high speed applications. Consequently, high speed design
techniques must be used to achieve the specified performance.
It is critically important to use low impedance supply planes,
particularly for the negative supply (VEE), the output supply
plane (VCCO), and the ground plane (GND). Individual supply
planes are recommended as part of a multilayer board. Provid-
ing the lowest inductance return path for the switching currents
ensures the best possible performance in the target application.
It is also important to adequately bypass the input and output
supplies. A 1 µF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.1 µF bypass capacitors should
be placed as close as possible to each of the VEE, VCCI, and VCCO
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be strictly avoided to maximize the
effectiveness of the bypass at high frequencies.
ADCMP58x FAMILY OF OUTPUT STAGES
Specified propagation delay dispersion performance is achieved
by using proper transmission line terminations. The outputs of
the ADCMP580 family comparators are designed to directly
drive 400 mV into 50 Ω cable or microstrip/stripline transmis-
sion lines terminated with 50 Ω referenced to the proper return.
The CML output stage for the ADCMP580 is shown in the
simplified schematic diagram in Figure 24. Each output is
back-terminated with 50 Ω for best transmission line matching.
The outputs of the ADCMP581/ADCMP582 are illustrated in
Figure 25; they should be terminated to −2 V for ECL outputs of
ADCMP581 and VCCO − 2 V for PECL outputs of ADCMP582.
As an alternative, Thevenin equivalent termination networks
can also be used. If these high speed signals must be routed
more than a centimeter, either microstrip or stripline techniques
are required to ensure proper transition times and to prevent
excessive output ringing and pulse width-dependent propagation
delay dispersion.
Q
16mA
50Ω50Ω
Q
GND
V
EE
04672-024
Figure 24. Simplified Schematic Diagram of the ADCMP580 CML Output Stage
GND/V
CCO
V
EE
Q
Q
04672-025
Figure 25. Simplified Schematic Diagram of the
ADCMP581/ADCMP582 ECL/PECL Output Stage
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/LE) are active low for latch mode and are
internally terminated with 50 Ω resistors to the VTT pin. When
using the ADCMP580, VTT should be connected to ground.
When using the ADCMP581, VTT should be connected to −2 V.
When using the ADCMP582, VTT should be connected externally
to VCCO − 2 V, preferably with its own low inductance plane.
When using the ADCMP580, the latch function can be disabled
by connecting the LE pin to VEE with an external pull-down
resistor and by leaving the LE pin to ground. To prevent excessive
power dissipation, the resistor should be 1 kΩ for the ADCMP580.
When using the ADCMP581 comparators, the latch can be
disabled by connecting the LE pin to VEE with an external 750 Ω
resistor and leaving the LE pin connected to −2 V. The idea is to
create an approximate 0.5 V offset using the internal resistor as
half of the voltage divider. The VTT pin should be connected as
recommended.
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 12 of 16
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power, and ground
impedances or other layout issues can severely limit performance
and can cause oscillation. Discontinuities along input and output
transmission lines can also severely limit the specified pulse
width dispersion performance.
For applications in a 50 Ω environment, input and output
matching have a significant impact on data-dependent (or
deterministic) jitter (DJ) and pulse width dispersion
performance. The ADCMP58x family of comparators provides
internal 50 Ω termination resistors for both VP and VN inputs.
The return side for each termination is pinned out separately
with the VTP and VTN pins, respectively. If a 50 Ω termination
is desired at one or both of the VP/VN inputs, the VTP and VTN
pins can be connected (or disconnected) to (from) the desired
termination potential as appropriate. The termination potential
should be carefully bypassed using ceramic capacitors as dis-
cussed previously to prevent undesired aberrations on the input
signal due to parasitic inductance in the termination return
path. If a 50 Ω termination is not desired, either one or both
of the VTP/VTN termination pins can be left disconnected. In this
case, the open pins should be left floating with no external pull
downs or bypassing capacitors.
For applications that require high speed operation but do not
have on-chip 50 Ω termination resistors, some reflections
should be expected, because the comparator inputs can no
longer provide matched impedance to the input trace leading
up to the device. It then becomes important to back-match the
drive source impedance to the input transmission path leading
to the input to minimize multiple reflections. For applications
in which the comparator is less than 1 cm from the driving
signal source, the source impedance should be minimized. High
source impedance in combination with parasitic input capaci-
tance of the comparator could cause undesirable degradation
in bandwidth at the input, thus degrading the overall response.
It is therefore recommended that the drive source impedance
should be no more than 50 Ω for best high speed performance.
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP58x family of comparators has been specifically
designed to reduce propagation delay dispersion over a wide
input overdrive range of 5 mV to 500 mV. Propagation delay
dispersion is a change in propagation delays that results
from a change in the degree of overdrive or slew rate (how far
or fast the input signal exceeds the switching threshold). The
overall result is a higher degree of timing accuracy.
Propagation delay dispersion is a specification that becomes
important in critical timing applications, such as data commu-
nications, automatic test and measurement, instrumentation,
and event-driven applications, such as pulse spectroscopy,
nuclear instrumentation, and medical imaging. Dispersion
is defined as the variation in the overall propagation delay as
the input overdrive conditions are changed (see Figure 26 and
Figure 27). For the ADCMP58x family of comparators, disper-
sion is typically <25 ps, because the overdrive varies from 5 mV
to 500 mV, and the input slew rate varies from 1 V/ns to 10 V/ns.
This specification applies for both positive and negative signals
because the ADCMP58x family of comparators has almost
equal delays for positive- and negative-going inputs.
Q/Q OUTPUT
INPUT VOLTAGE
500mV OVERDRIVE
5mV OVERDRIVE
DISPERSION
V
N
± V
OS
04672-026
Figure 26. Propagation Delay—Overdrive Dispersion
Q/Q OUTPUT
INPUT VOLTAGE
10V/ns
1V/ns
DISPERSION
V
N
± V
OS
0
4672-027
Figure 27. Propagation Delay—Slew Rate Dispersion
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 13 of 16
COMPARATOR HYSTERESIS
Adding hysteresis to a comparator is often desirable in a noisy
environment or when the differential inputs are very small or
slow moving. The transfer function for a comparator with
hysteresis is shown in Figure 28. If the input voltage approaches
the threshold from the negative direction, the comparator
switches from a low to a high when the input crosses +VH/2.
The new switching threshold becomes −VH/2. The comparator
remains in the high state until the threshold −VH/2 is crossed
from the positive direction. In this manner, noise centered on
0 V input does not cause the comparator to switch states unless
it exceeds the region bounded by ±VH/2.
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to
the input. A limitation of this approach is that the amount
of hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and can even
reduce overall stability in some cases.
OUTPUT
INPUT
0V
0
1
+
V
H
2
–V
H
2
0
4672-028
Figure 28. Comparator Hysteresis Transfer Function
The ADCMP58x family of comparators offers a programmable
hysteresis feature that can significantly improve the accuracy
and stability of the desired hysteresis. By connecting an external
pull-down resistor from the HYS pin to VEE, a variable amount
of hysteresis can be applied. Leaving the HYS pin disconnected
disables the feature, and hysteresis is then less than 1 mV, as
specified. The maximum range of hysteresis that can be applied
by using this method is approximately ±70 mV.
Figure 29 illustrates the amount of applied hysteresis as a
function of the external resistor value. The advantage of
applying hysteresis in this manner is improved accuracy,
stability, and reduced component count. An external bypass
capacitor is not required on the HYS pin, and it would likely
degrade the jitter performance of the device.
The hysteresis pin can also be driven by a current source.
It is biased approximately 400 mV above VEE and has an
internal series resistance of approximately 600 Ω.
80
0
1 10k
R
HYS
CONTROL RESISTOR (Ω)
COMPARATOR HYSTERESIS (mV)
70
60
50
40
30
20
10
10 100 1k
04672-029
Figure 29. Comparator Hysteresis vs. RHYS Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENT
As with many high speed comparators, a minimum slew rate
requirement must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This oscil-
lation is due in part to the high input bandwidth of the comparator
and the feedback parasitics inherent in the package. A
minimum slew rate of 50 V/µs should ensure clean output
transitions from the ADCMP58x family of comparators.
The slew rate may be too slow for other reasons. The extremely
high bandwidth of these devices means that broadband noise
can be a significant factor when input slew rates are low. There
is 120 V of thermal noise generated over the bandwidth of the
comparator by the two 50 terminations at room temperature.
With a slew rate of only 50 V/s, the inputs are inside this noise
band for over 2 ps, rendering the comparator’s jitter performance of
200 fs irrelevant. Raising the slew rate of the input signal and/or
reducing the bandwidth over which that resistance is seen at the
input can greatly reduce jitter. Devices are not characterized this
way but simply bypassing a reference input close to the package
can reduce jitter 30% in low slew rate applications.
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 14 of 16
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1
INDICATO
R
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATO
R
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
(BOTTOM VIEW)
*COMPLIANT
TO
JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADCMP580BCP-WP −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G07
ADCMP580BCP–R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G07
ADCMP580BCP–RL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G07
ADCMP580BCPZ-WP1−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G12
ADCMP580BCPZ–R21−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G12
ADCMP580BCPZ–RL71−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G12
ADCMP581BCP-WP −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G09
ADCMP581BCP–R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G09
ADCMP581BCP–RL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G09
ADCMP581BCPZ-WP1−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G11
ADCMP581BCPZ–R21−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G11
ADCMP581BCPZ–RL71−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G11
ADCMP582BCP-WP −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G0B
ADCMP582BCP-R2 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G0B
ADCMP582BCP-RL7 −40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G0B
ADCMP582BCPZ-WP1−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G10
ADCMP582BCPZ-R21−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G10
ADCMP582BCPZ-RL71−40°C to +125°C 16-Lead LFCSP_VQ CP-16-3 G10
EVAL-ADCMP580BCPZ1 Evaluation Board
EVAL-ADCMP581BCPZ1 Evaluation Board
EVAL-ADCMP582BCPZ1 Evaluation Board
1 Z = RoHS Compliant Part.
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 15 of 16
NOTES
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 16 of 16
T
NOTES
©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04672-0-8/07(A)
TTT
