HYUNDAI HY534256A 256Kx4, Fast Page mode DESCRIPTION This family is a 1M bit dynamic RAM organized 262,144 x 4-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode offers high speed of random access memory within the same row. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(45, 50 or 60ns) and power consumption (Normal or Low power). Hyundais advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. FEATURES Fast Page Mode operation e JEDEC standard pinout Read-modify-write Capability 20/26-pin SOJ (300mil) TTL compatible inputs and outputs Single power supply of 5V + 10% /CAS-before-/RAS, /RAS-only, Hidden and Early Write or output enable controlled write Self refresh capability Max. Active power dissipation Fast access time and cycle time Speed Power Speed tRAC tCAC tPC 45 550mW 45 45ns 15ns 30ns 50 495mWw 50 50ns 15ns 33ns 60 440mW 60 60ns 15ns 40ns Refresh cycle Part number Refresh | Normal L-part HY534256A 512 8ms 64ms ORDERING INFORMATION Part Name Refresh Power Package HY534256AJ 512 20/26Pin SOJ HY534256ALJ 512 L-part 20/26Pin SOJ *L : Low power This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied . . Rev.10 / Jan.98 1 Hyundai SemiconductorHYUNDAI FUNCTIONAL BLOCK DIAGRAM HY534256A DQ0 ~ DQ3 {ft ff 4 Data Input Buffer Data Output Buffer <~@OE WE e + \ CAS e _, 4 4 CAS Clock Generator N 4 Ao>| i Cloumn 9 Predecoder a Column Decoder Ai (9) A2 . Sense Amp A3> 2 Refresh Controller /O Gate a A4> | o AS 3 Refresh Counter >| * (9) AG Row Memory Array A7> Vv Decoder 262,144 x 4 9 A8> bey Row Predecoder Sg (9) RAS Clock Substrate Bias Vcc RAS > Generator Generator <@ Vss 256Kx4,FP DRAM Rev.10 / Jan.98HYUNDAI PIN CONFIGURATION (Marking Side) DQo Dat WE RAS NC Oo 0 1 11 AO O Al Q A2q A3 O Vec _ 1 26 2 25 3 24 4 23 5 22 9 18 10 17 11 16 12 15 13 14 KY -1 Vss 1] DQ3 1 DQ2 1 CAS OE 1 A8 rl A7 rl AS rf] AS r] A4 20/26 Pin Plastic SOJ (300mil) PIN DESCRIPTION Pin Name Parameter /RAS Row Address Strobe ICAS Column Address Strobe WE Write Enable /OE Output Enable A0~A8 Address Input DQ0~DQ3 Data In/Out Vec Power (5V) Vss Ground HY534256A 256Kx4,FP DRAM Rev.10 / Jan.984 YUNDAI HY534256A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating Unit TA Ambient Temperature 0 to 70 C TSTG Storage Temperature -55 to 145 C VIN, VOUT Voltage on Any Pin relative to Vss -1.0 to 7.0 V Vcc Voltage on Vcc relative to Vss -1.0 to 7.0 V los Short Circuit Output Current 50 mA Pb Power Dissipation 0.9 Ww TSOLDER Soldering Temperature Time 260-10 C sec Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability RECOMMENDED DC OPERATING CONDITIONS (TA = 0C to 70C ) Symbol Parameter Min Typ Max UNIT Vcc Power Supply Voltage 45 5.0 5.5 Vv VIH Input High Voltage 2.4 - Voec+1.0 Vv VIL Input Low Voltage -1.3 - 0.8 Vv Note : All voltages are referenced to Vss. DC OPERATING CHARACTERISTICS Symbol Parameter Test condition Min Max Unit IL! Input Leakage Current Vss < VIN< Vcc+ 1.0 10 10 A (Any input) All other pins not under test = Vss H ILO Output Leakage Current Vss < VOUT < Vcc 10 10 A (Any input) /RAS &/CAS at VIH H VOL Output Low Voltage loL = 4.2mA - 0.4 Vv VOH Output High Voltage IOH = -5.0mA 2.4 - Vv 256Kx4,FP DRAM Rev.10 / Jan.98HYUNDAI HY534256A DC CHARACTERISTICS (TA =0C to 70C , Vcc = 5V + 10%, Vss = OV, unless otherwise noted.) Symbol Parameter Test condition Speed Max. Unit : . 45 100 Icct Operating Current RAS TAS Cycling 50 90 mA = TRO (min) 60 80 Icc2 TTL Standby /RAS, /CAS 2 VIH(min) 2 mA Current Other inputs > Vss loos /RAS-only Refresh /RAS Cycling,/CAS = VIH 45 100 Current tRC = tRC(mi 80 90 mA = TRE(min) 60 80 : 45 80 Ioc4 Fast Page mode Current] /CAS Cycling, /RAS = VIL tPC = tPC(mi 80 70 mA = 1PE(min) 60 60 Iocs CMOS Standby 1 mA Current /RAS = /CAS 2 Voc -0.2V L-part 200 WA loce /CAS-before-/RAS /RAS & /CAS = 0.2V as 100 Refresh Current tRC = tRC(mi 80 90 mA = HRE(mIn,) 60 80 lcc7 Battery Back-up tRC=125us tRAS < 300 Current (SL-part) /CAS = CBR cycling or 0.2V 300ns A /OE & WE =Vcc- 0.2V H Address = Vcc-0.2V or 0.2V tRAS < 400 DQ0~DQ3 = Vcc-0.2, 0.2V or Open ius Note 1. loc1, leca, Ieca, loce and Icc7 depend on output loading and cycle rates(tRc and tPc). 2. Specified values are obtained with output unloaded. 3. Icc is specified as an average current. In Icc1, Icc3, Icc, address can be changed only once while /RAS=VIL. In Icc4, address can be changed maximum once while /CAS=VIH within one cycle time tPc. 4. Only tRAS(max) = 1s is applied to refresh of battery backup but tRAS(max) = 10s is to applied to normal functional operation. 5. Iec5(max.), lcc7 are applied to L-part only. 256Kx4,FP DRAM Rev.10 / Jan.98HYUNDAI HY534256A AC CHARACTERISTICS (TA = 0 C to 70 C, Vcc = 5V + 10% , VSS = OV, unless otherwise noted.) 45ns 50ns 60ns Symbol Parameter Unit Note Min | Max Min | Max = Min | Max tRC Random read or write cycle time 80 - 90 - 110 - ns tRWC Read-modify-write cycle time 135 - 145 - 165 - ns {PC Fast Page mode cycle time 30 - 33 - 40 - ns tPRWC Fast Page mode read-modify-write cycle time 90 - 90 - 95 - ns tRAC Access time from /RAS - 45 - 50 - 60 ns 4,9,10 tcac Access time from /CAS - 15 - 15 - 15 ns 4,9 tAA Access time from column address - 25 - 27 - 30 ns 4,10 {CPA Access time from /CAS precharge - 30 - 32 - 35 ns 4 tCLz /CAS to output low impedance 0 - 0 - 0 - ns 5 {OFF Output Buffer Turn-off Dealy Time 0 15 0 15 0 20 ns 3 tT Transition time(rise and fall) 2 50 2 50 2 50 ns tRP /RAS precharge time 25 - 25 - 30 - ns tRAS /RAS pulse width 45 10K 50 10K 60 10K ns tRASP /RAS pulse width(Fast Page Mode) 45 | 100K} 50 | 100K} 60 | 100K] ns tRSH /RAS hold time 15 - 15 - 15 - ns tCSH /CAS hold time 45 - 50 - 60 - ns {CAS /CAS pulse width 15 10K 15 10K 20 10K ns tRCD /RAS to /CAS delay time 13 30 13 35 13 45 ns 9 tRAD /RAS to column address delay time 11 20 11 12 11 30 ns 10 tcRP /CAS to /RAS precharge time 5 - 5 - 5 - ns tcP /CAS precharge time 10 - 10 - 10 - ns tASR Row address set-up time 0 - 0 - 0 - ns tRAH Row address hold time 8 - 8 - 10 - ns tASC Column address set-up time 0 - 0 - 0 - ns 13 {CAH Column address hold time 10 - 10 - 15 - ns tAR Column address hold time from /CAS 30 - 35 - 40 - ns tRAL Column address to /RAS lead time 25 - 27 - 30 - ns tRCS Read command set-up time 0 - 0 - 0 - ns tRCH Read command hold time referenced to /CAS 0 - 0 - 0 - ns 6 tRRH Read command hold time referenced to /RAS 0 - 0 - 0 - ns 6 tWCH Write command hold time 10 - 10 - 10 - ns twcR Write command hold time from /RAS 35 - 40 - 50 - ns twP Write command pulse width 10 - 10 - 10 - ns tRWL Write command to /RAS lead time 15 - 15 - 20 - ns 256Kx4,FP DRAM Rev.10 / Jan.98HYUNDAI HY534256A AC CHARACTERISTICS Continued 50ns 60ns 70ns Symbol Parameter Unit Note Min | Max Min | Max = Min | Max tCWL Write command to /CAS lead time 15 - 15 - 15 - ns {Ds Data-in set-up time 0 - 0 - 0 - ns 7 {DH Data-in hold time 10 - 10 - 10 - ns 7 {CHR /CAS Hold Time (CBR Cycle) 10 - 10 - 10 - ns Refresh period(512 cycles) 8 - 8 - 8 - ms 11 tREF Refresh period(L-part) 64 - 64 - 64 - ms 11 twcs Write command set-up time 0 - 0 - 0 - ns 8 tcwD /CAS to /WE delay time 45 - 45 - 45 - ns 8 tRWD /RAS to /WE delay time 75 - 80 - 90 - ns 8 tAWD Column address to /WE delay time 55 - 57 - 60 - ns 8 {CSR /CAS set-up time(CBR cycle) 5 - 5 - 5 - ns {CHR /CAS hold time(CBR cycle) 10 - 10 - 10 - ns tRPC /RAS to /CAS precharge time 10 - 10 - 10 - ns tROH /RAS hold time referenced to /OE 10 - 10 - 10 - ns tOEA /OE access time - 15 - 15 - 15 ns tOED /OE to data delay 10 - 10 - 10 - ns tOEZ Output buffer turn-off delay time from /OE 0 10 0 10 0 10 ns tOEH /OE command hold time 15 - 15 - 15 - ns tCPWD WE delay time from /CAS precharge 52 - 52 - 52 - ns 8 tRHCP /RAS hold time from /CAS precharge 22 - 22 - 22 - ns 256Kx4,FP DRAM Rev.10 / Jan.98HYUNDAI HY534256A NOTE 1. An initial pause of 200pus is required after power-up followed by 8 /RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of 8 /RAS-only refresh cycles are required. 2. AC measurements assume tT=3ns 3. VIH(min.) and ViL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.). 4. Measured at VOH=2.0V and VoL=0.8V with a load equivalent to 2TTL loads and 100pF. 5. tOFF(max.) defines the time at which the output achieves in early write cycles and to /WE leading edge in Read- Modify-Write cycles. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in read-modify-write cycles. 8. twcs, tRWD, tcwD, tAwD and tcPwo are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs => twcsimin.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD > tRWD(min.), tCWD = tcwD(min.), tAWD > tAWD(min), and tCPWD > tcPwDimin.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. Operation within the tRCD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD(max.) limit insures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 11.tREF(max.)=64ms is applied to L-parts only. (HY534256ALJ) CAPACITANCE (TA = 25C, Voc = 5V + 10%, Vss = OV and f=1MHz, unless otherwise noted.) Symbol Parameter Typ. Max Unit CIN1 Input Capacitance (A0~A8) - 5 pF CiN2 Input Capacitance (/RAS, /LCAS,/UCAS, /WE, /OE) - 7 pF Cpa Data Input / Output Capacitance (DQ0~DQ3) - 7 pF 256Kx4,FP DRAM Rev.10 / Jan.98