HARRIS SEMICOND SECTOR August 1991 Gq HARRIS WOE D MM 4302271 00323934 7 MBHAS TSAA CA555, CA555C, LM555C* Timers For Timing Delays & Oscillator Applications in Commercial, Industrial & Military Equipment Features Accurate Timing from Microseconds Through Hours Astable and Monostable Operation * Adjustable Duty Cycle . Output Capable of Sourcing or Sinking up to 200mA Output Capable of Driving TTL Devices @ Normally ON and OFF Outputs High-Temperature Stability ..... seseneee 0.005%/OC Directly Interchangeable with SE555, NE555, MC1555, and MC1455 Applications Precision Timing * Sequential Timing * Time-Delay Generation Pulse Generation Pulse-Width and Position Modulation Pulse Detector Description The CA555 and CA555C are highly stable timers for use in precision timing and oscillator applications. As timers, these monolithic Integrated circuits are capable of producing accurate time delays for periods ranging from microseconds through hours. These devices are also useful for astable oscillator operation and can maintain an accu- rately controlled free-running frequency and duty cycle with only two external resistors and one capacitor. The circults of the CAS55 and CASSSC may be triggered by the falling edge of the wave-form signal, and the output of these circuits can source or sink up to a 200-milliampere current or drive TTL circuits. The CAS55 and CAS555C are supplied in standard 8-lead TO-5 style packages (T suffix), 8-lead TO-5 style packages with dual~in-line formed leads (DIL-CAN, S suffix), 8-lead Smalt Outline package (M suffix), 8-lead dual-in-line plas- tic packages (MINI-DIP, E suffix), and in chip form (H suf- fix). These types are direct replacement for industry types in packages with similar terminal arrangements e.g. SE555 and NESS55, MC1555 and MC1455, respectively. The CA555 type circuits are Intended for applications requiring premium electrical performance. The CA555C type circuits are intended for applications requiring less stringent efectri- cal characteristics. Pinouts Functional Diagram CAS555, CA555C, LM555C 8 PIN MINI-DIP VOLTAGE - TOP VIEW 3) @ taiccen VW cGno [ff [a] v+ Triccer [2] [7] DISCHARGE output [3 6] THRESHOLD B u of Reset [4 3] CONTROL 3 VOLTAGE TO-5 Style Package with Formed Leads CAS555, CA555C, LM555C 8 LEAD METAL CAN TOP VIEW V+ TAB DISCHARGE GND . ~ GNO(1) (7) DISCHARGE TRIGGER (2) (6) THRESHOLD OUTPUT CONTROL Q S VOLTAGE RESET TO-5 Style Package Technkal Data on LM Branded types Is identical (o the cor ding CA Branded types. : File Number 834.1 CAUTION: These devices are sensitive to electrastalic discharghe. Proper I.C, handling procedures should be followed, Copyright Harris Corporation 1991 8-3 ANALOG CIRCUITSHARRIS SEMICOND SECTOR WOE D MM 4302271 0032335 9 EMHAS T-51-19 Specifications CA555, CA555C, LM555C Absolute Maximum Ratings Absolute-Maximum Values Ambient Temperature Range: DC Supply Voltage..........00.eeee veeseeseuseucucceeeese 1sv Operating CA55S......... vee. 559C to +1250C Device Dissipation: CASSSC....005. es0C to +70C UptoTa=+55C .... ce eeeeneeeeneees sseees BOOmW Storage Temperature Range ~65C to +150C Above Ta = +550C ............+.... Derate Linearly 5nw/ocG Lead Temperature (During Soldering): At distance 1/16 + 1/32in. (1.59 + 0.79mm) from case for 108 Max ......eeeseeee $2650C Electrical Characteristics Ta = +259C, V+ = 5V to 18V Unless Otherwise Specified LiMiTs CAS55 CA555C CHARACTERISTICS TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS OC Supply Voltage, V+ 4.5 - 18 4.5 - 16 Vv OC Supply Current V+ = 8V, AL = 09 - 3 5 - 3 6 mA {Low State), Note 1, 1+ V4 = 18V, Rp = co - 10 12 - 10 15 mA Threshold Voltage, VTH - (2/3)V+ - - {2/3)V+ - Vv Trigger Voltage V+=5V 1.45 1.67 1.9 - 1.67 - v V+ = 15V 48 5 .2 - 5 - Vv Trigger Current - 0.5 - - 0.5 - uA Threshold Current, - 041 0.25 - 0O.1 0.25 pA Note 2, itr Reset Voltage 04 0.7 1.0 0.4 0.7 1.0 Vv Reset Current - 0.1 - - 0.1 - mA Control Voltage Leve! V+- 5V 2.9 3.33 3.8 2.6 3.33 4 v V+ = 15V 9.6 10 10.4 9 10 14 Vv Output Voltage Drop: V+ = 5V, ISINK = 5mA - - - - 0.25 0.35 Vv Low State, VoL ISINK = 8mA - 0.1 0.25 - - - Vv V+ = 15V, Isic = 10mA - 0.1 0.15 - 0.1 0.25 v ISINK = 50mA - 0.4 0.5 - 0.4 0.75 v ISINK = 100mA - 2.0 2.2 - 2.0 0.5 Vv IsINK = 200mA - 25 - - 2.5 - v Output Voltage Droop: Vt =5V, 3.0 3.3 - 2.75 3.3 - Vv High State, Vou IlgquRCE =100mA V+ = 15V, 13.0 13.3 - 12.75 13.3 | ~ Vv ISOURCE =100mA . ISOURCE = 200mA - 12.5 - - 12.5 - Vv Timing Error (Monostable): | Ry, Ro = 1k to 100kN, - 05 2 - 1 - % C=0.1uF Tested at Frequency Drift with V+ = 5V, - 30 100 - 50 - p/m/PG Temperature Vt = 15V Drift with Supply Voltage - 0.05 0.2 - 0.1 - NV Ouput Rise Time, tr - 100 - - 100 - ns QOuput Fall Time, t; - 100 - - 100 - ns NOTES: 1. When the output Is in a high state, the DC supply current Is typically 1mA fess than the tow-sfate value. 2. Tha thrashold current will determine the sum of tha values of Ry and Ro to be used in Figure 15 (astable operation}; the maximum total Ry +Ro= 20Mn.HARRIS SEMICOND SECTOR WOE D MM 430ee7h CA555, CA5S5C, LM555C 0032336 O BMHAS T-51-19 MINIMUM PULSE WIDTHns VOLTAGE FIGURE 1. MINIMUM PULSE WIDTH vs MINIMUM TRIGGE! < 4 . 3 b Fy a < = a 3 z a TRIGGER avy * Wwnene a ISTHE CEQMAL MULTIPLIER OF THE SUPPLY VOLTAGE SUPPLY VOLTAGE (vt]- FIGURE 2. SUPPLY CURRENT vs SUPPLY VOLTAGE FLIP-FLOP T oureur THAESHGLD fouTPUT RESISTANCE VALUES ARE iN OHMS FIGURE 3. SCHEMATIC DIAGRAM OF THE CA555 AND CAS555C ANALOG CIRCUITSHARRIS SEMNICOND SECTOR WOE Dd MM 4302271 0032337 2 BBHAS T-51-19 CA555, CA5S55C, LM555C TEMPERATURE yen sarc e250 OUTPUT VOLTAGE SUPPLY VOLTAGE [VFl*SveVteIS t 100 SOURCE CURRENT tT gounce? #8 FIGURE 4, OUTPUT VOLTAGE DROP (HIGH STATE) va SOURCE CURRENT SUPPLY VOLTAGE | a0 VOLTAGE~LOW STATE (Vg v SINK CURREAT (Tginx }mA FIGURE 6. OUTPUT VOLTAGE-LOW STATE vs SINK CURRENT AT V+ = 10V SLT ee a eee eee eae a NORMALIZED DELAY TIME (14) REE REGS eee tes pet is F a Seri Sees 28 3 a rr] SUPPLY VOLTAGE IV) -V FIGURE 8, DELAY TIME vs SUPPLY VOLTAGE PROPAGATION DELAY TIME Cipghas TRIGGER: SUPPLY VOLTAGE ( Sv - 4 i 1 s5re AMBIENT TEMPERATURE Wa OUTPUT VOLTAGE-LOW STATE (VgUIV t SINK CUAREHT (Isinx]mA " FIGURE 5. OUTPUT VOLTAGE-LOW STATE vs SINK CURRENT AT V+ = 5V SUPPLY VOLTAGE (VtIEISY OUTPUT VOLTAGE-LOW STATE {Q1) 2 10 SINK CURRENT (Isiqn }maA FIGURE 7, OUTPUT VOLTAGE-LOW STATE vs SINK CURRENT AT V+ = 15V HB - 2s 2s 50 AMBIENT TEMPERATURE (1%) -C FIGURE 8 DELAY TIME vs TEMPERATURE tayo?" * WHERE IS THE OECIMAL MULTIPLIER OF THE SUPPLY VOLTAGE FIGURE 10. PROPAGATION DELAY TIME vs TRIGGER VOLTAGE 8-6HARRIS SEMICOND SECTOR 4OE D MM 4302271 00323348 4 EMHAS CA555, CA555C, LM555C T-51~19 Typical Applications Reset Timer (Monostable Operation) Figure 11 shows the CA555 connected as a reset timer. In this mode of operation capacitor Cy Is Initially held discharged by a transistor on the integrated circuit. Upon closing the start switch, or applying a negative trigger Pulse to terminal 2, the Integral timer flip-flop is set and releases the short circuit across Ct which drives the output voltage high (relay energized). The action allows the voit- age across the capacitor to increase exponentially with the constant t = RyC7. When the voltage across the capacitor equals 2/3 V+, the comparator resets the flip-flop which in turn discharges the capacitor rapidly and drives the output to its low state. y lOOJAMBIENT TEMPERATURE (Ta}* 25C a RESET sv 4ISUPPLY VOLTAGE (vt}<5V LA L. at ea a ae | : Ce o iF S, 5 4h * Sy w et gt > YS, Indool 2 ar Yi | 7 1 ot # ou : BOSE 10K Q 4b | * 4 ar a RELAY ool a > 680 i of 20.01 pF > Coll tA] A A A, ab Oot EEE Ju tI Pint fit? [| Pty e 46af 2 466] 2 46a! 2 a6al 2 aca 2 468 1o3 074 ALL RESISTANCE VALUES ARE IN OHMS FIGURE 11, RESET TIMER (MONOSTABLE OPERATION) Since the charge rate and threshold level of the are both directly proportional to V+, the timing interval Is relatively Independent of supply voltage variations. Typically, the timing varles only 0.05% for a 1V change in V+. Applying a negative pulse simultaneously to the reset terminal (4) and the trigger terminal (2) during the timing cycle discharges CT and causes the timing cycle to restart. Momentarily closing only the reset switch during the timing Interval discharges CT, but the timing cycle does not restart. Figure 12 shows the typical waveforms generated during this mode of operation, and Figure 13 gives the family of time delay curves with variations In Ry and Cry. Repeat Cycle Timer (Astable Operation) Figure 14 shows the CA555 connected as a repeat cycle timer. In this mode of operation, the total period Is a function of both Rt and R2. . . gy SwitcH StoPEN ENPUT VOLTAGE (TERMINAL 2} SWITCH Si CLOSED Q SWITCH Si CLOSED a3v---~-5 CAPACITOR VOLTAGE (TERMINALS 6,7) VOLTAGE (TERMINAL 3) FIGURE 12. TYPICAL WAVEFORMS FOR RESET TIMER to3 to? ig! ' to TIME DELAY (tp)S FIGURE 13. TIME DELAY vs RESISTANCE AND CAPACITANCE vl + ~---4 FIGURE 14, REPEAT CYCLE TIMER (ASTABLE OPERATIONAL) T= 0.693 (Ry + 2Ro) Cy =ty + to where ty = 0.693 (Ry =Ro) Cr and t2= 0.693 (R2) CT the duty cycle Is: to = Ra ty +to R1+2Ro Typical waveforms generated during this mode of operation are shown in Figure 15. Figure 16 give the family of curves of free running frequency with variations in the value of (Ry + 2Ro) and Cr. 8-7 ANALOG CIRCUITSHARRIS SEMICOND SECTOR 4OE D MM 4302271 0032339 & MBHAS Top Trace: Output voltage (2V/div. and 0.5 ms/div.) CA555, CAS55C, LM555C T-51-] 9 INN EE fo , iol BA \ \ NX dob ce yy NS 1 INNANA Bottom Trace: Capacitor voltage (1 V/ div. and 0.6 ms/div,) FIGURE 15. TYPICAL WAVEFORMS FOR REPEAT CYCLE TIMER . 5, to 102 03 rot 10% FREQUENCYHz FIGURE 16. FREE RUNNING FREQUENCY OF REPEAT CYCLE TIMER WITH VARIATION IN CAPACITANCE AND RESISTANCE